Datasheet

Section 20 Ethernet Controller (EtherC)
Rev. 2.00 Aug. 20, 2008 Page 768 of 1198
REJ09B0403-0200
20.3.5 MAC Address High Register (MAHR)
MAHR is a 32 -bit readable/writable register that specifies the upper 32 bits of the 48-bit MAC
address. The settings in this register are normally made in the initialization process after a reset.
The MAC address setting must not be changed while the transmitting and receiving functions are
enabled. To switch the MAC address setting, return the EtherC and E-DMAC to their initial states
by means of the SWR bit in EDMR before making settings again.
Bit Bit Name
Initial
Value R/W Description
31 to 0 MA47 to MA16 All 0 R/W MAC Address Bits
These bits are used to set the upper 32 bits of the MAC
address.
If the MAC address is 01-23-45-67-89-AB
(hexadecimal), the value set in this register is
H'01234567.
20.3.6 MAC Address Low Register (MALR)
MALR is a 32-bit readable/writable register that specifies the lower 16 bits of the 48-bit MAC
address. The settings in this register are normally made in the initialization process after a reset.
The MAC address setting must not be changed while the transmitting and receiving functions are
enabled. To switch the MAC address setting, return the EtherC and E-DMAC to their initial states
by means of the SWR bit in EDMR before making settings again.
Bit Bit Name
Initial
Value
R/W Description
31 to 16  All 0 R Reserved
These bits are always read as 0. The initial value
should not be changed.
15 to 0 MA15 to MA0 All 0 R/W MAC Address Bits 15 to 0
These bits are used to set the lower 16 bits of the
MAC address.
If the MAC address is 01-23-45-67-89-AB
(hexadecimal), the value set in this register is
H'000089AB.