Datasheet

Section 20 Ethernet Controller (EtherC)
Rev. 2.00 Aug. 20, 2008 Page 770 of 1198
REJ09B0403-0200
20.3.8 PHY Status Register (PSR)
PSR is a read-only register that can read interface signals from the PHY.
Bit Bit Name
Initial
Value
R/W Description
31 to 1  All 0 R Reserved
These bits are always read as 0. The initial value
should not be changed.
0 LMON 0 R LNKSTA Pin Status
The Link status can be read by connecting the Link
signal output from the PHY to the LNKSTA pin. For
the polarity, refer to the PHY specifications to be
connected.
20.3.9 Transmit Retry Over Counter Register (TROCR)
TROCR is a 32-bit counter that indicates the number of frames that were unable to be transmitted
in 16 transmission attempts including the retransmission. When 16 transmission attempts have
failed, TROCR is incremented by 1. When the value in this register reaches H'FFFFFFFF, the
count is halted. The counter value is cleared to 0 by a write to this register with any value.
Bit Bit Name
Initial
Value
R/W Description
31 to 0 TROC31 to
TROC0
All 0 R/W Transmit Retry Over Count
These bits indicate the number of frames that were
unable to be transmitted in 16 transmission attempts
including retransmission.