Datasheet

Section 20 Ethernet Controller (EtherC)
Rev. 2.00 Aug. 20, 2008 Page 771 of 1198
REJ09B0403-0200
20.3.10 Delayed Collision Detect Counter Register (CDCR)
CDCR is a 32-bit counter that indicates the number of delayed collisions on all lines from a start
of transmission. When the value in this register reaches H'FFFFFFFF, count-up is halted. The
counter value is cleared to 0 by a write to this register with any value.
Bit Bit Name
Initial
Value
R/W Description
31 to 0 COSDC31 to
COSDC0
All 0 R/W Delayed Collision Detect Count
These bits indicate the number of delayed collisions
on all lines from a start of transmission.
20.3.11 Lost Carrier Counter Register (LCCR)
LCCR is a 32-bit counter that indicates the number of times the carrier was lost during data
transmission. When the value in this register reaches H'FFFFFFFF, the count is halted. The
counter value is cleared to 0 by writing to this register with any value.
Bit Bit Name
Initial
Value
R/W Description
31 to 0 LCC31 to
LCC0
All 0 R/W Lost Carrier Count
These bits indicate the number of times the carrier
was lost during data transmission.
20.3.12 Carrier Not Detect Counter Register (CNDCR)
CNDCR is a 32-bit counter that indicates the number of times the carrier could not be detected
while the preamble was being sent. When the value in this register reaches H'FFFFFFFF, the count
is halted. The counter value is cleared to 0 by a write to this register with any value.
Bit Bit Name
Initial
Value
R/W Description
31 to 0 CNDC31 to
CNDC0
All 0 R/W Carrier Not Detect Count
These bits indicate the number of times the carrier
was not detected.