Datasheet

Section 20 Ethernet Controller (EtherC)
Rev. 2.00 Aug. 20, 2008 Page 774 of 1198
REJ09B0403-0200
20.3.19 IPG Register (IPGR)
IPGR sets the IPG (Inter Packet Gap). This register must not be changed while the transmitting
and receiving functions of the EtherC mode register (ECMR) are enabled. (For details, refer to
section 20.4.6, Operation by IPG Setting.)
Bit Bit Name
Initial
Value
R/W Description
31 to 5  All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
4 to 0 IPG4 to IPG0 H'13 R/W Inter Packet Gap
Sets the IPG value every 4-bit time.
H'00: 20-bit time
H'01: 24-bit time
: :
H'13: 96-bit time (Initial value)
: :
H'1F: 144-bit time
20.3.20 Automatic PAUSE Frame Set Register (APR)
APR sets the TIME parameter value of the automatic PAUSE frame. When transmitting the
automatic PAUSE frame, the value set in this register is used as the TIME parameter of the
PAUSE frame.
Bit Bit Name
Initial
Value
R/W Description
31 to 16  All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
15 to 0 AP15 to AP0 All 0 R/W Automatic PAUSE
Sets the TIME parameter value of the automatic
PAUSE frame. At this time, 1 bit means 512-bit time.