Datasheet

Section 20 Ethernet Controller (EtherC)
Rev. 2.00 Aug. 20, 2008 Page 780 of 1198
REJ09B0403-0200
4. Following data reception from the RMII, the receiver carries out a CRC check. The result is
indicated as a status bit in the descriptor after the frame data has been written to memory. The
error status is reported in the case of an abnormality.
5. After one frame has been received, if the receive enable bit is set (RE = 1) in the EtherC mode
register, the receiver prepares to receive the next frame.
20.4.3 RMII Frame Timing
(1) RMII Frame Transmission Timing
Timing of RMII frame transmission is shown in figure 20.4.
RM_TXD1
RM_TXD0
RM_REF-CLK
RM_TX-EN
Preamble SFD
Data
000000000010BAEDCGFIH0J
111111111111BAEDCGFIH0J
Figure 20.4 RMII Frame Transmit Timing (Normal Transmission)
(2) RMII Frame Reception Timing
Timing of RMII frame reception is shown in figures 20.5 and 20.6.
RM_RXD1
RM_RXD0
RM_REF-CLK
RM_CRS-DV
PreambleJ K SFD
Data
000000000010BAEDCGFIH0J
000001111111BAEDCGFIH0J
nibble boundary
Figure 20.5 RMII Frame Receive Timing (Normal Reception)