Datasheet

Section 21 Ethernet Controller Direct Memory Access Controller (E-DMAC)
Rev. 2.00 Aug. 20, 2008 Page 792 of 1198
REJ09B0403-0200
Transmit
FIFO
Receive
FIFO
Transmit
descriptor
Transmit
buffer
Receive
buffer
Receive
descriptor
Internal bus
Internal
bus
interface
Descriptor
information
Transmit DMAC
Receive DMAC
Descriptor
information
EtherC
E-DMAC
RAM
Figure 21.1 Configuration of E-DMAC, and Descriptors and Buffers
21.2 Register Descriptions
The E-DMAC has the following registers.
• E-DMAC mode register (EDMR)
• E-DMAC transmit request register (EDTRR)
• E-DMAC receive request register (EDRRR)
• Transmit descriptor list address register (TDLAR)
• Receive descriptor list address register (RDLAR)
• EtherC/E-DMAC status register (EESR)
• EtherC/E-DMAC status interrupt permission register (EESIPR)
• Transmit/receive status copy enable register (TRSCER)
• Receive missed-frame counter register (RMFCR)
• Transmit FIFO threshold register (TFTR)
• FIFO depth register (FDR)
• Receiving method control register (RMCR)