Datasheet

Section 21 Ethernet Controller Direct Memory Access Controller (E-DMAC)
Rev. 2.00 Aug. 20, 2008 Page 801 of 1198
REJ09B0403-0200
Bit Bit Name
Initial
value
R/W Description
18 FR 0 R/W Frame Reception
Indicates that a frame has been received and the
receive descriptor has been updated. This bit is set to
1 each time a frame is received.
0: Frame not received
1: Frame received
17 RDE 0 R/W Receive Descriptor Empty
When receive descriptor empty (RDE = 1) occurs,
receiving can be restarted by setting RACT = 1 in the
receive descriptor and initiating receiving.
0: Receive descriptor active bit RACT = 1 not
detected
1: Receive descriptor active bit RACT = 0 detected
16 RFOF 0 R/W Receive FIFO Overflow
Indicates that the receive FIFO has overflowed during
frame reception.
0: Overflow has not occurred
1: Overflow has occurred
15 to 12  All 0 R Reserved
These bits are always read as 0. The initial value
should not be changed.
11 CND 0 R/W Carrier Not Detect
Indicates the carrier detection status.
0: A carrier is detected when transmission starts
1: A carrier is not detected when transmission starts
10 DLC 0 R/W Detect Loss of Carrier
Indicates that loss of the carrier has been detected
during frame transmission.
0: Loss of carrier not detected
1: Loss of carrier detected
9 CD 0 R/W Delayed Collision Detect
Indicates that a delayed collision has been detected
during frame transmission.
0: Delayed collision not detected
1: Delayed collision detected