Datasheet

Section 21 Ethernet Controller Direct Memory Access Controller (E-DMAC)
Rev. 2.00 Aug. 20, 2008 Page 806 of 1198
REJ09B0403-0200
21.2.8 Transmit/Receive Status Copy Enable Register (TRSCER)
TRSCER specifies whether or not receive status information reported by bits 7 and 4 in the
EtherC/E-DMAC status register is to be indicated in bit RFE in the corresponding descriptor. Bits
in this register correspond to bits 7 and 4 in the EtherC/E-DMAC status register (EESR). When a
bit is cleared to 0, the receive status (bits 7 and 4 in EESR) is indicated in bit RFE of the receive
descriptor. When a bit is set to 1, the occurrence of the corresponding interrupt is not indicated in
the descriptor. After this LSI is reset, all bits are cleared to 0.
Bit Bit Name
Initial
value
R/W Description
31 to 8  All 0 R Reserved
These bits are always read as 0. The initial value
should not be changed.
7 RMAFCE 0 R/W RMAF Bit Copy Directive
0: Indicates the RMAF bit state in bit RFE of the
receive descriptor
1: Occurrence of the corresponding interrupt is not
indicated in bit RFE of the receive descriptor
6, 5  All 0 R Reserved
These bits are always read as 0. The initial value
should not be changed.
4 RRFCE 0 R/W RRF Bit Copy Directive
0: Indicates the RRF bit state in bit RFE of the receive
descriptor
1: Occurrence of the corresponding interrupt is not
indicated in bit RFE of the receive descriptor
3 to 0  All 0 R Reserved
These bits are always read as 0. The initial value
should not be changed.
21.2.9 Receive Missed-Frame Counter Register (RMFCR)
RMFCR is a 16-bit counter that indicates the number of frames missed (discarded, and not
transferred to the receive buffer) during reception. When the receive FIFO overflows, the receive
frames in the FIFO are discarded. The number of frames discarded at this time is counted. When
the value in this register reaches H'FFFF, counting-up is halted. When this register is read, the
counter value is cleared to 0. Write operations to this register have no effect.