Datasheet

Section 21 Ethernet Controller Direct Memory Access Controller (E-DMAC)
Rev. 2.00 Aug. 20, 2008 Page 809 of 1198
REJ09B0403-0200
21.2.11 FIFO Depth Register (FDR)
FDR is a 32-bit readable/writable register that specifies the capacity of the transmit and receive
FIFOs.
Bit Bit Name
Initial
value
R/W Description
31 to 11  All 0 R Reserved
These bits are always read as 0. The initial value
should not be changed.
10 to 8 TFD2 to
TFD0
B’000 R Transmit FIFO Capacity
Specify the capacity of transmit FIFO, from 256 bytes
to 2048 bytes, in 256-byte units. The set value should
not be changed after the transmit/receive operation is
started.
7 to 3  All 0 R Reserved
These bits are always read as 0. The initial value
should not be changed.
2 to 0 RFD2 to
RFD0
B’000 R Receive FIFO Capacity
Specify the capacity of receive FIFO, from 256 bytes
to 2048 bytes, in 256-byte units. The set value should
not be changed after the transmit/receive operation is
started.