Datasheet

Section 21 Ethernet Controller Direct Memory Access Controller (E-DMAC)
Rev. 2.00 Aug. 20, 2008 Page 810 of 1198
REJ09B0403-0200
21.2.12 Receiving method Control Register (RMCR)
RMCR is a 32-bit readable/writable register that specifies the control method for the RR bit in
EDRRR when a frame is received. This register must be set during the receiving-halt state.
Bit Bit Name
Initial
value
R/W Description
31 to 1  All 0 R Reserved
These bits are always read as 0. The initial value
should not be changed.
0 RNC 0 R/W Receive Enable Control
0: When reception of one frame is completed, the E-
DMAC writes the receive status into the descriptor
and clears the RR bit in EDRRR
1: When reception of one frame is completed, the E-
DMAC writes the receive status into the descriptor,
reads the next descriptor, and prepares to receive
the next frame
21.2.13 Receiving-Buffer Write Address Register (RBWAR)
RBWAR stores the address of data to be written in the receiving buffer when the E-DMAC writes
data to the receiving buffer. Which addresses in the receiving buffer are processed by the E-
DMAC can be recognized by monitoring addresses displayed in this register. The address that the
E-DMAC is actually processing may be different from the value read from this register.
Bit Bit Name
Initial
value
R/W Description
31 to 0 RBWA31 to
RBWA0
All 0 R Receiving-Buffer Write Address
These bits can only be read. Writing is prohibited.