Datasheet

Section 21 Ethernet Controller Direct Memory Access Controller (E-DMAC)
Rev. 2.00 Aug. 20, 2008 Page 812 of 1198
REJ09B0403-0200
21.2.17 Flow Control FIFO Threshold Register (FCFTR)
FCFTR is a 32-bit readable/writable register that sets the flow control of the EtherC (setting the
threshold on automatic PAUSE transmission). The threshold can be specified by the depth of the
receive FIFO data (RFD2 to RFD0) and the number of receive frames (RFF2 to RFF0). The
condition to start the flow control is decided by taking OR operation on the two thresholds.
Therefore, the flow control by the two thresholds is independently started.
When flow control is performed according to the RFD bits setting, if the setting is the same as the
depth of the receive FIFO specified by the FIFO depth register (FDR), flow control is started when
the remaining FIFO is (FIFO data depth − 64) bytes. For instance, when RFD in FDR = 0 and
RFD in FCFTR = 0, flow control is started when (256 − 64) bytes of data is stored in the receive
FIFO. The value set in the RFD bits in this register should be equal to or less than those in FDR.
Bit Bit Name
Initial
value
R/W Description
31 to 19  All 0 R Reserved
These bits are always read as 0. The initial value
should not be changed.
18
17
16
RFF2
RFF1
RFF0
1
1
1
R/W
R/W
R/W
Receive Frame Number Flow Control Threshold
000: When 2 receive frame has been stored in the
receive FIFO
001: When 4 receive frames have been stored in the
receive FIFO
: :
110: When 14 receive frames have been stored in the
receive FIFO
111: When 16 receive frames have been stored in the
receive FIFO