Datasheet

Section 21 Ethernet Controller Direct Memory Access Controller (E-DMAC)
Rev. 2.00 Aug. 20, 2008 Page 813 of 1198
REJ09B0403-0200
Bit Bit Name
Initial
value
R/W Description
15 to 3  All 0  Reserved
These bits are always read as 0. The initial value
should not be changed.
2
1
0
RFD2
RFD1
RFD0
1
1
1
R
R
R
Receive Byte Flow Control Threshold
000: When (256 − 32) bytes of data is stored in the
receive FIFO
001: When (512 − 32) bytes of data is stored in the
receive FIFO
: :
110: When (1792 − 32) bytes of data is stored in the
receive FIFO
001: When (2048 − 64) bytes of data is stored in the
receive FIFO
21.2.18 Bit Rate Setting Register (ECBRR)
ECBRR sets the bit rate for retransmission and reception.
Bit Bit Name
Initial
Value
R/W Description
7 to 1  All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
0 RTM 0 R/W Transmit/Receive Rate
0: 10 Mbps
1: 100 Mbps