Datasheet

Section 21 Ethernet Controller Direct Memory Access Controller (E-DMAC)
Rev. 2.00 Aug. 20, 2008 Page 814 of 1198
REJ09B0403-0200
21.2.19 Transmit Interrupt Register (TRIMD)
TRIMD is a 32-bit readable/writable register that specifies whether or not to notify write-back
completion for each frame using the TWB bit in EESR and an interrupt on transmit operations.
Bit Bit Name
Initial
Value
R/W Description
31 to 1  All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
0 TIS 0 R/W Transmit Interrupt Setting
0: Write-back completion for each frame is not
notified
1: Write-back completion for each frame using the
TWB bit in EESR is notified