Datasheet

Section 22 USB Function Module (USB)
Rev. 2.00 Aug. 20, 2008 Page 836 of 1198
REJ09B0403-0200
22.3.2 Interrupt Flag Register 1 (IFR1)
IFR1, together with interrupt flag registers 0 and 2 (IFR0 and IFR2), indicates interrupt status
information required by the application. When an interrupt source is generated, the corresponding
bit is set to 1. And then this bit, in combination with interrupt enable register 1 (IER1), generates
an interrupt request to the CPU. To clear, write 0 to the bit to be cleared and 1 to the other bits.
Bit Bit Name
Initial
Value
R/W Description
7 to 4  All 0 R Reserved
These bits are always read as 0. The initial value
should not be changed.
3 VBUS MN 0 R
This is a status bit which monitors the state of the
VBUS pin.
This bit reflects the state of the VBUS pin and
generates no interrupt request. This bit is always 0
when the PULLUP_E bit in DMA is 0.
2 EP3 TR 0 R/W EP3 Transfer Request
This bit is set if there is no valid transmit data in the
FIFO buffer when an IN token for endpoint 3 is
received from the host. A NAK handshake is returned
to the host until data is written to the FIFO buffer and
packet transmission is enabled.
1 EP3 TS 0 R/W EP3 Transmit Complete
This bit is set when data is transmitted to the host from
endpoint 3 and an ACK handshake is returned.
0 VBUSF 0 R/W USB Disconnection Detection
When the function is connected to the USB bus or
disconnected from it, this bit is set to 1. The VBUS pin
of this module is used for detecting connection or
disconnection.