Datasheet

Section 22 USB Function Module (USB)
Rev. 2.00 Aug. 20, 2008 Page 859 of 1198
REJ09B0403-0200
Table 22.4 Relationship between TRNTREG0 Setting and Pin Output
Pin Input Register Setting Pin Output
VBUS PTSTE txenl txse0 txdata USD+ USD-
0 X X X X Hi-Z Hi-Z
1 0 X X X  
1 1 0 0 0 0 1
1 1 0 0 1 1 0
1 1 0 1 x 0 0
1 1 1 X X Hi-Z Hi-Z
[Legend]
X: Don't care.
: Cannot be controlled. Indicates state in normal operation according to the USB operation
and port settings.
22.3.27 Transceiver Test Register 1 (TRNTREG1)
TRNTREG1 is a test register that can monitor the built-in transceiver input signal.
Setting bits PTSTE and txenl in TRNTREG0 to 1 enables monitoring the built-in transceiver input
signal. Table 22.5 shows the relationship between pin input and TRNTREG1 monitoring value.
Bit Bit Name
Initial
Value
R/W Description
7 to 3  All 0 R
Reserved
These bits are always read as 0. The initial value
should not be changed.
2
1
0
xver_data
dpls
dmns
*
*
*
R
R
R
Built-In Transceiver Input Signal Monitor
xver_data: Monitors the differential input level
(xver_data) signal of the built-in transceiver.
dpls: Monitors the USD+ (dpls) signal of the built-
in transceiver.
dmns: Monitors the USD- (dmns) signal of the built-
in transceiver.
Note: * Determined by the state of pins, VBUS, USD+, and USD-