Datasheet

Section 2 CPU
Rev. 2.00 Aug. 20, 2008 Page 42 of 1198
REJ09B0403-0200
2.6.1 Table of Instructions Classified by Function
Tables 2.3 to 2.10 summarize the instructions in each functional category. The notation used in
tables 2.3 to 2.10 is defined below.
Table 2.2 Operation Notation
Symbol Description
Rd General register (destination)*
Rs General register (source)*
Rn General register*
ERn General register (32-bit register)
MAC Multiply-accumulate register (32-bit register)
(EAd) Destination operand
(EAs) Source operand
EXR Extended control register
CCR Condition-code register
N N (negative) flag in CCR
Z Z (zero) flag in CCR
V V (overflow) flag in CCR
C C (carry) flag in CCR
PC Program counter
SP Stack pointer
#IMM Immediate data
disp Displacement
+ Addition
– Subtraction
× Multiplication
÷ Division
∧ Logical AND
∨ Logical OR
⊕ Logical XOR
→ Move
∼ NOT (logical complement)
:8/:16/:24/:32 8-, 16-, 24-, or 32-bit length
Note: * General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0
to R7, E0 to E7), and 32-bit registers (ER0 to ER7).