Datasheet

Section 23 A/D Converter
Rev. 2.00 Aug. 20, 2008 Page 896 of 1198
REJ09B0403-0200
23.3 Register Descriptions
The A/D converter has the following registers.
• A/D data register A (ADDRA)
• A/D data register B (ADDRB)
• A/D data register C (ADDRC)
• A/D data register D (ADDRD)
• A/D data register E (ADDRE)
• A/D data register F (ADDRF)
• A/D data register G (ADDRG)
• A/D data register H (ADDRH)
• A/D control/status register (ADCSR)
• A/D control register (ADCR)
23.3.1 A/D Data Registers A to H (ADDRA to ADDRH)
The ADDR are eight 16-bit read-only registers, ADDRA to ADDRH, which store the results of
A/D conversion. The ADDR registers, which store a conversion result for each channel, are shown
in table 23.2.
The converted 10-bit data is stored to bits 15 to 6. The lower 6-bit data is always read as 0.
The data bus between the CPU and the A/D converter is 16-bit width and can be read directly
from the CPU. The ADDR must always be accessed in 16-bit unit. They cannot be accessed in 8-
bit unit.
The results of A/D conversion are stored in each registers, when the ADF flag is set to 1.