Datasheet

Section 23 A/D Converter
Rev. 2.00 Aug. 20, 2008 Page 897 of 1198
REJ09B0403-0200
Table 23.2 Analog Input Channels and Corresponding ADDR Registers
Analog Input Channel
A/D Data Register to Store A/D Conversion
Results
AN0 ADDRA
AN1 ADDRB
AN2 ADDRC
AN3 ADDRD
AN4 ADDRE
AN5 ADDRF
AN6 ADDRG
AN7 ADDRH
23.3.2 A/D Control/Status Register (ADCSR)
The ADCSR controls the operation of the A/D conversion.
Bit Bit Name
Initial
Value
R/W Description
7 ADF 0 R/(W)* A/D End Flag
A status flag that indicates the end of A/D conversion.
This flag indicates that the results of A/D conversion are
stored in the A/D data registers.
[Setting conditions]
• When A/D conversion ends in single mode
• When A/D conversion ends on all channels specified
in scan mode
[Clearing conditions]
• When 0 is written after reading ADF = 1
• When DTC starts by an ADI interrupt and ADDR is
read
6 ADIE 0 R/W A/D Interrupt Enable
Enables ADI interrupt by ADF when this bit is set to 1