Datasheet

Section 23 A/D Converter
Rev. 2.00 Aug. 20, 2008 Page 904 of 1198
REJ09B0403-0200
φ
Address
Write signal
Input sampling
timing
ADF
[Legend]
(1): ADCSR write cycle
(2): ADCSR address
t
D
: A/D conversion start delay
t
SPL
: Input sampling time
t
CONV
: A/D conversion time
(2)
(1)
t
D
t
SPL
t
CONV
Figure 23.4 A/D Conversion Timing