Datasheet

Section 25 Flash Memory
Rev. 2.00 Aug. 20, 2008 Page 924 of 1198
REJ09B0403-0200
25.3 Register Descriptions
The registers/parameters which control flash memory are shown in the following. To read from or
write to these registers/parameters, the FLSHE bit in the serial timer control register (STCR) must
be set to 1. For details on STCR, see section 3.2.3, Serial Timer Control Register (STCR).
• Flash code control status register (FCCS)
• Flash program code select register (FPCS)
• Flash erase code select register (FECS)
• Flash key code register (FKEY)
• Flash MAT select register (FMATS)
• Flash transfer destination address register (FTDAR)
• Download pass/fail result (DPFR)
• Flash pass/fail result (FPFR)
• Flash multipurpose address area (FMPAR)
• Flash multipurpose data destination area (FMPDR)
• Flash erase Block select (FEBS)
• Flash programming/erasing frequency control (FPEFEQ)
There are several operating modes for accessing flash memory, for example, read mode/program
mode.
There are two memory MATs: user MAT and user boot MAT. The dedicated registers/parameters
are allocated for each operating mode and MAT selection. The correspondence of operating modes
and registers/parameters for use is shown in table 25.3.