Datasheet
RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: T
A = -40 to +85°C)
Page 91 of 194R01DS0131EJ0310 Rev.3.10
Nov 15, 2013
(6) Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode) (1/2)
(TA = −40 to +85°C, 1.8 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter Symbol Conditions HS (high-
speed main)
Mode
LS (low-speed
main) Mode
LV (low-
voltage main)
Mode
Unit
MIN. MAX. MIN. MAX. MIN. MAX.
Transfer
rate
Recep-
tion
4.0 V ≤ EVDD0 ≤ 5.5 V,
2.7 V ≤ V
b ≤ 4.0 V
f
MCK/6
Note 1
fMCK/6
Note 1
f
MCK/6
Note 1
bps
Theoretical value
of the maximum
transfer rate
f
MCK = fCLK
Note 4
5.3 1.3 0.6 Mbps
2.7 V ≤ EVDD0 < 4.0 V,
2.3 V ≤ V
b ≤ 2.7 V
f
MCK/6
Note 1
fMCK/6
Note 1
f
MCK/6
Note 1
bps
Theoretical value
of the maximum
transfer rate
f
MCK = fCLK
Note 4
5.3 1.3 0.6 Mbps
1.8 V ≤ EVDD0 < 3.3 V,
1.6 V ≤ V
b ≤ 2.0 V
f
MCK/6
Notes 1 to
3
f
MCK/6
Notes 1, 2
f
MCK/6
Notes 1, 2
bps
Theoretical value
of the maximum
transfer rate
f
MCK = fCLK
Note 4
5.3 1.3 0.6 Mbps
Notes 1. Transfer rate in the SNOOZE mode is 4800 bps only.
2. Use it with EVDD0≥Vb.
3. The following conditions are required for low voltage interface when EVDD0 < VDD.
2.4 V ≤ EV
DD0 < 2.7 V : MAX. 2.6 Mbps
1.8 V ≤ EVDD0 < 2.4 V : MAX. 1.3 Mbps
4. The maximum operating frequencies of the CPU/peripheral hardware clock (f
CLK) are:
HS (high-speed main) mode: 32 MHz (2.7 V ≤ V
DD ≤ 5.5 V)
16 MHz (2.4 V ≤ V
DD ≤ 5.5 V)
LS (low-speed main) mode: 8 MHz (1.8 V ≤ VDD ≤ 5.5 V)
LV (low-voltage main) mode: 4 MHz (1.6 V ≤ V
DD ≤ 5.5 V)
Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (V
DD tolerance (When
20- to 52-pin products)/EV
DD tolerance (When 64- to 128-pin products)) mode for the TxDq pin by
using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL,
see the DC characteristics with TTL input buffer selected.
Remarks 1. V
b[V]: Communication line voltage
2. q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 8, 14)
3. f
MCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00 to 03, 10 to 13)
4. UART2 cannot communicate at different potential when bit 1 (PIOR1) of peripheral I/O redirection
register (PIOR) is 1.