Datasheet

RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: T
A = -40 to +85°C)
Page 99 of 194R01DS0131EJ0310 Rev.3.10
Nov 15, 2013
(8) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output)
(3/3)
(TA = −40 to +85°C, 1.8 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter Symbol Conditions HS (high-speed
main) Mode
LS (low-speed
main) Mode
LV (low-voltage
main) Mode
Unit
MIN. MAX. MIN. MAX. MIN. MAX.
SIp setup time
(to SCKp↓)
Note 1
t
SIK1 4.0 V ≤ EVDD0 ≤ 5.5 V,
2.7 V ≤ V
b ≤ 4.0 V,
C
b = 30 pF, Rb = 1.4 kΩ
44
110 110 ns
2.7 V ≤ EVDD0 < 4.0 V,
2.3 V ≤ V
b ≤ 2.7 V,
C
b = 30 pF, Rb = 2.7 kΩ
44
110 110 ns
1.8 V ≤ EVDD0 < 3.3 V,
1.6 V ≤ V
b ≤ 2.0 V
Note 2
,
C
b = 30 pF, Rb = 5.5 kΩ
110
110 110 ns
SIp hold time
(from SCKp↓)
Note 1
t
KSI1 4.0 V ≤ EVDD0 ≤ 5.5 V,
2.7 V ≤ V
b ≤ 4.0 V,
C
b = 30 pF, Rb = 1.4 kΩ
19 19 19
ns
2.7 V ≤ EVDD0 < 4.0 V,
2.3 V ≤ V
b ≤ 2.7 V,
C
b = 30 pF, Rb = 2.7 kΩ
19 19 19
ns
1.8 V ≤ EVDD0 < 3.3 V,
1.6 V ≤ V
b ≤ 2.0 V
Note 2
,
C
b = 30 pF, Rb = 5.5 kΩ
19 19 19
ns
Delay time from SCKp↑
to
SOp output
Note 1
t
KSO1 4.0 V ≤ EVDD0 ≤ 5.5 V,
2.7 V ≤ V
b ≤ 4.0 V,
C
b = 30 pF, Rb = 1.4 kΩ
25 25 25
ns
2.7 V ≤ EVDD0 < 4.0 V,
2.3 V ≤ V
b ≤ 2.7 V,
C
b = 30 pF, Rb = 2.7 kΩ
25 25 25
ns
1.8 V ≤ EVDD0 < 3.3 V,
1.6 V ≤ V
b ≤ 2.0 V
Note 2
,
C
b = 30 pF, Rb = 5.5 kΩ
25 25 25
ns
Notes 1. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
2. Use it with EVDD0 ≥ Vb.
Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (V
DD tolerance (When
20- to 52-pin products)/EV
DD tolerance (When 64- to 128-pin products)) mode for the SOp pin and
SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For
VIH and VIL, see the DC characteristics with TTL input buffer selected.
(Remarks are listed on the next page.)