Datasheet

RL78/G14 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C)
R01DS0053EJ0200 Rev. 2.00 Page 88 of 187
Oct 25, 2013
Note 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.
Note 2. Use it with EVDD0  Vb.
Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance (When 30- to 52-pin
products)/EV
DD tolerance (When 64- to 100-pin products)) mode for the SOp pin and SCKp pin by using port
input mode register g (PIMg) and port output mode register g (POMg). For V
IH and VIL, see the DC characteristics
with TTL input buffer selected.
(Remarks are listed on the page after the next page.)
(8) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock
output)
(T
A = -40 to +85 C, 1.8 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (2/3)
Parameter Symbol Conditions HS (high-speed main)
mode
LS (low-speed main)
mode
LV (low-voltage main)
mode
Unit
MIN. MAX. MIN. MAX. MIN. MAX.
SIp setup time
(to SCKp↑)
Note 1
tSIK1 4.0 V  EVDD0  5.5 V,
2.7 V
 Vb  4.0 V,
C
b = 30 pF, Rb = 1.4 k
81 479 479 ns
2.7 V
 EVDD0 < 4.0 V,
2.3 V
 Vb  2.7 V,
C
b = 30 pF, Rb = 2.7 k
177 479 479 ns
1.8 V
 EVDD0 < 3.3 V,
1.6 V
 Vb  2.0 V
Note 2
,
C
b = 30 pF, Rb = 5.5 k
479 479 479 ns
SIp hold time
(from SCKp↑)
Note 1
tKSI1 4.0 V  EVDD0  5.5 V,
2.7 V
 Vb  4.0 V,
C
b = 30 pF, Rb = 1.4 k
19 19 19 ns
2.7 V
 EVDD0 < 4.0 V,
2.3 V
 Vb  2.7 V,
C
b = 30 pF, Rb = 2.7 k
19 19 19 ns
1.8 V
 EVDD0 < 3.3 V,
1.6 V
 Vb  2.0 V
Note 2
,
C
b = 30 pF, Rb = 5.5 k
19 19 19 ns
Delay time from SCKp↓
to SOp output
Note 1
tKSO1 4.0 V  EVDD0  5.5 V,
2.7 V
 Vb  4.0 V,
C
b = 30 pF, Rb = 1.4 k
100 100 100 ns
2.7 V
 EVDD0 < 4.0 V,
2.3 V
 Vb  2.7 V,
C
b = 30 pF, Rb = 2.7 k
195 195 195 ns
1.8 V
 EVDD0 < 3.3 V,
1.6 V
 Vb  2.0 V
Note 2
,
C
b = 30 pF, Rb = 5.5 k
483 483 483 ns