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R8C/10 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER REJ03B0035-0160 Rev.1.60 Jan 27, 2006 1. Overview This MCU is built using the high-performance silicon gate CMOS process using a R8C/Tiny Series CPU core and is packaged in a 32-pin plastic molded LQFP. This MCU operates using sophisticated instructions featuring a high level of instruction efficiency. With 1M bytes of address space, it is capable of executing instructions at high speed. 1.
R8C/10 Group 1. Overview 1.2 Performance Overview Table 1.1. lists the performance outline of this MCU. Table 1.1 Performance outline Item Performance CPU Number of basic instructions 89 instructions Minimum instruction execution time 62.5 ns (f(XIN) = 16 MHZ, VCC = 3.0 to 5.5 V) 100 ns (f(XIN) = 10 MHZ, VCC = 2.7 to 5.5 V) Operating mode Single-chip Address space 1M bytes Memory capacity See Table 1.
R8C/10 Group 1. Overview 1.3 Block Diagram Figure 1.1 shows this MCU block diagram.
R8C/10 Group 1. Overview 1.4 Product Information Table 1.2 lists the product inforamation. Table 1.2 Product Information As of January 2006 ROM capacity RAM capacity R5F21102FP 8K bytes 512 bytes PLQP0032GB-A R5F21103FP 12K bytes 768 bytes PLQP0032GB-A R5F21104FP 16K bytes 1K bytes PLQP0032GB-A R5F21102DFP 8K bytes 512 bytes PLQP0032GB-A R5F21103DFP 12K bytes 768 bytes PLQP0032GB-A R5F21104DFP 16K bytes 1K bytes PLQP0032GB-A Type No. Type No.
R8C/10 Group 1. Overview 1.5 Pin Assignment Figure 1.3 shows the pin Assignments (top view).
R8C/10 Group 1. Overview 1.6 Pin Description Table 1.3 shows the pin description Table 1.3 Pin description Signal name Power supply input IVcc Pin name Vcc, Vss IVcc Analog power supply input AVcc, AVss Reset input CNVss MODE Main clock input RESET CNVss MODE XIN I/O type I O I Power supply input pins for A/D converter. Connect the AVcc pin to Vcc. Connect the AVss pin to Vss. Connect a capacitor between pins AVcc and AVss. I I I I Input “L” on this pin resets the MCU.
R8C/10 Group 2. Central Processing Unit (CPU) 2. Central Processing Unit (CPU) Figure 2.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB comprise a register bank. Two sets of register banks are provided.
R8C/10 Group 2. Central Processing Unit (CPU) 2.2 Address Registers (A0 and A1) A0 is a 16-bit register for address register indirect addressing and address register relative addressing. They also are used for transfer, arithmetic and logic operations. The same applies to A1 as A0. A0 can be combined with A0 to be used as a 32-bit address register (A1A0). 2.3 Frame Base Register (FB) FB is a 16-bit register for FB relative addressing. 2.
R8C/10 Group 3. Memory 3. Memory Figure 3.1 is a memory map of this MCU. This MCU provides 1-Mbyte address space from addresses 0000016 to FFFFF16. The internal ROM is allocated lower addresses beginning with address 0FFFF16. For example, a 16Kbyte internal ROM is allocated addresses from 0C00016 to 0FFFF16. The fixed interrupt vector table is allocated addresses 0FFDC16 to 0FFFF16. They store the starting address of each interrupt routine.
R8C/10 Group 4. Special Function Register (SFR) 4. Special Function Register (SFR) SFR(Special Function Register) is the control register of peripheral functions. Tables 4.1 to 4.4 list the SFR information Table 4.
R8C/10 Group 4. Special Function Register (SFR) Table 4.
R8C/10 Group 4. Special Function Register (SFR) Table 4.
R8C/10 Group 4. Special Function Register (SFR) Table 4.
R8C/10 Group 5. Electrical Characteristics 5. Electrical Characteristics Table 5.1 Absolute Maximum Ratings Condition Rated value Unit VCC Symbol Supply voltage Parameter VCC=AVCC -0.3 to 6.5 V AVCC Analog supply voltage VCC=AVCC -0.3 to 6.5 V VI Input voltage -0.3 to VCC+0.3 V VO Output voltage -0.3 to VCC+0.3 V Pd Power dissipation 300 mW Topr Operating ambient temperature -20 to 85 / -40 to 85 (D version) C Tstg Storage temperature Topr=25 C C -65 to 150 Table 5.
R8C/10 Group 5. Electrical Characteristics Table 5.3 A/D Conversion Characteristics Symbol Parameter – Resolution – Absolute accuracy Standard Unit Min. Typ. Max. Measuring condition Vref =VCC 10 Bit 10 bit mode øAD=10 MHz, Vref=Vcc=5.0V ±3 LSB 8 bit mode øAD=10 MHz, Vref=Vcc=5.0V ±2 LSB 10 bit mode øAD=10 MHz, Vref=Vcc=3.3V(3) ±5 LSB 8 bit mode øAD=10 MHz, Vref=Vcc=3.
R8C/10 Group 5. Electrical Characteristics P0 P1 30pF P2 P3 P4 Figure 5.1 Port P0 to P4 measurement circuit Erase-suspend request (interrupt request) FMR46 td(SR-ES) Figure 5.2 Time delay from Suspend Request until Erase Suspend Rev.1.
R8C/10 Group 5. Electrical Characteristics Table 5.6 Electrical Characteristics (1) [Vcc=5V] Measuring condition Parameter Symbol "H" output voltage Except XOUT IOH=-5mA IOH=-200µA XOUT Drive capacity HIGH Drive capacity LOW VOH "L" output voltage IOH=-1 mA IOH=-500µA Standard Typ. Max. VCC-2.0 VCC-0.3 VCC-2.0 VCC-2.0 Unit VCC VCC VCC VCC V V 2.0 V V V Except P10 to P17, XOUT IOL= 5 mA IOL= 200 µA 0.45 V P10 to P17 Drive capacity HIGH IOL= 15 mA 2.
R8C/10 Group 5. Electrical Characteristics Table 5.
R8C/10 Group 5. Electrical Characteristics Timing requirements (Unless otherwise noted: VCC = 5V, VSS = 0V at Topr = 25 °C) [VCC=5V] Table 5.8 XIN input Symbol tC(XIN) tWH(XIN) tWL(XIN) Parameter XIN input cycle time XIN input HIGH pulse width XIN input LOW pulse width Standard Min. Max. 62.5 – 30 – 30 – Unit Standard Min. Max. 100 – 40 – 40 – Unit Standard Min. Max. 400(1) – 200(2) – 200(2) – Unit ns ns ns ________ Table 5.
R8C/10 Group 5. Electrical Characteristics VCC = 5V tc(CNTR0) tWH(CNTR0) CNTR0 input tWL(CNTR0) tc(TCIN) tWH(TCIN) TCIN input tWL(TCIN) tc(XIN) tWH(XIN) XIN input tWL(XIN) tc(CK) tW(CKH) CLKi tW(CKL) th(C-Q) TxDi td(C-Q) tsu(D-C) RxDi tW(INL) INTi tW(INH) Figure 5.3 Vcc=5V timing diagram Rev.1.
R8C/10 Group 5. Electrical Characteristics Table 5.13 Electrical Characteristics (3) Symbol [Vcc=3V] Measuring condition Parameter "H" output voltage VOH "L" output voltage VOL Except XOUT IOH=-1mA XOUT Drive capacity HIGH Drive capacity LOW Except P10 to P17, XOUT I O L= 1 m A P10 to P17 Drive capacity HIGH Drive capacity LOW XOUT Drive capacity HIGH Drive capacity LOW VT+-VT- Hysteresis II H "H" input current IOH=-0.
R8C/10 Group 5. Electrical Characteristics Table 5.14 Electrical Characteristics (4) Symbol [Vcc=3V] Measuring condition Parameter 5 XIN=16 MHz (square wave) On-chip oscillator on=125 kHz Division by 8 2 .5 XIN=10 MHz (square wave) On-chip oscillator on=125 kHz Division by 8 1 .
R8C/10 Group 5. Electrical Characteristics Timing requirements (Unless otherwise noted: VCC = 3V, VSS = 0V at Topr = 25 °C) [VCC=3V] Table 5.15 XIN input Symbol tC(XIN) tWH(XIN) tWL(XIN) Parameter XIN input cycle time XIN input HIGH pulse width XIN input LOW pulse width Standard Min. Max. 100 – 40 – 40 – Unit Standard Min. Max. 300 – 120 – 120 – Unit Standard Min. Max. 1200(1) – 600(2) – 600(2) – Unit ns ns ns ________ Table 5.
R8C/10 Group 5. Electrical Characteristics VCC = 3V tc(CNTR0) tWH(CNTR0) CNTR0 input tWL(CNTR0) tc(TCIN) tWH(TCIN) TCIN input tWL(TCIN) tc(XIN) tWH(XIN) XIN input tWL(XIN) tc(CK) tW(CKH) CLKi tW(CKL) th(C-Q) TxDi td(C-Q) tsu(D-C) RxDi tW(INL) INTi tW(INH) Figure 5.4 Vcc=3V timing diagram Rev.1.
R8C/10 Group Package Dimensions Package Dimensions JEITA Package Code P-LQFP32-7x7-0.80 RENESAS Code PLQP0032GB-A Previous Code 32P6U-A MASS[Typ.] 0.2g HD *1 D 24 17 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. 16 25 bp c c1 HE *2 E b1 Reference Symbol 9 1 ZE Terminal cross section 32 8 ZD c A A1 F A2 Index mark L D E A2 HD HE A A1 bp b1 c c1 L1 y e Rev.1.
REVISION HISTORY Rev. R8C/10 Group Datasheet Date Description Summary Page 1.00 Jun. 19, 2003 First edition issued 1.10 Sep. 08, 2003 2 5 6 12 14 Table 1.1: Shortest instruction execution time ____________ and f(XIN) changed Figure 1.3: Pin name changed from TXOUT to____________ CNTR0 Table 1.3: Pin name changed from TXOUT to CNTR0 The value of Time C register after reset changed Chapter “5. Electrical Characteristics” added 1.20 Oct. 31, 2003 2 6 14 15 16 18 23 24 Table 1.
REVISION HISTORY Rev. R8C/10 Group Datasheet Date Description Summary Page 1.50 Apr.27.2005 12 15 17 21 25 1.60 Jan.27.2006 2 3 4 6 7-8 10 11 12 13 14 15 17 18 21 22 Table 4.3 revised Table 5.3 partly revised Table 5.4 partly added Table 5.5 partly revised Table 5.6 partly revised Table 5.13 partly revised Package Dimensions revised Table 1.1 Performance outline revised Figure 1.1 Block diagram partly revised 1.4 Product Information, title of Table 1.
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