Datasheet
R8C/10 Group 2. Central Processing Unit (CPU)
Rev.1.60 Jan 27, 2006 page 7 of 25
REJ03B0035-0160
2. Central Processing Unit (CPU)
Figure 2.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB
comprise a register bank. Two sets of register banks are provided.
2.1 Data Registers (R0, R1, R2 and R3)
R0 is a 16-bit register for transfer, arithmetic and logic operations. The same applies to R1 to R3. The
R0 can be split into high-order bit (R0H) and low-order bit (R0L) to be used separately as 8-bit data
registers. The same applies to R1H and R1L as R0H and R0L. R2 can be combined with R0 to be
used as a 32-bit data register (R2R0). The same applies to R3R1 as R2R0.
Data registers
(1)
Address registers
(1)
Frame base registers
(1)
Program counter
Interrupt table register
User stack pointer
Interrupt stack pointer
Static base register
Flag register
NOTES:
1.
A re
g
ister bank com
p
rises these re
g
isters. Two sets of re
g
ister banks are
p
rovided
R
0
H
(
h
i
g
h
-
o
r
d
e
r
o
f
R
0
)
b
1
5
b
8
b7 b
0
R
3
I
N
T
B
H
USP
ISP
SB
CDZSBOIU
IPL
R
0
L
(
h
i
g
h
-
o
r
d
e
r
o
f
R
0
)
R1H (high-order of R1)
R1L (high-order of R1)
R
2
b
3
1
R
3
R2
A
1
A
0
F
B
b
1
9
I
N
T
B
L
b
1
5
b
0
P
C
b
1
9
b
0
b15 b0
FLG
b15 b0
b15 b0 b7 b8
Reserved bit
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved bit
Processor interrupt priority level
The 4-high order bits of INTB are INTBH and
the 16-low bits of INTB are INTBL.
Figure 2.1 CPU Register