Datasheet

R8C/26 Group, R8C/27 Group 1. Overview
Rev.2.10 Sep 26, 2008 Page 4 of 69
REJ03B0168-0210
1.3 Block Diagram
Figure 1.1 shows a Block Diagram.
Figure 1.1 Block Diagram
R8C CPU core
A/D converter
(10 bits
× 12 channels)
UART or
clock synchronous serial I/O
(8 bits × 2 channels)
Memory
Watchdog timer
(15 bits)
ROM
(1)
RAM
(2)
Multiplier
R0H R0L
R1H
R2
R3
R1L
A0
A1
FB
SB
USP
ISP
INTB
PC
FLG
I/O ports
NOTES:
1. ROM size varies with MCU type.
2. RAM size varies with MCU type.
3. XCIN, XCOUT can be used only for N or D version.
I
2
C bus interface or clock synchronous
serial I/O with chip select
(8 bits × 1 channel)
LIN module
(1 channel)
System clock
generation circuit
XIN-XOUT
High-speed on-chip oscillator
Low-Speed on-chip oscillator
XCIN-XCOUT
(3)
Timers
Timer RA (8 bits)
Timer RB (8 bits)
Timer RC
(16 bits × 1 channel)
Timer RE (8 bits)
8
Port P0
8
Port P1
6
Port P3
1 3
Port P4
2
Port P5
Peripheral functions