Datasheet

R01DS0190EJ0100 Rev.1.00 Page 76 of 107
Jun 19, 2013
RX111 Group 5. Electrical Characteristics
5.3.5 Timing of On-Chip Peripheral Modules
Note 1. t
Pcyc
: PCLK cycle
Note 2. t
cac
: CAC count clock source cycle
Note 3. When the LOCO is selected as the clock output source (CKOCR.CKOSEL[2:0] bits = 000b), set the clock output division ratio
selection to divided by 2 (CKOCR.CKODIV[2:0] bits = 001b).
Note 4. When the EXTAL external clock input or an oscillator is used with divided by 1 (CKOCR.CKOSEL[2:0] bits = 010b and
CKOCR.CKODIV[2:0] bits = 000b) to output from CLKOUT, the above should be satisfied with an input duty cycle of 45 to 55%.
Table 5.30 Timing of On-Chip Peripheral Modules (1)
Conditions: VCC = AVCC0 = VCC_USB = 1.8 to 3.6 V, VSS = AVSS0 = VREFL0 = VSS_USB = 0 V, T
a
= –40 to +105°C
Item Symbol Min. Max. Unit*
1
Test
Conditions
I/O ports Input data pulse width t
PRW
1.5 — t
Pcyc
Figure 5.33
MTU2 Input capture input pulse width Single-edge setting t
TICW
1.5 — t
Pcyc
Figure 5.34
Both-edge setting 2.5 —
Timer clock pulse width Single-edge setting t
TCKWH,
t
TCKWL
1.5 — t
Pcyc
Figure 5.35
Both-edge setting 2.5 —
Phase counting mode 2.5 —
POE POE# input pulse width t
POEW
1.5 — t
Pcyc
Figure 5.36
SCI Input clock cycle Asynchronous t
Scyc
4—t
Pcyc
Figure 5.37
Clock synchronous 6 —
Input clock pulse width t
SCKW
0.4 0.6 t
Scyc
Input clock rise time t
SCKr
—20ns
Input clock fall time t
SCKf
—20ns
Output clock cycle Asynchronous t
Scyc
16 — t
Pcyc
Figure 5.38
Clock synchronous 4 —
Output clock pulse width t
SCKW
0.4 0.6 t
Scyc
Output clock rise time t
SCKr
—20ns
Output clock fall time t
SCKf
—20ns
Transmit data delay time
(master)
Clock synchronous t
TXD
—40ns
Transmit data delay time
(slave)
Clock
synchronous
2.7 V or above — 65 ns
1.8 V or above — 100 ns
Receive data setup time
(master)
Clock
synchronous
2.7 V or above t
RXS
65 — ns
1.8 V or above 90 — ns
Receive data setup time
(slave)
Clock synchronous 40 — ns
Receive data hold time Clock synchronous t
RXH
40 — ns
A/D
converter
Trigger input pulse width t
TRGW
1.5 — t
Pcyc
Figure 5.39
CAC CACREF input pulse width t
Pcyc
≤ t
cac
*
2
t
CACREF
4.5 t
cac
+ 3 t
Pcyc
—ns
t
Pcyc
> t
cac
*
2
5 t
cac
+ 6.5 t
Pcyc
CLKOUT CLKOUT pin output cycle*
4
VCC = 2.7 V or above t
Ccyc
125 — ns
VCC = 1.8 V or above 250
CLKOUT pin high pulse width*
3
VCC = 2.7 V or above t
CH
35 — ns
VCC = 1.8 V or above 70
CLKOUT pin low pulse width*
3
VCC = 2.7 V or above t
CL
35 — ns
VCC = 1.8 V or above 70
CLKOUT pin output rise time VCC = 2.7 V or above t
Cr
—15ns
VCC = 1.8 V or above 30
CLKOUT pin output fall time VCC = 2.7 V or above t
Cf
—15ns
VCC = 1.8 V or above 30