Datasheet

R01DS0190EJ0100 Rev.1.00 Page 78 of 107
Jun 19, 2013
RX111 Group 5. Electrical Characteristics
Note 1. t
Pcyc
: PCLK cycle
Table 5.32 Timing of On-Chip Peripheral Modules (3)
Conditions: VCC = AVCC0 = VCC_USB = 1.8 to 3.6 V, VSS = AVSS0 = VREFL0 = VSS_USB = 0 V, T
a
= –40 to +105°C
Item Symbol Min. Max. Unit*
1
Test Conditions
Simple
SPI
SCK clock cycle output (master) t
SPcyc
4 65536 t
Pcyc
Figure 5.41
SCK clock cycle input (slave) 6 65536
SCK input clock high pulse width t
SPCKWH
0.4 0.6 t
SPcyc
SCK input clock low pulse width t
SPCKWL
0.4 0.6 t
SPcyc
SCK clock rise/fall time t
SPCKr,
t
SPCKf
—20ns
Data input setup time (master) 2.7 V or above t
SU
65 — ns Figure 5.42,
Figure 5.43
1.8 V or above 95 —
Data input setup time (slave) 40 —
Data input hold time t
H
40 — ns
SSL input setup time t
LEAD
3—t
Pcyc
SSL input hold time t
LAG
3—t
Pcyc
Data output delay time (master) t
OD
—40ns
Data output delay time (slave) 2.7 V or above — 65
1.8 V or above — 85
Data output hold time (master) 2.7 V or above t
OH
–10 — ns
1.8 V or above –20 —
Data output hold time (slave) –10 —
Data rise/fall time t
Dr,
t
Df
—20ns
SSL input rise/fall time t
SSLr,
t
SSLf
—20ns
Slave access time t
SA
—6t
Pcyc
Figure 5.44,
Figure 5.45
Slave output release time t
REL
—6t
Pcyc