Datasheet
R01DS0190EJ0100 Rev.1.00 Page 77 of 107
Jun 19, 2013
RX111 Group 5. Electrical Characteristics
Note 1. t
Pcyc
: PCLK cycle
Note 2. N: An integer from 1 to 8 that can be set by the RSPI clock delay register (SPCKD)
Note 3. N: An integer from 1 to 8 that can be set by the RSPI slave select negation delay register (SSLND)
Table 5.31 Timing of On-Chip Peripheral Modules (2)
Conditions: VCC = AVCC0 = VCC_USB = 1.8 to 3.6 V, VSS = AVSS0 = VREFL0 = VSS_USB = 0 V, T
a
= –40 to +105°C,
C = 30 pF
Item
Symbol Min. Max. Unit Test
Conditions
RSPI RSPCK clock
cycle
Master t
SPcyc
24096t
Pcyc
*
1
Figure 5.41
Slave 8 4096
RSPCK clock
high pulse width
Master t
SPCKWH
(t
SPcyc
– t
SPCKr
–
t
SPCKf
)/2
– 3
—ns
Slave (t
SPcyc
– t
SPCKr
–
t
SPCKf
)/2
—
RSPCK clock
low pulse width
Master t
SPCKWL
(t
SPcyc
– t
SPCKr
–
t
SPCKf
)/2
– 3
—ns
Slave (t
SPcyc
– t
SPCKr
–
t
SPCKf
)/2
—
RSPCK clock
rise/fall time
Output 2.7 V or above t
SPCKr,
t
SPCKf
—10ns
1.8 V or above — 15
Input — 1 μs
Data input setup
time
Master 2.7 V or above t
SU
10 — ns Figure 5.42 to
Figure 5.45
1.8 V or above 30 —
Slave 25 – t
Pcyc
—
Data input hold
time
Master RSPCK set to a
division ratio other than
PCLKB divided by 2
t
H
t
Pcyc
—ns
RSPCK set to PCLKB
divided by 2
t
HF
0—
Slave t
H
20 + 2 × t
Pcyc
—
SSL setup time Master t
LEAD
–30 + N*
2
× t
SPcyc
—ns
Slave 2 — t
Pcyc
SSL hold time Master t
LAG
–30 + N*
3
× t
SPcyc
—ns
Slave 2 — t
Pcyc
Data output delay
time
Master 2.7 V or above t
OD
—14ns
1.8 V or above — 30
Slave 2.7 V or above — 3 × t
Pcyc
+ 65
1.8 V or above — 3 × t
Pcyc
+105
Data output hold
time
Master 2.7 V or above t
OH
0—ns
1.8 V or above –20 —
Slave 0 —
Successive
transmission delay
time
Master t
TD
t
SPcyc
+ 2 × t
Pcyc
8 × t
SPcyc
+ 2 × t
Pcyc
ns
Slave 4 × t
Pcyc
—
MOSI and MISO
rise/fall time
Output 2.7 V or above t
Dr,
t
Df
—10ns
1.8 V or above — 20
Input — 1 μs
SSL rise/fall time Output t
SSLr,
t
SSLf
—20ns
Input — 1 μs
Slave access time 2.7 V or above t
SA
—6t
Pcyc
Figure 5.44,
Figure 5.45
1.8 V or above — 7
Slave output release time 2.7 V or above t
REL
—5t
Pcyc
1.8 V or above — 6