Datasheet

R01DS0190EJ0100 Rev.1.00 Page 80 of 107
Jun 19, 2013
RX111 Group 5. Electrical Characteristics
Note: • t
Pcyc
: PCLK cycle
Note 1. C
b
indicates the total capacity of the bus line.
Note 2. This applies when the SMR.CKS[1:0] bits = 00b and the SNFR.NFCS[2:0] bits = 010b while the SNFR.NFE bit = 1 and the digital
filter is enabled.
Figure 5.33 I/O Port Input Timing
Figure 5.34 MTU2 Input/Output Timing
Table 5.34 Timing of On-Chip Peripheral Modules (5)
Conditions: VCC = AVCC0 = VCC_USB = 2.7 to 3.6 V, VSS = AVSS0 = VREFL0 = VSS_USB = 0 V, fPCLKB ≤ 32 MHz,
T
a
= –40 to +105°C
Item Symbol Min.*
1
Max. Unit Test Conditions
Simple IIC
(Standard mode)
SDA0 rise time
t
Sr
—1000ns
Figure 5.46
SDA0 fall time
t
Sf
—300ns
SDA0 spike pulse removal time
t
SP
04 × t
pcyc
*
2
ns
Data setup time
t
SDAS
250 — ns
Data hold time
t
SDAH
0—ns
SCL0, SDA0 capacitive load
C
b
—400pF
Simple IIC
(Fast mode)
SCL0, SDA0 rise time
t
Sr
—300ns
Figure 5.46
SCL0, SDA0 fall time
t
Sf
—300ns
SCL0, SDA0 spike pulse removal time
t
SP
04 × t
pcyc
*
2
ns
Data setup time
t
SDAS
100 — ns
Data hold time
t
SDAH
0—ns
SCL0, SDA0 capacitive load
C
b
—400pF
Port
PCLK
t
PRW
Output
compare output
Input capture
input
PCLK
t
TICW