Datasheet

R01DS0190EJ0100 Rev.1.00 Page 94 of 107
Jun 19, 2013
RX111 Group 5. Electrical Characteristics
5.8 Power-On Reset Circuit and Voltage Detection Circuit Characteristics
Note: • These characteristics apply when noise is not superimposed on the power supply. When a setting is made so that the voltage
detection level overlaps with that of the voltage detection circuit (LVD2), it cannot be specified which of LVD1 and LVD2 is used
for voltage detection.
Note 1. # in the symbol Vdet1_# denotes the value of the LVDLVLR.LVD1LVL[3:0] bits.
Note: • These characteristics apply when noise is not superimposed on the power supply. When a setting is made so that the voltage
detection level overlaps with that of the voltage detection circuit (LVD1), it cannot be specified which of LVD1 and LVD2 is used
for voltage detection.
Note 1. # in the symbol Vdet2_# denotes the value of the LVDLVLR.LVD2LVL[3:0] bits.
Note 2. Vdet2_3 selection can be used only when the CMPA2 pin input voltage is selected and cannot be used when the power supply
voltage (VCC) is selected.
Note 3. When OFS1.(STUPLVD1REN, FASTSTUP) = 11b.
Note 4. When OFS1.(STUPLVD1REN, FASTSTUP) ≠ 11b.
Note 5. The minimum VCC down time indicates the time when VCC is below the minimum value of voltage detection levels V
POR
, V
det0
,
V
det1,
and V
det2
for the POR/LVD.
Table 5.43 Power-On Reset Circuit and Voltage Detection Circuit Characteristics (1)
Conditions: VCC = AVCC0 = VCC_USB, VSS = AVSS0 = VREFL0 = VSS_USB = 0 V, T
a
= –40 to +105°C
Item Symbol Min. Typ. Max. Unit Test Conditions
Voltage detection level Power-on reset (POR)
V
POR
1.35 1.50 1.65 V Figure 5.51,
Figure 5.52
Voltage detection
circuit (LVD1)*
1
V
det1_4
3.00 3.10 3.20 V
Figure 5.53
At falling edge VCC
V
det1_5
2.91 3.00 3.09
V
det1_6
2.81 2.90 2.99
V
det1_7
2.70 2.79 2.88
V
det1_8
2.60 2.68 2.76
V
det1_9
2.50 2.58 2.66
V
det1_A
2.40 2.48 2.56
V
det1_B
1.99 2.06 2.13
V
det1_C
1.90 1.96 2.02
V
det1_D
1.80 1.86 1.92
Table 5.44 Power-On Reset Circuit and Voltage Detection Circuit Characteristics (2)
Conditions: VCC = AVCC0 = VCC_USB, VSS = AVSS0 = VREFL0 = VSS_USB = 0 V, T
a
= –40 to +105°C
Item Symbol Min. Typ. Max. Unit Test Conditions
Voltage detection level Voltage detection circuit
(LVD2)*
1
V
det2_0
2.71 2.90 3.09 V
Figure 5.54
At falling edge VCC
V
det2_1
2.43 2.60 2.77
V
det2_2
1.87 2.00 2.13
V
det2_3
*
2
1.69 1.80 1.91
Wait time after power-on
reset cancellation
At normal startup*
3
t
POR
― 9.1 ― ms
Figure 5.52
During fast startup time*
4
t
POR
― 1.6 ―
Wait time after voltage
monitoring 1 reset
cancellation
Power-on voltage monitoring
1 reset disabled*
3
t
LVD1
― 568 ―μs
Figure 5.53
Power-on voltage monitoring
1 reset enabled*
4
― 100 ―
Wait time after voltage monitoring 2 reset cancellation
t
LVD2
― 100 ―μs
Figure 5.54
Response delay time
t
det
――350 μs
Figure 5.51
Minimum VCC down time*
5
t
VOFF
350 ―― μs
Figure 5.51,
VCC = 1.0 V or above
Power-on reset enable time
t
W(POR)
1 ――ms
Figure 5.52,
VCC = below 1.0 V
LVD operation stabilization time (after LVD is enabled)
Td
(E-A)
――300 μs
Figure 5.53, Figure 5.54
Hysteresis width (LVD1 and LVD2)
V
LVH
― 70 ― mV
Vdet1_4 selected
― 60 ―
Vdet1_5 to 9, LVD2 selected
― 50 ―
When selection is from
among Vdet1_A to B.
― 40 ―
When selection is from
among Vdet1_C to D.