Datasheet

R01DS0190EJ0100 Rev.1.00 Page 79 of 107
Jun 19, 2013
RX111 Group 5. Electrical Characteristics
Note: • t
IICcyc
: RIIC internal reference count clock (IICφ) cycle
Note 1. The value in parentheses is used when the ICMR3.NF[1:0] bits are set to 11b while a digital filter is enabled with the ICFER.NFE
bit = 1.
Note 2. C
b
indicates the total capacity of the bus line.
Note 3. The minimum tsr and tsf specifications for fast mode are not set.
Table 5.33 Timing of On-Chip Peripheral Modules (4)
Conditions: VCC = AVCC0 = VCC_USB = 2.7 to 3.6 V, VSS = AVSS0 = VREFL0 = VSS_USB = 0 V, fPCLKB ≤ 32 MHz,
T
a
= –40 to +105°C
Item Symbol Min.*
1,
*
2
Max. Unit Test Conditions
RIIC
(Standard mode,
SMBus)
SCL0 cycle time
t
SCL
6 (12) × t
IICcyc
+ 1300 — ns
Figure 5.46
SCL0 high pulse width
t
SCLH
3 (6) × t
IICcyc
+ 300 — ns
SCL0 low pulse width
t
SCLL
3 (6) × t
IICcyc
+ 300 — ns
SCL0, SDA0 rise time
t
Sr
— 1000 ns
SCL0, SDA0 fall time
t
Sf
— 300 ns
SCL0, SDA0 spike pulse removal time
t
SP
01 (4) × t
IICcyc
ns
SDA0 bus free time
t
BUF
3 (6) × t
IICcyc
+ 300 — ns
START condition hold time
t
STAH
t
IICcyc
+ 300 — ns
Repeated START condition setup time
t
STAS
1000 — ns
STOP condition setup time
t
STOS
1000 — ns
Data setup time
t
SDAS
t
IICcyc
+ 50 — ns
Data hold time
t
SDAH
0—ns
SCL0, SDA0 capacitive load
C
b
— 400 pF
RIIC
(Fast mode)
SCL0 cycle time
t
SCL
6 (12) × t
IICcyc
+ 600 — ns
Figure 5.46
SCL0 high pulse width
t
SCLH
3 (6) × t
IICcyc
+ 300 — ns
SCL0 low pulse width
t
SCLL
3 (6) × t
IICcyc
+ 300 — ns
SCL0, SDA0 rise time
t
Sr
—*
3
300 ns
SCL0, SDA0 fall time
t
Sf
—*
3
300 ns
SCL0, SDA0 spike pulse removal time
t
SP
01 (4) × t
IICcyc
ns
SDA0 bus free time
t
BUF
3 (6) × t
IICcyc
+ 300 — ns
START condition hold time
t
STAH
t
IICcyc
+ 300 — ns
Repeated START condition setup time
t
STAS
300 — ns
STOP condition setup time
t
STOS
300 — ns
Data setup time
t
SDAS
t
IICcyc
+ 50 — ns
Data hold time
t
SDAH
0—ns
SCL0, SDA0 capacitive load
C
b
— 400 pF