Datasheet

R01DS0190EJ0100 Rev.1.00 Page 9 of 107
Jun 19, 2013
RX111 Group 1. Overview
1.3 Block Diagram
Figure 1.2 shows a block diagram.
Figure 1.2 Block Diagram
External bus
BSC
ICUb: Interrupt controller
DTCa: Data transfer controller
IWDTa: Independent watchdog timer
ELC: Event link controller
CRC: CRC (cyclic redundancy check) calculator
SCIe/SCIf: Serial communications interface
RSPI: Serial peripheral interface
RIIC: I
2
C bus interface
MTU2a: Multi-function timer pulse unit 2
POE2a: Port output enable 2
USBc: USB 2.0 host/function module
CMT: Compare match timer
RTCA: Realtime clock
DOC: Data operation circuit
CAC: Clock frequency accuracy measurement circuit
Operand bus
Instruction bus
Internal main bus 1
Clock
generation
circuit
RX CPU
RAM
ROM
Port 0
Port 1
Port 2
Port 3
Port 4
Internal peripheral buses 1 to 6
Internal main bus 2
DTCa
ICUb
Port 5
Port A
Port B
Port C
Port E
E2 DataFlash
IWDTa
ELC
CRC
SCIe × 2 channels
SCIf × 1 channel
RSPI × 1 channel
RIIC × 1 channel
MTU2a × 6 channels
POE2a
USBc × 1 port
CMT × 2 channels (unit 0)
RTCA
12-bit A/D converter × 14 channels
8-bit D/A converter × 2 channels
DOC
CAC
Temperature sensor
Port H
Port J