Computer Monitor User Manual

ManualsBrandsRenesas ManualsMonitorR61509V

Rev. 0.11 April 25, 2008, page 1 of 181

Target Spec

R61509V

260k-color, 240RGB x 432-dot graphics liquid crystal

controller driver for Amorphous-Silicon TFT Panel

REJxxxxxxx-xxxx

Rev.0.11

April 25, 2008

Description ......................................................................................................... 6

Features ......................................................................................................... 7

Power Supply Specifications .............................................................................. 8

Differences Between R61509 and R61509V...................................................... 9

Block Diagram.................................................................................................... 10

Block Function.................................................................................................... 11

1. System Interface.....................................................................................................................................................11

External Display Interface (RGB, VSYNC interfaces)........................................................................................12

Address Counter (AC) ...........................................................................................................................................12

Graphics RAM (GRAM)........................................................................................................................................13

Grayscale Voltage Generating Circuit..................................................................................................................13

Liquid Crystal Drive Power Supply Circuit..........................................................................................................13

Timing Generator ..................................................................................................................................................13

Oscillator (OSC).....................................................................................................................................................13

Liquid crystal driver Circuit ..................................................................................................................................13

10.

Internal Logic Power Supply Regulator...............................................................................................................13

Pin Function........................................................................................................ 14

Pad Arrangement ................................................................................................ 19

Pad coordinate..................................................................................................... 21

Bump Arrangement............................................................................................. 36

Connection Example........................................................................................... 37

GRAM Address Map .......................................................................................... 38

Instruction ......................................................................................................... 40

Summary of content (181 pages)

PAGE 1
Target Spec R61509V 260k-color, 240RGB x 432-dot graphics liquid crystal controller driver for Amorphous-Silicon TFT Panel REJxxxxxxx-xxxx Rev.0.11 April 25, 2008 Description ......................................................................................................... 6 Features ......................................................................................................... 7 Power Supply Specifications ..............................................................................
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R61509V Target Spec Outline ..........................................................................................................................................................................40 Instruction Data Format..............................................................................................................................................40 Index (IR) ..................................................................................................................................
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R61509V Target Spec NVM Control ................................................................................................................................................................90 NVM Access Control 1 (R6F0h), NVM Access Control 2 (R6F1h), NVM Access Control 3 (R6F2h).................90 Instruction List .................................................................................................... 92 Reset Function ......................................................................
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R61509V Target Spec Partial Display Function ..................................................................................... 139 Liquid Crystal Panel Interface Timing ............................................................... 140 Internal Clock Operation.............................................................................................................................................140 RGB Interface Operation.............................................................................
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R61509V Target Spec Clock Characteristics .............................................................................................................................................172 80-system 18-/16-/9-/8-bit Bus interface Timing Characteristics .........................................................................172 Clock Synchronous Serial Interface Timing Characteristics.................................................................................173 RGB Interface Timing Characteristics....
PAGE 6
R61509V Target Spec Description The R61509V is a single-chip liquid crystal controller driver LSI for a-Si TFT panel, incorporating RAM for a maximum 240 RGB x 432 dot graphics display, gate driver, source driver and power supply circuits. For efficient data transfer, the R61509V supports high-speed interface via 8-/9-/16-/18-bit ports as system interface to the microcomputer. As moving picture interface, the R61509V also supports RGB interface (VSYNCX, HSYNCX, DOTCLK, ENABLE and DB17-0).
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R61509V Target Spec Features • • • • • • • • • • • • • • A single-chip controller driver incorporating a gate circuit and a power supply circuit for a maximum 240RGB x 432dots graphics display on amorphous TFT panel in 262k colors System interface – High-speed interfaces via 8-, 9-, 16-, 18-bit parallel ports – Clock synchronous serial interface Moving picture display interface – 16-/18-bit RGB interface (VSYNCX, HSYNCX, DOTCLK, ENABLE, DB17-0) – VSYNC interface (System interface + VSYNCX) – FMARK
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R61509V Target Spec Power Supply Specifications Table 1 No. 1 Item TFT data lines R61509V 720 output 2 TFT gate lines 432 output 3 TFT display storage capacitance Cst only (Common VCOM formula) 4 Liquid crystal drive output V0 ~ V63 grayscales 5 6 Input voltage Liquid crystal drive voltages S1~S720 G1~G432 VGH-VGL VCOM Change VCOMH-VCOML amplitude with electronic volume Change VCOMH with either electronic volume or from VCOMR IOVCC (interface voltage) 1.65V ~ 3.
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Difference Between R61509 and R61509V 2008.04.18 R61509V Deleted B509H 1 line inversion Deleted Index (Pin) R000h R002h R003h Command System Interface Device Code Read LCD Drive Waveform Control Entry Mode NW[1-0] --> NW bit is deleted. HWM R006h R007h Outline Sharpening Control Display Control 1 EPF[1-0] EGMODE, AVST[2:0], ADST[2:0]DTHU[1:0], DTHL[1:0] PTDE[1-0]-->PTDE0 High Speed RAM Write Sets data format when writing 16bit data in 18bit format.
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R61509V Target Spec Block Diagram GND Control 㩷 Register (CR) AGND 18 㩷㩷 18 bit 16 bit 9 bit 8 bit Serial Write data latch 㩷 18 㩷 18 Read data 㩷 latch 㩷 18 Graphic RAM (GRAM) 233,280byte 18 㩷 18 㩷㩷 External display㩷㩷 interface Gate line drive circuit NVM VDD Figure 1 Rev. 0.
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R61509V Target Spec Block Function 1. System Interface The R61509V supports 80-system high-speed interface via 8-, 9-, 16-, 18-bit parallel ports and a clock synchronous serial interface. The interface is selected by setting the IM2-0 pins. The R61509V has 16-bit index register (IR), 18-bit write-data register (WDR), and 18-bit read-data register (RDR). The IR is the register to store index information from control register and internal GRAM.
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R61509V Target Spec Table 4 2.
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R61509V 4. Target Spec Graphics RAM (GRAM) GRAM stands for graphics RAM, which can store bit-pattern data of 233,280 (240RGB x 432 (dots) x 18(bits)) bytes at maximum, using 18 bits per pixel. 5. Grayscale Voltage Generating Circuit The grayscale voltage generating circuit generates liquid crystal drive voltages according to the grayscale data in the γ-correction registers to enable 262k-color display. For details, see the γ-Correction Register section. 6.
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R61509V Target Spec Pin Function Table 5 External Power Supply Signal I/O Connect to Function Power supply for Internal VDD regulator. When not used VCC I Power supply IOVCC I Power supply Power supply for interface pins. ― GND I Power supply GND level for internal logic and interface pins. GND=0V. ― VCI I Power supply Power supply for liquid crystal power supply analog circuit.
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R61509V DB[17:0] Target Spec I/O Host processor 18-bit parallel bi-directional data bus for 80-system interface operation (Amplitude: IOVCC-GND). 8-bit I/F: DB17-DB10 are used. 9-bit I/F: DB17-DB9 are used. 16-bit I/F: DB17-DB10 and DB8-1 are used. 18-bit I/F: DB17-DB0 are used. 18-bit parallel bi-directional data bus for RGB interface operation (Amplitude: IOVCC-GND). 16-bit I/F: DB17-DB13 and DB11-1 are used. 18-bit I/F: DB17-DB0 are used.
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R61509V PROTECT Target Spec I Host processor Reset protect pin. The R61509V enters a reset protect status by fixing PROTECT to GND level disabling hardware reset. With this, erroneous operations caused by noise are prevented. Low: Hardware reset is disabled (Reset protect status) High: Hardware reset is enabled. (Normal status) IOVCC Table 7 Internal Power Supply Circuit Signal I/O Connect to Function When not used VDD O Stabilizing capacitor Output from internal logic regulator.
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R61509V Target Spec Table 8 LCD drive Signal I/O VREG1OUT O VCOM O Connect to Function When not in use Stabilizing Output voltage generated from the reference voltage VCIR. The factor capacitor is determined by instruction (VRH bits). VREG1OUT is used for (1) source driver grayscale reference voltage VREG1OUT, (2) VCOMH level reference voltage, and (3) VCOM amplitude reference voltage. Connect to a stabilizing capacitor. VREG1OUT =4.0V ~ (DDVDH – 0.
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R61509V Target Spec Table 9 Others (test, dummy pins) When not in use Signal I/O Connect to Function VTEST O Open Test pin. Leave open. VREFC I GND Test pin. Make sure to fix to the GND level. VREFD O Open Test pin. Leave open. Open Open VREF O Open Test pin. Leave open. VDDTEST I GND Test pin. Make sure to fix to the GND level. VMON O Open Test pin. Leave open. VCIR O Open - Open Open Test pin. Leave open.
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R61509V Pad Arrangement Rev 0.
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R61509V Target Spec ●Chip size: 19.03mm x 0.76mm ●Chip thickness: 280μm (typ) ●Pad coordinates: Pad center ●Coordinate origin: Chip center ●Au bump size 1. 50μm x 90μm (I/O side: No.1-262) 2. 15μm x 100μm (LCD output side: No.263-1434) ●Au bump pitch: See pad coordinate ●Au bump height:12μm ● Alignment mark Table 10 Alignment marks Type A X-axis Y-axis (1-a) -9381.0 -251.0 (1-b) 9381.0 -251.
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R61509V Pad Coordinate （Unit：μm） pad No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 pad name DUMMYR1 DUMMYR2 AGNDDUM1 VPP3B VPP3B VPP3B VPP3B AGNDDUM2 VPP3A VPP3A VPP1 VPP1 VPP1 VPP1 VPP1 VPP1 VPP1 GNDDUM1 VDDTEST VREFC VREFD VREF VCCDUM1 DUMMYA DUMMYA DUMMYA DUMMYA DUMMYA GNDDUM2 AGND AGND AGND AGND AGND AGND GND GND GND GND GND VCC VCC VCC VCC VCC VCC VCC TS8 TS7 TS6 X -9135.0 -9065.0 -8995.0 -8925.0 -8855.
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R61509V Pad Coordinate （Unit：μm） pad No 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 pad name GNDDUM8 DB3 DB2 DB1 DB0 GNDDUM9 CSX RS WRX_SCL RDX GNDDUM10 FMARK SDI SDO VDD VDD VDD VDD VDD VDD VDD VDD VDD VMON VCOM VCOM VCOM VCOM VCOM VCOM VCOM VCOM VCOMH VCOMH VCOMH VCOMH VCOMH VCOMH VCOML VCOML VCOML VCOML VCOML VCOML GND GND GND GND GND GND X -2135.
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R61509V Pad Coordinate （Unit：μm） pad No 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 pad name VCI VCI VCI VCI VCI VCI VCILVL DUMMYC DUMMYC DUMMYC DUMMYC DUMMYC GND GND GND GND GND AGND AGND AGND AGND AGND VGL VGL VGL VGL VGL VGL VGL VGL VGL AGNDDUM3 AGNDDUM4 VGH VGH VGH VGH VGH VGH AGNDDUM5 VCL VCL VCL C13M C13M C13M C13P C13P C13P C21M X 4865.0 4935.
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R61509V Pad Coordinate （Unit：μm） pad No 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 pad name G70 G72 G74 G76 G78 G80 G82 G84 G86 G88 G90 G92 G94 G96 G98 G100 G102 G104 G106 G108 G110 G112 G114 G116 G118 G120 G122 G124 G126 G128 G130 G132 G134 G136 G138 G140 G142 G144 G146 G148 G150 G152 G154 G156 G158 G160 G162 G164 G166 G168 X 8827.5 8812.5 8797.
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R61509V Pad Coordinate （Unit：μm） pad No 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 pad name G270 G272 G274 G276 G278 G280 G282 G284 G286 G288 G290 G292 G294 G296 G298 G300 G302 G304 G306 G308 G310 G312 G314 G316 G318 G320 G322 G324 G326 G328 G330 G332 G334 G336 G338 G340 G342 G344 G346 G348 G350 G352 G354 G356 G358 G360 G362 G364 G366 G368 X 7327.
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R61509V Pad Coordinate （Unit：μm） pad No 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 pad name S704 S703 S702 S701 S700 S699 S698 S697 S696 S695 S694 S693 S692 S691 S690 S689 S688 S687 S686 S685 S684 S683 S682 S681 S680 S679 S678 S677 S676 S675 S674 S673 S672 S671 S670 S669 S668 S667 S666 S665 S664 S663 S662 S661 S660 S659 S658 S657 S656 S655 X 5632.
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R61509V Pad Coordinate （Unit：μm） pad No 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 pad name S604 S603 S602 S601 S600 S599 S598 S597 S596 S595 S594 S593 S592 S591 S590 S589 S588 S587 S586 S585 S584 S583 S582 S581 S580 S579 S578 S577 S576 S575 S574 S573 S572 S571 S570 S569 S568 S567 S566 S565 S564 S563 S562 S561 S560 S559 S558 S557 S556 S555 X 4132.
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R61509V Pad Coordinate （Unit：μm） pad No 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 pad name S504 S503 S502 S501 S500 S499 S498 S497 S496 S495 S494 S493 S492 S491 S490 S489 S488 S487 S486 S485 S484 S483 S482 S481 S480 S479 S478 S477 S476 S475 S474 S473 S472 S471 S470 S469 S468 S467 S466 S465 S464 S463 S462 S461 S460 S459 S458 S457 S456 S455 X 2632.
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R61509V Pad Coordinate （Unit：μm） pad No 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 pad name S404 S403 S402 S401 S400 S399 S398 S397 S396 S395 S394 S393 S392 S391 S390 S389 S388 S387 S386 S385 S384 S383 S382 S381 S380 S379 S378 S377 S376 S375 S374 S373 S372 S371 S370 S369 S368 S367 S366 S365 S364 S363 S362 S361 TESTO6 TESTO7 TESTO8 TESTO9 TESTO10 TESTO1
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R61509V Pad Coordinate （Unit：μm） pad No 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 pad name S312 S311 S310 S309 S308 S307 S306 S305 S304 S303 S302 S301 S300 S299 S298 S297 S296 S295 S294 S293 S292 S291 S290 S289 S288 S287 S286 S285 S284 S283 S282 S281 S280 S279 S278 S277 S276 S275 S274 S273 S272 S271 S270 S269 S268 S267 S266 S265 S264 S263 X -1207.
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R61509V Pad Coordinate （Unit：μm） pad No 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 pad name S212 S211 S210 S209 S208 S207 S206 S205 S204 S203 S202 S201 S200 S199 S198 S197 S196 S195 S194 S193 S192 S191 S190 S189 S188 S187 S186 S185 S184 S183 S182 S181 S180 S179 S178 S177 S176 S175 S174 S173 S172 S171 S1
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R61509V Pad Coordinate （Unit：μm） pad No 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 pad name S112 S111 S110 S109 S108 S107 S106 S105 S104 S103 S102 S101 S100 S99 S98 S97 S96 S95 S94 S93 S92 S91 S90 S89 S88 S87 S86 S85 S84 S83 S82 S81 S80 S79 S78 S77 S76 S75 S74 S73 S72 S71 S70 S69 S68 S67 S66 S65 S64 S63
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R61509V Pad Coordinate （Unit：μm） pad No 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 pad name S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 TESTO14 VGLDMY3 G431 G429 G427 G425 G423 G421 G419 G417 G415 G413 G411 G409 G407 G405 G403 G401 G399 G397 G395 G393 G391 G389 G387 G385 G383 G381 G379 G377 G375 G373 G371 G3
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R61509V Pad Coordinate （Unit：μm） pad No 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 pad name G259 G257 G255 G253 G251 G249 G247 G245 G243 G241 G239 G237 G235 G233 G231 G229 G227 G225 G223 G221 G219 G217 G215 G213 G211 G209 G207 G205 G203 G201 G199 G197 G195 G193 G191 G189 G187 G185 G183 G181 G179 G177 G1
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R61509V Pad Coordinate （Unit：μm） pad No 1401 1402 1403 1404 1405 1406 1407 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 pad name G59 G57 G55 G53 G51 G49 G47 G45 G43 G41 G39 G37 G35 G33 G31 G29 G27 G25 G23 G21 G19 G17 G15 G13 G11 G9 G7 G5 G3 G1 VGLDMY4 TESTO15 DUMMYR3 DUMMYR4 X -8902.5 -8917.5 -8932.5 -8947.5 -8962.5 -8977.5 -8992.5 -9007.5 -9022.5 -9037.5 -9052.5 -9067.5 -9082.5 -9097.5 -9112.5 -9127.5 -9142.5 -9157.
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R61509V Target Spec Bump Arrangement 㪪㪈䌾㪪㪎㪉㪇䋬㩷㪞㪈䌾㪞㪋㪊㪉䋬㩷㪛㪬㪤㪤㪰㪩㪎㪄㪈㪇㪃㩷㪫㪜㪪㪫㪦㪈㪈㪄㪈㪏㪃㩷㪭㪞㪣㪛㪤㪰㪈㪄㪋㩷㩿㪥㫆㩷㪉㪍㪊㪄㪈㪋㪊㪋㪀㩷㩷㩷㩷㩷㩷㩷㩷㩷㩷㩷㩷㩷㩷㩷㩷㩷㩷㩷㩷㩷 15 15 100 19 219 12 Unit : um 50 50 20 S=4,500um2 90 㪠㪆㪦㩷㫇㫀㫅㫊㩷㩿㪥㫆㪈㩷㵨㩷㪉㪍㪉㪀㩷 12 70 Figure 3 Rev. 0.
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R61509V Wiring Example & Recommended Wiring Resistance (Pad Arrangement Rev0.6) 2008.04.21 Rev0.5 Rev0.1 2008.02.14 Made for PR Rev0.11 2008.02.19 VPP3C-->VPP3B, VPP2-->VPP1 Rev0.2 2008.02.28 Pad names changed. Rev0.3 2008.0314 Instruction changed. Rev0.4 2008.0402 R61517's EEPROM IF deleted. R61509V VPP2--> VPP1 Rev0.5 2008.04.21 Pad names changed.
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R61509V Target Spec GRAM Address Map GS=0 GS=1 S720 S719 S718 S717 S716 S715 S714 S713 S712 S711 S710 ・・・・・ S709 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S/G pin S1 Table 11 GRAM address and display position on the panel (SS = 0, BGR = 0) WD[17:0] WD[17:0] WD[17:0] WD[17:0] ・・・・・ WD[17:0] WD[17:0] WD[17:0] WD[17:0] G1 G432 h00000 h00001 h00002 h00003 ・・・・・ h000EC h000ED h000EE h000EF G2 G431 h00100 h00101 h00102 h00103 ・・・・・ h001EC h001ED h001EE h001EF
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R61509V Target Spec GS=0 GS=1 WD[17:0] S1 S3 S2 S4 S5 S6 S7 S8 S9 S10 S11 ・・・・・ S12 S709 S710 S711 S712 S713 S714 S715 S716 S717 S718 S719 S/G pin S720 Table 12 GRAM address and display position on the panel (SS = 1, BGR = 1) WD[17:0] WD[17:0] WD[17:0] ・・・・・ WD[17:0] WD[17:0] WD[17:0] WD[17:0] G1 G432 h00000 h00001 h00002 h00003 ・・・・・ h000EC h000ED h000EE h000EF G2 G431 h00100 h00101 h00102 h00103 ・・・・・ h001EC h001ED h001EE h001EF G3 G430 h00200
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R61509V Target Spec Instruction Outline The R61509V adopts 18-bit bus architecture in order to interface to high-performance microcomputer in high speed. The R61509V starts internal processing after storing control information (18, 16, 9, 8, 1 bit(s)), sent from the microcomputer, in the instruction register (IR) and the data register (DR).
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R61509V Target Spec Index (IR) R/W RS IB15 IB14 IB13 IB12 IB11 W 0 0 0 0 0 0 IB10 ID [10] IB9 ID [9] IB8 ID [8] IB7 ID [7] IB6 ID [6] IB5 ID [5] IB4 ID [4] IB3 ID [3] IB2 ID [2] IB1 ID [1] IB0 ID [0] The index register specifies the indexes of control register or RAM control to be accessed. It is prohibited to access registers and instruction bits to which no index register is assigned.
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R61509V Target Spec LCD Drive Wave Control (R002h) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 R/W 1 0 0 0 0 0 0 0 BC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IB3 IB2 IB1 IB0 AM 0 0 0 0 0 0 0 Default value BC: Selects the liquid crystal drive waveform VCOM. BC = 0: frame inversion waveform is selected. BC = 1: line inversion waveform is selected.
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R61509V Target Spec BGR: Reverses the order from RGB to BGR in writing 18-bit pixel data in the GRAM. BGR = 0: BGR = 1: Write data in the order of RGB to the GRAM. Reverse the order from RGB to BGR in writing data to the GRAM. DFM: In combination with the TRI setting, DFM sets the format to develop 16-/8-bit data to 18-bit data when using either 16- or 8-bit bus interface. Make sure to set DFM = 0 when not transferring data via 16bit or 8-bit interface.
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R61509V Target Spec Automatic Address Update (ORG = 0, AM, ID) ID1-0 = 00 Horizontal: Decrement Vertical: Decrement ORG = 0 AM = 0 Horizontal 17'h00000 ID1-0 = 01 Horizontal: Increment Vertical: Decrement 17'h00000 17'h00000 17'hAFEF Note: 17'h00000 17'h00000 17'hAFEF 17'hAFEF ID1-0 = 11 Horizontal: Increment Vertical: Increment 17'hAFEF 17'hAFEF 17'h00000 17'h00000 AM = 1 Vertical ID1-0 = 10 Horizontal: Decrement Vertical: Increment 17'hAFEF 17'h00000 17'hAFEF 17'hAFEF When writing d
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R61509V Target Spec Display Control 1 (R007h) R/W RS R/W 1 Default IB15 IB14 IB13 IB12 IB11 IB10 PTD 0 0 0 0 0 E 0 0 0 0 0 0 IB9 0 0 IB8 BAS EE IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BASEE: Base image display enable bit. BASEE = 0: No base image is displayed. The R61509V drives the LCD at non-lit display level or displays partial images. BASEE = 1: A base image is displayed. PTDE: Partial display 1 enable bit.
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R61509V Target Spec Display Control 2 (R008h) R/W RS R/W 1 IB15 IB14 IB13 IB12 IB11 IB10 FP FP FP FP FP FP [7] [6] [5] [4] [3] [2] Default 0 0 0 0 1 0 IB9 FP [1] IB8 FP [0] IB7 BP [7] IB6 BP [6] IB5 BP [5] IB4 BP [4] IB3 BP [3] IB2 BP [2] IB1 BP [1] IB0 BP [0] 0 0 0 0 0 0 1 0 0 0 FP[7:0]: Sets the number of lines for front porch period (a blank period made after the end of display).
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R61509V Target Spec VSYNCX BP Back porch NL Display Area Front porch FP Note: The output timing to the panel is delayed by 2 line period from the synchronous signal (VSYNCX) input. Figure 5 Front and Back Porch Periods Note on Setting BP and FP: Set the BP and FP bits as follows in the following operation modes, respectively. Table 14 BP ≥ 2 lines FP ≥ 3 lines FP + BP ≤ 256 lines Rev. 0.
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R61509V Target Spec Display Control 3 (R009h) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 R/W 1 0 0 0 0 PTV Default 0 0 0 0 0 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 PTS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 PTS: Sets the source output level to drive non-display area. PTS also selects operation of grayscale amplifier and step-up clock frequency.
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R61509V Target Spec 8 Color Control (R00Bh) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W/R 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Default value COL: When COL = 1, the R61509V enters the eight-color display mode. RAM data rewrite operation is not required when setting the eight-color display mode. Set the 8-color mode instruction according to the 8-color mode sequence.
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R61509V Target Spec External Display Interface Control 1 (R00Ch) R/W RS R/W IB15 IB14 IB13 IB12 IB11 IB10 IB9 1 0 Default 0 ENC ENC ENC [2] [1] [0] 0 0 0 IB8 IB7 IB6 0 0 0 RM 0 0 0 0 0 0 0 0 IB5 IB4 DM DM [1] [0] 0 0 IB3 IB2 IB1 IB0 0 0 0 RIM 0 0 0 0 RIM: Sets the interface format when RGB interface is selected by RM and DM bits. Set RIM bit before starting display operation via the external display interface.
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R61509V Target Spec ENC[2:0]: Sets the RAM write cycle via RGB interface. Table 21 ENC[2:0] RAM Write Cycle (frame periods) 3’h0 1 frame 3’h1 2 frames 3’h2 3 frames 3’h3 4 frames 3’h4 5 frames 3’h5 6 frames 3’h6 7 frames 3’h7 8 frames Rev. 0.
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R61509V Target Spec External Display Interface Control 2 (R00Fh) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 R/W 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Default value IB4 0 DPL: Sets the signal polarity of DOTCLK pin. DPL = 0: input data on the rising edge of DOTCLK DPL = 1: input data on the falling edge of DOTCLK EPL: Sets the signal polarity of ENABLE pin.
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R61509V Target Spec Panel Interface Control 1 (R010h) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 R/W 1 0 0 0 0 0 0 Default 0 0 0 0 0 0 IB9 DIV I [1] 0 IB8 DIV I [0] 0 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 0 0 0 RTNI [4] RTNI [3] RTNI [2] RTNI [1] RTNI [0] 0 0 0 1 1 0 0 1 RTNI[4:0]: Sets 1H (line) period. This setting is valid when the R61509V’s display operation is synchronized with internal clock signal.
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R61509V Target Spec Frame Frequency Calculation Frame frequency = fosc Clocks per line x division ratio x (line + BP + FP) fosc : RC oscillation frequency Line: Number of lines to drive the LCD (NL bits) Division ratio: DIVI Clocks per line: RTNI Rev. 0.
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R61509V Target Spec Panel Interface Control 2 (R011h) R/W R/W RS IB15 IB14 IB13 IB12 IB11 1 0 0 0 0 0 Default 0 0 0 0 0 IB10 IB9 IB8 IB7 NOW NOW NOW I[2] I[1] I[0] 0 0 1 IB6 IB5 IB4 IB3 0 0 0 0 0 0 0 0 0 0 IB2 IB1 NOWI[2:0]: Sets the non-overlap period of adjacent gate outputs. The setting is enabled when the R61509V’s display operation is synchronized with internal clock signals.
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R61509V Target Spec Panel Interface Control 3 (R012h) R/W RS R/W 1 Default value IB15 IB14 IB12 IB11 0 0 IB13 0 0 0 0 0 0 0 0 IB10 IB9 IB8 VEQ VEQ VEQ WI[2] WI[1] WI[0] 0 0 0 IB7 IB6 IB5 IB4 IB3 0 0 0 0 0 0 0 0 0 0 IB2 IB1 IB0 SEQ SEQ SEQ WI[2] WI[1] WI[0] 0 0 VEQWI[2:0]: Sets VCOM equalize period. The VCOM equalize operation is executed from VCOM alternating point defined by MCPI [2:0] for the period defined by VEQWI [2:0].
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R61509V Target Spec SEQWI[2:0]: Sets source equalize period. SEQWI setting is enabled only when the R61509V executes display operation in synchronization with internal clock. Table 27 SEQWI[2:0] Source Equalize Period 3'h0 0 clocks 3'h1 1 clock 3'h2 2 clocks 3'h3 3 clocks 3'h4 4 clocks 3'h5 5 clocks 3'h6 6 clocks 3'h7 7 clocks Note: The clock is the frequency divided clock, which is set by DIVI[[1:0] bits. Rev. 0.
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R61509V Target Spec Panel Interface Control 4 (R013h) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 R/W 1 0 0 0 0 0 Default 0 0 0 0 0 IB9 IB8 IB7 IB6 IB5 IB4 IB3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IB2 IB1 MC MC PI PI[2] [1] 0 0 IB0 MC PI [0] 1 MCPI: Defines VCOM alternating timing. This bit is enabled when displaying in synchronization with internal clock. MCP cannot be used in RGB interface operation.
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R61509V Target Spec Panel Interface Control 5 (R014h) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 R/W 1 0 0 0 0 0 Default 0 0 0 0 0 IB9 IB8 IB7 0 0 0 0 0 0 0 0 IB6 PC DIV H [2] 1 IB5 PC DIV H [1] 0 IB4 PC DIV H [0] 1 IB3 0 0 IB2 PC DIV L [2] 1 IB1 PC DIV L [1] 0 IB0 PC DIV L [0] 1 PCDIVH[2:0], PCDIVL[2:0]: When DM=1 and RGB I/F is selected, display operation is executed using DOTCLKD. PCDIVH and PCDIVL define division ratio of DOTCLK to generate DOTCLKD.
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R61509V Target Spec Panel Interface Control 6 (R020h) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 R/W 1 0 0 0 0 0 0 Default 0 0 0 0 0 0 IB9 DIV E[1] 0 IB8 DIV E[0] 0 IB7 IB6 0 0] 0 0 IB5 IB4 IB3 IB2 IB1 IB0 RTN RTN RTN RTN RTN RTN E[5] E[4] E[3] E[2] E[1] E[0] 0 1 1 0 0 1 DIVE[1:0]: Sets the division ratio of DOTCLK. The R61509V’s internal operation is synchronized with the frequency-divided DOTCLK, the frequency of which is divided by the division ratio set by DIVE[1:0].
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R61509V Target Spec RTNE[5:0]: Sets RTNE in combination with PCDIVH and PCDIVL to decide the number of DOTCLK in 1H (1 line) period according to the following formula. RTNE is enabled when RGB interface is selected. DOTCLKD x RTNE (Number of clock) ≤ DOTCLK in 1H period.
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R61509V Target Spec Panel Interface Control 7 (R021h) R/W RS R/W 1 Default IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 NOW NOW NOW 0 0 0 0 0 0 E[2] E[1] E[0] 0 0 0 0 0 0 0 1 0 IB6 IB5 IB4 IB3 0 0 0 0 0 0 0 0 IB2 IB1 IB0 SDTE SDTE SDTE [2] [1] [0] 0 0 1 NOWE[2:0]: Sets the non-overlap period of adjacent gate outputs. NOWE is enabled when RGB interface is selected.
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R61509V Target Spec Panel Interface Control 8 (R022h) R/W RS R/W 1 Default IB15 IB14 IB13 IB12 IB11 IB10 0 0 0 0 0 0 0 0 IB9 IB8 IB7 IB6 IB5 IB4 IB3 0 0 0 0 0 VEQ VEQ VEQ WE WE WE 0 0 [2] [1] [0] 0 0 0 0 0 0 0 0 IB2 IB1 IB0 SEQ SEQ SEQ WE WE WE [2] [1] [0] 0 0 0 VEQWE[2:0]: Sets low power VCOM drive period. The setting is enabled when RGB interface is selected.
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R61509V Target Spec SEQWE[2:0]: Sets source equalize period. SEQWE setting is enabled when the R61509V executes display operation via RGB interface. Table 36 SEQWE[2:0] Source Equalize Period 3'h0 0 clocks 3'h1 1 clock 3'h2 2 clocks 3'h3 3 clocks 3'h4 4 clocks 3'h5 5 clocks 3'h6 6 clocks 3'h7 7 clocks Note: 1 clock = (number of data transfer/pixel) x DIVE(Division ratio) x (PCDIVL + PCDIVH)) Rev. 0.
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R61509V Target Spec Panel Interface Control 9 (R023h) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 R/W 1 0 0 0 0 0 Default 0 0 0 0 0 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 0 0 0 0 0 0 0 0 MC PE [2] MC PE [1] MC PE [0] 0 0 0 0 0 0 0 0 0 0 1 MCPE [2:0]: Specifies VCOM alternating point. MCPE is enabled when RGB interface is selected.
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R61509V Target Spec Frame Marker Control (R090h) R/W RS R/W 1 IB15 IB14 IB13 IB12 IB11 IB10 Default FM KM FMI FMI FMI [2] [1] [0] 0 0 0 0 IB9 0 0 0 0 0 0 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 FMP FMP FMP FMP FMP FMP FMP FMP FMP [8] [7] [6] [5] [4] [3] [2] [1] [0] 0 0 0 0 0 0 0 0 0 FMI[2:0]: Sets FMARK output interval by FMI register setting according to the update period of display data and transfer rate.
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R61509V Target Spec Power Control Power Control 1 (R100h) R/W R/W RS IB15 IB14 IB13 IB12 IB11 IB10 1 0 0 0 0 0 Default 0 0 0 0 0 IB9 IB8 BT BT BT [2] [1] [0] 0 1 1 IB7 IB6 0 0 0 0 IB5 IB4 AP AP [1] [0] 1 1 IB3 IB2 IB1 IB0 0 DST B 0 0 0 0 0 0 DSTB: When DSTB = 1, the R61509V enters the shut down mode. In shut down mode, the internal logic power supply is turned off to reduce power consumption.
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R61509V Target Spec BT[2:0]: Sets the factor used in the step-up circuits. Select the optimal step-up factor for the operating voltage. To reduce power consumption, set a smaller factor.
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R61509V Target Spec Power Control 2 (R101h) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 R/W 1 0 0 0 0 0 Default 0 0 0 0 0 IB9 IB8 DC1 DC1 DC1 [2] [1] [0] 0 1 0 IB7 0 0 IB6 IB5 IB4 DC0 DC0 DC0 [2] [1] [0] 1 0 0 IB3 IB2 IB1 IB0 0 VC [2] VC [1] VC [0] 0 1 1 1 DC1 [2:0]: Sets step-up clock frequency for Step-up Circuit 2. The step-up clock is in synchronization with internal clock.
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R61509V Target Spec DC0 [2:0]: Sets step-up clock frequency for Step-up Circuit 1. The step-up clock is in synchronization with internal clock. Table 43 Step-up Frequency (Step-up Circuit 2) DC0[2:0] Step-up Circuit 1 Step-up frequency (fDCDC1) 3’h0 Step-up circuit 1 halts 3’h1 Setting inhibited 3’h2 Setting inhibited 3’h3 Setting inhibited 3’h4 FOSC / 8 3’h5 FOSC / 16 3’h6 FOSC / 32 3’h7 Setting inhibited Note 1: Make sure that fDCDC1 ≥ fDCDC2.
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R61509V Target Spec VC[2:0]: Sets VCI voltage level. VC[2:0] VCI1 voltage (Reference voltage for step-up operation) 3’h0 Setting inhibited 3’h1 0.94 x VCILVL 3’h2 0.89 x VCILVL 3’h3 Setting inhibited 3’h4 Setting inhibited 3’h5 0.76 x VCILVL 3’h6 Setting inhibited 3’h7 1.00 x VCILVL Rev. 0.
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■DC0ｘ Value and DCDC1 Step-up Clock Signal Waveform Example DCDC1 performs charge operation and boost operation with the step-up clock generated from the timing generator. The DCDC1 step-up clock frequency is adjusted by setting the division ratio of the reference clock frequency with DC0x register. (To prevent flickering, the DCDC1 step-up clock signal is synchronized with the reference point of display operation in unit of lines.
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R61509V Target Spec Power Control3 (R102h) R/W RS R/W 1 Default IB15 IB14 IB13 IB12 IB11 IB10 VRH VRH VRH VRH VRH 0 [4] [3] [2] [1] [0] R/W R/W R/W R/W R/W 0 0 0 0 0 0 IB9 0 0 IB8 IB7 VCM 1 R R/W R/W 1 1 IB6 0 0 IB5 IB4 PSON PON W W 0 0 IB3 IB2 IB1 IB0 0 0 0 0 0 0 0 0 Note: True values of PSON and PON are not read when instruction read is executed. PON, PSON: Turn power supply ON.
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R61509V Target Spec Power Control 4 (R103h) R/W R/W RS IB15 IB14 IB13 IB12 IB11 IB10 1 0 0 0 Default 0 0 0 IB9 IB8 VDV VDV VDV VDV VDV [4] [3] [2] [1] [0] 0 0 0 0 0 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VDV[4:0]: Selects the factor of VREG1OUT to set the amplitude of VCOM alternating voltage from 0.70 to 1.32. Table 46 VDV[4:0] VCOM amplitude VDV[4:0] VCOM amplitude 5’h0 VREG1OUT x 0.70 5’h10 VREG1OUT x 1.
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R61509V Target Spec RAM Access RAM Address Set (Horizontal Address) (R200h) RAM Address Set (Vertical Address) (R201h) R/W R 200 R 201 R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 AD AD AD AD AD AD AD AD [7] [6] [5] [4] [3] [2] [1] [0] 1 0 0 0 0 0 0 0 0 Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AD AD AD AD AD AD AD AD AD [16] [15] [14] [13] [12] [11] [10] [9] [8] 0 0 0 0 0 0 0 0 0 R/W 1 0 0
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R61509V Target Spec GRAM Data Write (R202h) R/W RS W 1 RAM write data WD[17:0] is transferred via different data bus in different interface operation. RGB interface RAM write data WD[17:0] is transferred via different data bus in different interface operation. WD[17:0]: The R61509V develops data into 18 bits internally in write operation. The format to develop data into 18 bits is different in different interface operation. The GRAM data represents the grayscale level.
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R61509V Target Spec GRAM Data Read (R202h) R/W RS R 1 RAM read data RD[17:0] is transferred via different data bus in different interface operation. RD[17:0]: 18-bit data read from the GRAM. RAM read data RD[17:0] is transferred via different data bus in different interface operation. When the R61509V reads data from the GRAM to the microcomputer, the first word read immediately after RAM address set is not outputted. Therefore, data on the data bus is invalid.
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R61509V Target Spec NVM Data Read / NVM Data Write (R280h) R 280h R/W RS IB15 IB14 IB13 IB12 IB11 IB10 R/W 1 1 VC M [6] VC M [5] VC M [4] VC M [3] Default 1 1 1 1 1 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 VC M [2] VC M [1] VC M [0] UID UID UID UID UID UID UID UID [7] [6] [5] [4] [3] [2] [1] [0] 1 1 1 1 1 1 1 1 1 1 1 UID[3:0]: Used to temporarily store NVM data such as used identification code.
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R61509V Target Spec Table 48 VCM [6:0] VCOMH voltage VCM [6:0] VCOMH voltage 7’h00 VREG1OUT x 0.492 7’h40 VREG1OUT x 0.748 7’h01 VREG1OUT x 0.496 7’h41 VREG1OUT x 0.752 7’h02 VREG1OUT x 0.500 7’h42 VREG1OUT x 0.756 7’h03 VREG1OUT x 0.504 7’h43 VREG1OUT x 0.760 7’h04 VREG1OUT x 0.508 7’h44 VREG1OUT x 0.764 7’h05 VREG1OUT x 0.512 7’h45 VREG1OUT x 0.768 7’h06 VREG1OUT x 0.516 7’h46 VREG1OUT x 0.772 7’h07 VREG1OUT x 0.520 7’h47 VREG1OUT x 0.776 7’h08 VREG1OUT x 0.
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R61509V Target Spec 7’h38 VREG1OUT x 0.716 7’h78 7’h39 VREG1OUT x 0.720 7’h79 VREG1OUT x 0.972 VREG1OUT x 0.976 7’h3A VREG1OUT x 0.724 7’h7A VREG1OUT x 0.980 7’h3B VREG1OUT x 0.728 7’h7B VREG1OUT x 0.984 7’h3C VREG1OUT x 0.732 7’h7C VREG1OUT x 0.988 7’h3D VREG1OUT x 0.736 7’h7D VREG1OUT x 0.992 7’h3E VREG1OUT x 0.740 7’h7E VREG1OUT x 0.996 7’h3F VREG1OUT x 0.744 7’h7F VREG1OUT x 1.000 Notes: 1. Make sure the VCOMH level is between 3.0V to (DDVDH-0.5)V. 2.
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R61509V Target Spec Window Address Control Window Horizontal RAM Address Start (R210h), Window Horizontal RAM Address End (R211h) Window Vertical RAM Address Start (R212h), Window Vertical RAM Address End (R213h) R 210 R 211 R 212 R 213 R/W RS R/W 1 0 0 0 0 0 0 0 Default 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 Default 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 Default 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 Default 0 0 0 0 0 0 0 R/W R/W R/W IB15 IB14 IB13 IB12 IB11 I
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R61509V Target Spec γ Control γ Control 1 ~ 14 (R300h to R309h) R/W R 300 W RS 1 Default R 301 W 1 Default R 302 R 303 R 304 R 305 W R R R 308 R 309 0 0 PR0 P01 [3] PR0 P01 [2] IB8 PR0 P01 [1] PR0 P01 [0] IB5 0 0 0 0 0 0 IB4 IB1 IB0 PR0 PR0P PR0P PR0P P00 00[4] 00[3] 00[2] [1] PR0 P00 [0] 0 0 0 0 0 0 0 0 PR0 P04 [3] PR0 P04 [2] PR0 P04 [1] PR0 P04 [0] PR0 P03 [3] PR0 P03 [2] PR0 P03 [1] PR0 P03 [0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PR0 P06 [4]
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R61509V PR0P00[4:0] PR0N00[4:0] PR0P01[4:0] PR0N01[4:0] PR0P02[4:0] PR0N02[4:0] PR0P03[3:0] PR0N03[3:0] PR0P04[3:0] PR0N04[3:0] PR0P05[3:0] PR0N05[3:0] PR0P06[4:0] PR0N06[4:0] PR0P07[4:0] PR0N07[4:0] PR0P08[4:0] PR0N08[4:0] PI0P0~1[1:0] PI0N0~1[1:0] PI0P2~3[1:0] PI0N2~3[1:0] Target Spec Adjusts reference level for positive polarity output R0 Adjusts reference level for negative polarity output R0 Adjusts reference level for positive polarity output R1 Adjusts reference level for negative polarity output
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R61509V Target Spec Base Image Display Control Base Image Number of Line (R400h) Base Image Display Control (R401h) Base Image Vertical Scroll Control (R404h) R/W R 400 RS 401 R 404 IB9 NL NL NL NL NL NL [5] [4] [3] [2] [1] [0] 0 1 1 0 1 0 1 0 0 0 0 0 Default 0 0 0 0 0 R/W 1 Default R IB15 IB14 IB13 IB12 IB11 IB10 R/W R/W GS IB8 IB7 IB6 IB5 IB4 IB3 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 Default 0 0 0 0 0 0 0 I
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R61509V Target Spec Table 50 VLE Base image 0 Fixed 1 Scrolling enabled REV: Grayscale level of a image is inverted when REV = 1. This enables the R61509V to display the same image from the same set of data both on normally black and white panels.
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R61509V Target Spec Table 53 NL [5:0] 6’h00 Number of drive line NL [5:0] Number of drive line Setting inhibited 6’h1C 6’h01 16 lines 6’h1D 240 lines 6’h02 24 lines 6’h1E 248 lines 6’h03 32 lines 6’h1F 256 lines 6’h04 40 lines 6’h20 264 lines 6’h05 48 lines 6’h21 272 lines 6’h06 56 lines 6’h22 280 lines 6’h07 64 lines 6’h23 288 lines 6’h08 72 lines 6’h24 296 lines 6’h09 80 lines 6’h25 304 lines 6’h0A 88 lines 6’h26 312 lines 6’h0B 96 lines 6’h27 320 lines
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R61509V Target Spec Table 54 Gate scan start position SCN[5:0] SM=0 SM=1 GS=0 GS=1 GS=0 GS=1 6’h00 G1 G(N) G1 G(2N-432) 6’h01 G9 G(N+8) G17 G(2N-416) 6’h02 G17 G(N+16) G33 G(2N-400) 6’h03 G25 G(N+24) G49 G(2N-384) 6’h04 G33 G(N+32) G65 G(2N-368) 6’h05 G41 G(N+40) G81 G(2N-352) 6’h06 G49 G(N+49) G97 G(2N-336) 6’h07 G57 G(N+56) G113 G(2N-320) 6’h08 G65 G(N+64) G129 G(2N-304) 6’h09 G73 G(N+72) G145 G(2N-288) 6’h0A G81 G(N+80) G161 G(2N-272) 6’h0B
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R61509V Target Spec Partial Display Control Partial Image 1: Display Position (R500h), RAM Address 1 (Start Line Address) (R501h), RAM Address 1 (End Line Address) (R502h) R/W R 500h R 501h R 502h R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 PTD P [8] PTD P [7] PTD P [6] PTD P [5] PTD P [4] PTD P [3] PTD P [2] PTD P [1] PTD P [0] 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 Default 0 0 0 0 0 0 0 R/W 1 0 0 0 0 0 0 0 Default
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R61509V Target Spec Pin Control Test Register (Software Reset) (R600h) R/W RS R/W 1 Default value IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRSR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRSR: When TRSR = 1, test registers are initialized. When TRSR = 0, initialization of test registers halts. Instruction Write R600h TRSR="1" Test registers are initialized (0.
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R61509V Target Spec NVM Control NVM Access Control 1 (R6F0h), NVM Access Control 2 (R6F1h), NVM Access Control 3 (R6F2h) R/W R 6F0h R/W RS 1 Default R 6F1h R/W 1 Default R 6F2h R/W 1 Default IB15 IB14 0 0 IB13 IB12 0 0 0 0 0 NV NV NV DAT DAT DAT [15] [14] [13] 0 0 0 0 NV DAT [12] 0 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 EOP EOP 0 0 0 0 TE 0 0 0 0 [1] [0] 0 0 0 0 0 0 0 0 0 0 0 0 NV NV NV NV NV NV NV NV NV NV NV NV DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT [11] [10
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R61509V Target Spec Write “1” to NVDAT[15].
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●R61509V Instruction List Major category Index Upper Index 0** Rev 0.50 2008. 04.
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R61509V Target Spec Reset Function The R61509V is initialized by the RESETX input. During reset period, the R61509V is in a busy state and instruction from the microcomputer and GRAM access are not accepted. The R61509V’s internal power supply circuit unit is initialized also by the RESETX input. The RESET period must be secured for at least 1ms. In case of power-on reset, wait until the RC oscillation frequency stabilizes (for 1 ms).
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R61509V Target Spec 5 When a RESETX input is entered into the R61509V while it is in shutdown mode, the R61509V starts up the inside logic regulator and makes a transition to the initial state. During this period, the state of the interface pins may become unstable. For this reason, do not enter a RESETX input in shutdown mode. 6 When transferring instruction in either two or three transfers via 8-/9-/16-bit interface, make sure to execute data transfer synchronization after reset operation. Rev. 0.
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R61509V Target Spec Basic Mode Operation of the R61509V The basic operation modes of the R61509V are shown in the following diagram. When making a transition from one mode to another, refer to instruction setting sequence.
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R61509V Target Spec Interface and Data Format The R61509V supports system interface for making instruction and other settings, and external display interface for displaying a moving picture. The R61509V can select the optimum interface for the display (moving or still picture) in order to transfer data efficiently. As external display interface, the R61509V supports RGB interface and VSYNC interface, which enables data rewrite operation without flickering the moving picture on display.
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R61509V Target Spec CSX System interface RS WRX (RDX) System interface 18/16/9/8 System DB17-0 RGB interface 18/16 R61509V ENABLE VSYNCX RGB interface HSYNCX DOTCLK Figure 13 Internal clock operation The display operation is synchronized with signals generated from internal oscillator’s clock (OSC) in this mode. All input via external display interface is disabled in this operation. The internal RAM can be accessed only via system interface.
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R61509V Target Spec RGB interface operation (2) This mode enables the R61509V to rewrite RAM data via system interface while using RGB interface for display operation. To rewrite RAM data via system interface, make sure that display data is not transferred via RGB interface (ENABLE = high). To return to the RGB interface operation, change the ENABLE setting first. Then set an address in the RAM address set register and R22h in the index register.
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R61509V Target Spec System Interface The following are the kinds of system interfaces available with the R61509V. The interface operation is selected by setting the IM2/1/0 pins. The system interface is used for instruction setting and RAM access.
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R61509V Target Spec 80-System 18-bit Bus Interface IM[2:0] = 000 CSn CSX A1 RS HOST HWR PROCESSOR R61509V WRX (RDX) (RDX) DB17-0 D31-0 18 Figure 14 18-bit Interface Instruction write Input DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 Instruction IB 15 IB 14 IB 13 IB 12 IB 11 IB 10 IB 9 IB 8 DB 9 DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 IB 7 IB 6 IB 5 IB 4 IB 3 IB 2 IB 1 IB 0 IB 7 IB 6 IB 5 IB 4 IB 3 IB 2 IB 1 IB 0 DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 D
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R61509V Target Spec 80-System 16-bit Bus Interface IM[2:0] = 010 CSn CS: A1 RS HOST HWR PROCESSOR R61509V WR: (RD:) (RD:) DB17-10, 8-1 D15-0 16 Figure 17 16-bit Interface Instruction Input DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 Instruction IB 15 IB 14 IB 13 IB 12 IB 11 IB 10 IB 9 IB 8 IB 7 IB 6 IB 5 IB 4 IB 3 IB 2 IB 1 IB 0 Instruction code Device code read / Instruction read Device code IB 15 IB 14 IB 13 IB
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R61509V Target Spec RAM data write (1-transfer mode: TRI = 0) (EPE=2'h0) Input DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 R5 R4 R3 R2 R1 R0 G5 G4 G3 DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 G2 G1 G0 B5 B4 B3 B2 B1 1 pixel B0 Note: 65,536 colors are available.
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R61509V Target Spec Data Transfer Synchronization in 16-bit Bus Interface Operation The R61509V supports data transfer synchronization function to reset the counters for upper 16-/2-bit and lower 2-/16-bit transfers in 16-bit 2-transfer mode. When a mismatch occurs in upper and lower data transfers due to noise and so on, the 000H instruction is written four times consecutively to reset the upper and lower counters in order to restart the data transfer from upper 2/16 bits.
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R61509V Target Spec 80-System 9-bit Bus Interface When transferring 16-bit instruction, it is divided into upper and lower 8 bits, and the upper 8 bits are transferred first (the LSB is not used). The RAM write data is also divided into upper and lower 9 bits, and the upper 9 bits are transferred first. The unused DB pins must be fixed at either IOVCC or IOGND level. When transferring the index register setting, make sure to write upper byte (8 bits).
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R61509V Target Spec RAM data write Second transfer First transfer Input GRAM write data DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 9 DB 17 DB 6 DB 5 DB 14 DB 13 DB 12 DB 11 DB 10 DB 9 R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 1 pixel Note: Normal display in 262,144 colors.
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R61509V Target Spec 80-System 8-bit Bus Interface When transferring 16-bit instruction, it is divided into upper and lower 8 bits, and the upper 8 bits are transferred first. The RAM write data is also divided into upper and lower 8 bits, and the upper 8 bits are transferred first. The RAM write data is expanded into 18 bits internally as shown below. The unused DB pins must be fixed at either IOVCC1 or GND level. When transferring the index register setting, make sure to write upper byte (8 bits).
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R61509V Target Spec RAM data write (2-transfer mode: TRI = 0) Second transfer First transfer Input DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 R5 R4 R3 R2 R1 R0 G5 G4 G3 DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 G2 G1 G0 B5 B4 B3 B2 B1 1 pixel B0 Note: Normal display in 65,536 colors.
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R61509V Target Spec Data Transfer Synchronization in 8-bit Bus Interface operation The R61509V supports data transfer synchronization function to reset the counters for upper and lower 8bit transfers in 8-bit bus transfer mode. When a mismatch occurs in upper and lower data transfers due to noise and so on, the 00H instruction is written four times consecutively to reset the upper and lower counters in order to restart the data transfer from upper 8 bits.
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R61509V Target Spec Serial Interface The serial interface is selected by setting the IM2/1 pins to the IOVCC/GND levels, respectively. The data is transferred via chip select line (CS), serial transfer clock line (SCL), serial data input line (SDI), and serial data output line (SDO). In serial interface operation, the IM0_ID pin functions as the ID pin, and the DB17-0 pins, not used in this mode, must be fixed at either IOVCC or GND level.
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R61509V Target Spec Instruction Input D 15 D 14 D 13 Instruction IB 15 IB 14 IB 13 First transfer (upper) D D D D9 12 11 10 IB 12 IB 11 IB 10 IB 9 Sec on d t ransfer (lower) D8 D7 D6 D5 D4 D3 D2 D1 D0 IB 8 IB 7 IB 6 IB 5 IB 4 IB 3 IB 2 IB 1 IB 0 D 7 D 6 Sec on d t ransfer (lower) D D D D D 1 5 4 3 2 D 0 G2 G1 G0 B1 Instruction code RAM data write Input D 15 D 14 D 13 GRAM write data R5 R4 R3 First tran sfer (upper) D D D 12 11 10 R2 R1 R0 D 9 D 8 G5 G
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R61509V Target Spec (a) Clock synchronization serial data transfer (basic mode) End of transfer Transfer start CSX input 1 2 3 4 5 6 7 “0” “1” “1” “1” “0” ID RS SCL input 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 D9 D8 D7 D6 D5 D4 D3 D2 D1 LSB MSB SDI input Device ID code 24 RW D15 D14 D13 D12 D11 D10 D0 RS RW Start byte Set IR (index register), instruction, write RAM data SDO output D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 R
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R61509V Target Spec VSYNC Interface The R61509V supports VSYNC interface, which enables displaying a moving picture via system interface by synchronizing the display operation with the VSYNCX signal. VSYNC interface can realize moving picture display with minimum modification to the conventional system operation. VSYNCX CSX HOST PROCESSOR RS R61509V WRX DB17-0, 8-1 16 Figure 33 VSYNC Interface The VSYNC interface is selected by setting DM1-0 = 10 and RM = 0.
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R61509V Target Spec The VSYNC interface has the minimum for RAM data write speed and internal clock frequency, which must be more than the values calculated from the following formulas, respectively. Internal clock frequency (fosc) [Hz] = FrameFrequency × ( DisplayLin es( NL ) + FrontPorch( FP ) + BackPorch( BP )) × 23( clocks ) × var iance 240 × DisplayLines( NL ) RAMWriteSpeed (min .
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R61509V Target Spec RAM write VSYNCX Back porch (14 lines) RC oscillation ±7% [line] Display operation 432 Line processing FP = 2H Main panel Moving picture display (432 lines) RAM write 7.4 MHz Display operation 16.67 [ms] 0 Front porch (2 lines) (60 Hz) BP = 14H VSYNCX Blank period Figure 35 Write/Display Operation Timing via VSYNC Interface Notes to VSYNC Interface Operation 1. The above example of calculation gives a theoretical value.
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R61509V Target Spec 3. The front porch period continues from the end of one frame period to the next VSYNCX input. 4. The instructions to switch from internal clock operation (DM1-0 = 00) to VSYNC interface operation modes and vice versa are enabled from the next frame period. 5. The partial display and vertical scroll functions are not available in VSYNC interface operation. 6. In VSYNC interface operation, set AM = 0 to transfer display data correctly.
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R61509V Target Spec FMARK Interface In the FMARK interface operation, data is written to internal RAM via system interface synchronizing with the frame mark signal (FMARK), realizing tearing less video image while using conventional system interface. FMARK output position is set in units of line using FMP bit. Set the bit considering data transfer speed.
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R61509V Target Spec When transferring data in synchronization with FMARK signal, minimum RAM data write speed and internal clock frequency must be taken into consideration. They must be more than the values calculated from the following equations. Internal clock frequency (fosc) [Hz] = FrameFrequency × ( DisplayLin es( NL ) + FrontPorch( FP ) + BackPorch( BP )) × 23( clocks ) × var iance 240 × DisplayLin es( NL ) RAMWriteSp eed (min .
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R61509V Target Spec starts the display operation of the data written in that line and can write moving picture data without causing flicker on the display. RAM write Back porch (14 lines) RC oscillation 7% [line] 432 Front porch (2 lines) Display operation RAM write 7.4MHz Line processing FMARK Main panel Moving picture display (432 lines) Display operation 0 FP+BP=16H [ms] 16.
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R61509V Target Spec Table 60 Table 61 FMP[8:0] FMARK output position FMI[2] FMI[1] FMI[0] FMARK Output interval 9’h000 0 0 0 0 9’h001 1st line One frame period 0 0 1 2nd line 2 frame periods 9’h002 0 1 1 4 frame periods 1 0 1 : 9’h1BD 445th line 9’h1BE 446th line 9’h1BF 447 line 9’h1C0 ~ 1FF Setting disabled th Rev. 0.
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R61509V Target Spec FMP Setting Example FMARK output position FMP=9’h008 FMP=9’h008 NL=6’h35 (432 lines) FP=4’h8 BP=4’h8 VL=8’h00 Line address 0 (1st line) 1 (2nd line) 2 (3rd line) 3 (4th line) 4 (5th line) 5 (6th line) 6 (7th line) 7 (8th line) 8 (1st line) 9 (2nd line) 10 (3rd line) Base image Back porch RAM physical line address AD[16:8]=9’h000 AD[16:8]=9’h001 AD[16:8]=9’h002 Display area NL=6'h35 439 (432nd line) 440 (1st line) 441 (2nd line) 442 (3rd line) 443 (4th line) 444 (5th line) 445 (
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R61509V Target Spec RGB Interface The R61509V supports the RGB interface. The interface format is set by RM[1:0] bits. The internal RAM is accessible via RGB interface. Table 62 RGB interface RIM 0 1 Note: RGB Interface DB Pin 18-bit RGB interface DB17-0 16-bit RGB interface Using multiple interface at a time is prohibited. DB17-13, DB11-1 RGB Interface The display operation via RGB interface is synchronized with VSYNCX, HSYNCX, and DOTCLK.
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R61509V Target Spec Polarities of VSYNCX, HSYNCX, ENABLE, and DOTCLK Signals The polarities of VSYNCX, HSYNCX, ENABLE, and DOTCLK signals can be changed by setting the DPL, EPL, HSPL, and VSPL bits, respectively for convenience of system configuration. 㪟㫊㫐㫅㪺㪟㪙㪧㪟㪘㪻㫉㪟㪝㪧㪭㫊㫐㫅㪺㪙㪧㪭㪙㪧㪭㪘㪻㫉 Valid data period 㪭㪝㪧㪝㪧 Figure 43 Table 63 Parameters Symbols Min. Typ. Max.
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R61509V Target Spec Setting Example of Display Control Clock in RGB Interface Operation Register The display operation via DPI is performed in synchronization with the internal clock (PCLKD) that is generated by dividing PCLK frequency. PCDIVH[3:0]: When PCLKD is High, the number of clocks is set in unit of 1 clock. PCDIVL[3:0]: When PCLKD is Low, the number of clocks is set in unit of 1 clock.
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R61509V Target Spec RGB Interface Timing The timing relationship of signals in RGB interface operation is as follows. 16-/18-Bit RGB Interface Timing One frame Back porch period Front porch period VSYNCX HSYNCX DOTCLK ENABLE DB17-0 1H or more VSYNCX 1H HLW ҈ 1CLK HSYNCX 1 clock DOTCLK DTST ҈ 1CLK ENABLE DB17-0 Valid data Figure 45 Note: VLW: HLW: DTST: VSYNCX Low period HSYNCX Low period data transfer setup time Rev. 0.
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R61509V Target Spec Moving Picture Display via RGB Interface The R61509V supports RGB interface for moving picture display and incorporates RAM for storing display data, which provides the following advantages in displaying a moving picture. 1. 2. 3. 4.
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R61509V Target Spec 16-Bit RGB Interface The 16-bit RGB interface is selected by setting RIM = 1. The display operation is synchronized with VSYNCX, HSYNCX, and DOTCLK signals. The display data is transferred to the internal RAM in synchronization with the display operation via 16-bit ports while data enable signal (ENABLE) allows RAM access via RGB interface. Instruction bits can be transferred only via system interface.
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R61509V Target Spec 18-bit RGB Interface The 18-bit RGB interface is selected by setting RIM = 0. The display operation is synchronized with VSYNCX, HSYNCX, and DOTCLK signals. The display data is transferred to the internal RAM in synchronization with the display operation via 18-bit ports (DB17-0) while data enable signal (ENABLE) allows RAM access via RGB interface. Instruction bits can be transferred only via system interface.
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R61509V Target Spec Notes to RGB Interface Operation 1. The following functions are not available in RGB interface operation. Table 64 Functions Not Available in RGB Interface operation Function RGB Interface Internal Display Operation Partial display Not available Available Scroll function Not available Available 2. The VSYNCX, HSYNCX, and DOTCLK signals must be supplied during display period. 3.
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R61509V Target Spec RAM Address and Display Position on the Panel The R61509V has memory to store display data of 240RGB x 432 lines. The R61509V incorporates a circuit to control partial display, which allows switching driving method between full-screen display mode and partial display mode. The R61509V makes display arrangement setting and panel driving position control setting separately and specifies RAM area for each image displayed on the panel.
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R61509V Target Spec Display data output position Panel display position Base image RAM address Partial image RAM address 1 RAM write address (HSA,HEA) 9’h000 Partial image PTSA0 PTDP Scan direction 䇼LCD䇽 PTEA0 Base image Window Address (VSA,VEA) NL 9’h1AF Figure 50 RAM Address, Display Position and Drive Position Restrictions in Setting Display Control Instruction There are restrictions in coordinates setting for display data, display position and partial display.
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R61509V Target Spec The following figure shows the relationship among the RAM address, display position, and the lines driven for the display.
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R61509V Target Spec Instruction Setting Example The followings are examples of settings for 240(RGB) x 432(lines) panel. 1. Full screen display (no partial display) The following is an example of settings for full screen display.
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R61509V 2. Target Spec Partial only The following is an example of settings for displaying partial image 1 only and turning off the base image. The partial image 1 is displayed at the position specified by PTDP0 bit.
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R61509V Target Spec Window Address Function The window address function enables writing display data consecutively in a rectangular area (a window address area) made in the internal RAM. The window address area is described by the horizontal address register (start: HSA7-0, end: HEA7-0 bits) and the vertical address register (start: VSA8-0, end: VEA8-0 bits). The AM and ID bits set the transition direction of RAM address (either increment or decrement, horizontal or vertical, respectively).
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R61509V Target Spec Scan Mode Setting The R61509V can set the gate pin assignment and the scan direction in the following 4 different ways by setting SM and GS bits to realize various connections between the R61509V and the LCD panel.
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R61509V Target Spec 8-Color Display Mode The R61509V has a function to display in eight colors. In this display mode, only V0 and V63 are used and power supplies to other grayscales (V1 to V62) are turned off to reduce power consumption. In 8-color display mode, the γ-adjustment registers R300 to R309 are disabled and the power supplies to V1 to V62 are halted. The R61509V does not require GRAM data rewrite for 8-color display by writing the MSB to the rest in each dot data to display in 8 colors.
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R61509V Target Spec Frame-Frequency Adjustment Function The R61509V supports a function to adjust frame frequency. The frame frequency for driving liquid crystal can be adjusted by setting the DIVI, RTNI bits without changing the oscillation frequency. By changing the DIVI and RTNI settings, the R61509V can operate at high frame frequency when displaying a moving picture, which requires the R61509V to rewrite data in high speed, and it can operate at low frame frequency when displaying a still picture.
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R61509V Target Spec Under the above conditions, the frame frequency can be changed according to the table shown below.
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R61509V Target Spec Partial Display Function The partial display function allows the R61509V to drive lines selectively to display partial images by setting partial display control registers. The lines not used for displaying partial images are driven at nonlit display level to reduce power consumption. The power efficiency can be enhanced in combination with 8-color display mode. Check the display quality when using low power consumption functions.
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R61509V Target Spec Liquid Crystal Panel Interface Timing The relationships between RGB interface signals and liquid crystal panel control signals in internal operation and RGB interface operations are as follows. Internal Clock Operation One Frame reference point reference point reference point reference point reference point reference point 1H FMARK (FMP=BP-1) NOWI G1 G2 G432 SDTI S(3n+1) S(3n+2) S(3n+3) SDTI R,G,B R,G,B R,G,B n=0to239 First line Second line VCOM Figure 58 Rev. 0.
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R61509V Target Spec RGB Interface Operation One frame BP FP VSYNCX 1H HSYNCX DOTCLK ENABLE DB 1 2 3 4 5 6 430 431 432 1 2 3 5DOTCLK See note Reference point Reference point 1H FMARK (FMP=BP-1) NOWE G1 G2 G3 G432 SDTE S(3n+1) S(3n+2) S(3n+3) RGB RGB RGB 432 n=0 to 239 432nd line Third line FIrst line Second line VCOM Note: Transfer RGB data in one transfer via 16-bit port Figure 59 Rev. 0.
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R61509V Target Spec γ Correction Function γ Correction Function The R61509V supports γ-correction function to make the optimal colors according to the characteristics of the panel. The R61509V has registers for positive and negative polarities. γ Correction Circuit The following figure shows the γ-correction circuit.
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R61509V Target Spec γ Correction Registers The γ-correction registers include 42 bits for each of R, G, and B dots and 8-bit interpolation adjustment registers.
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R61509V Target Spec Table 71 Reference Level Adjustment Registers and Resistors Resistor R0 R1 R2 R3 R4 Register Name PR0*00[4:0] PR0*01[4:0] PR0*02[4:0] PR0*03[3:0] PR0*04[3:0] Value Resistance Resistor Register Name Valie Resistance 5'h00 0R 4'h0 4R 5'h01 1R 4'h1 5R 5'h02 2R 4'h2 6R 5'h1F 31R 4'hF 19R 5'h00 1R 5'h00 2R 5'h01 2R 5'h01 3R 5'h02 3R 5'h02 4R 5'h1F 32R 5'h1F 33R 5'h00 2R 5'h00 1R 5'h01 3R 5'h01 2R 5'h02 4R 5'h02 3R 5'h1F 33R 5'h
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R61509V Target Spec Interpolation Registers Table 72 Interpolation Registers Gamma Control Interpolation adjustment V2~V7 V56~V61 Positive polarity Negative polarity PI0P0[1:0] PI0N0[1:0] PI0P1[1:0] PI0N1[1:0] PI0P2[1:0] PI0N2[1:0] PI0P3[1:0] PI0N3[1:0] Table 73 Interpolation factor for V2 to V7 (See “Grayscale Voltage Calculation Formula” for IPV* level) PI0*0[1:0] 2'h0 2'h1 2'h2 2'h3 PI0*1[1:0] IPV2 IPV3 IPV4 IPV5 IPV6 IPV7 2'h0 81% 67% 52% 39% 26% 13% 2'h1 78% 61% 43%
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R61509V Target Spec Table 74 Interpolation Factor for V56 to V61 PI0*3[1:0] 2'h0 2'h1 2'h2 2'h3 PI0*2[1:0] IPV56 IPV57 IPV58 IPV59 IPV60 IPV61 2'h0 87% 74% 61% 48% 33% 19% 2'h1 89% 78% 67% 57% 39% 22% 2'h2 92% 85% 77% 69% 48% 27% 2'h3 93% 86% 79% 72% 50% 28% 2'h0 86% 72% 58% 44% 32% 20% 2'h1 88% 76% 64% 52% 38% 24% 2'h2 91% 83% 74% 65% 48% 30% 2'h3 92% 84% 77% 69% 50% 31% 2'h0 85% 70% 54% 39% 30% 22% 2'h1 87% 74% 61% 47% 37%
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R61509V Target Spec Table 75 Grayscale Voltage Calculation Formula Grayscale voltage Formula Grayscale voltage Formula V0 ΔV ｘ Σ（R1～R8)/SUMR V32 V43 + (V20 - V43) x 11/23 V1 ΔV ｘ Σ（R2～R8)/SUMR V33 V43 + (V20 - V43) x 10/23 V2 V8 + (V1 - V8) x IPV2 V34 V43 + (V20 - V43) x 9/23 V3 V8 + (V1 - V8) x IPV3 V35 V43 + (V20 - V43) x 8/23 V4 V8 + (V1 - V8) x IPV4 V36 V43 + (V20 - V43) x 7/23 V5 V8 + (V1 - V8) x IPV5 V37 V43 + (V20 - V43) x 6/23 V6 V8 + (V1 - V8) x IPV6 V38 V43 + (V20
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R61509V Target Spec Frame Memory Data and the Grayscale Voltage Table 76 Grayscale Voltage Frame memory data REV = 1 Grayscale Voltage REV = 0 Frame memory data REV = 1 REV = 0 Positive polarity Negative polarity Positive polarity Negative polarity 6'h20 V32 V31 V31 V32 V1 6'h21 V33 V30 V30 V33 V61 V2 6'h22 V34 V29 V29 V34 V60 V3 6'h23 V35 V28 V28 V35 V59 V59 V4 6'h24 V36 V27 V27 V36 V5 V58 V58 V5 6'h25 V37 V26 V26 V37 V6 V57 V57 V6 6'h26 V38 V25
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R61509V Target Spec Power Supply Generating Circuit The following figures show the configurations of liquid crystal drive voltage generating circuit of the R61509V. Power Supply Circuit Connection Example 1 (VCI1 = VCIOUT) In the following example, the VCI1 level can be adjusted.
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R61509V Target Spec Power Supply Circuit Connection Example 2 (VCI1 = VCI Direct Input) In the following example, the electrical potential VCI is directly applied to VCI1. In this case, the VCIOUT level cannot be adjusted internally but step-up operation becomes more effective. Make sure that VCI≤ 3.0V. (1) VREG1OUT (2) VREG1 ࡟ࠡࡘ࡟࡯࠲ 㓏⺞㔚࿶ ↢ᚑ࿁〝 VCILVL VCIOUT ಴ജ࿁〝 ౝㇱၮḰ 㔚࿶↢ᚑ࿁〝 ࠰࡯ࠬ ࠼࡜ࠗࡃ VCOMR VCI1 VCI S1-720 VCOMH (16) C11M See note 3.
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R61509V Target Spec Specifications of Power-supply Circuit External Elements The specifications of external elements connected to the power-supply circuit of the R61509V are as follows.
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R61509V Target Spec Voltage Setting Pattern Diagram The following are the diagrams of voltage generation in the R61509V and the TFT display application voltage waveforms and electrical potential relationship. VGH BT Internal reference 㩷 voltage (VCIR) VRH VCILVL(2.5~3.3V) VCC(2.5~3.3V) DDVDH VREG1OUT VC VREG1OUT BT VCM/VCOMR IOVCC(1.65~3.3V) VCOMH VCI1 VDV GND(0V) VCOML VCL BT VGL Figure 63 Notes: 1.
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R61509V Target Spec Liquid Crystal Application Voltage Waveform and Electrical Potential VGH VREG1OUT VCOMH VCOM VCOML Sn (source driver output) Gn (panel interface output) Figure 64 Rev. 0.
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R61509V Target Spec VCOMH and VREG1OUT Voltage Adjustment Sequence When adjusting the VCOMH voltage by setting VCM[6:0] (R280h, internal VCOMH level adjustment circuit), follow the sequence below. The R61509V can retain permanently the VREG1OUT and VCOMH level adjustment setting values in NVM. To write data to NVM, see “NVM Control” and NVM Write Sequence”. Display ON Sequence 㩷 VCOM level adjustment R280h: VCM[6:0] Set VCM[6:0] adjustment value.
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R61509V Target Spec NVM Control The R61509V incorporates 16-bit NVM for user’s use. • 7 bits are for VCOM adjustment (VCM register value is stored). • 8 bits are for UID. • 1 bit is for a dummy bit. To write, read and erase data from/to the NVM, follow the sequences below. Data on the NVM is loaded to internal registers automatically when the sequences are performed. • Power On reset • Exit shutdown mode Data stored in the NVM is retained permanently even if power supply is turned off.
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R61509V Target Spec NVM Load (Register Resetting) Sequence Data on the NVM is loaded either automatically or by setting a command. During the following sequence, the data written to the NVM is automatically loaded to the internal register. Except for the shutdown mode Index: 6F0h Command: 16’h0040 TE = 1’b0 CALB = 1’b1 EOP[1:0] = 2’b00 Wait 1ms or more Index: 280h VCM[6:0], UID[7:0] NVM data read Figure 66 NVM Load (Register Resetting) Sequence Rev. 0.
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R61509V Target Spec NVM Write Sequence Defined 16 bit data is written to the selected address. When “0” is written to these bits, the bits are set to “0”. If the data is erased from the bit, the bit is returned to ”1”. The bit to which data is not written should be set to “1”. NVM Write Sequence NVM Load (Register Resetting) Sequence Power supply (VCC, VCI, IOVCC) ON NVM load 6F0h:16’h0040 (CALB=1) 1msec or more 1ms or more VPP1=9.2r0.
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R61509V Target Spec NVM Erase Sequence The data written to the selected 16 bits is erased all together. The bits from which data is erased are set to “1”. To erase data from NVM, make sure VGL < VPP3A, and follow the sequence below after power supply ON sequence. NVM Erase Sequence Power supply ON sequence 㩷㩷 NVM erase power supply setting 㩷 and BT bits To erase data from NVM, set the VC 㩷 as follows to make sure VGL < VPP3A < -9.5V. (R100h): BT[2:0] = 3’h6 (VGL = -10.
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R61509V Target Spec Power Supply Setting Sequence The following are the sequences for setting power supply ON/OFF instructions. Set power supply ON/OFF instructions according to the following sequences in Display ON/OFF, Sleep set/exit sequences. Power Supply ON Sequence Power supply (VCC, VCI, IOVCC) ON 㪭㪚㪠㪠㪦㪭㪚㪚㪭㪚㪚㪞㪥㪛 VCC → IOVCC → VCI or VCC, IOVCC, VCI simultaneously PON=1 R102h: PSON=1, (1) Other mode setting instruction (2) RAM write instruction, etc.
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R61509V Target Spec Power Supply OFF Sequence (B) Liquid crystal power supply ON (DCDC ON) state Display OFF state ‫ޣ‬ᶧ᥏㔚Ḯ ࠝࡈࡈࡠ R102h: PON=0 PSON=0 ‫ޤ‬ 5 frames or more (A) Liquid crystal power supply OFF (DCDC OFF) Display OFF state Power supply (VCC, VCI, IOVCC) OFF VCI IOVCC VCC 㪞㪥㪛 VCI → IOVCC → VCC or VCC, IOVCC, VCI simultaneously Figure 70 Rev. 0.
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R61509V Target Spec Notes to Power Supply ON Sequence When voltages do not rise in the order of VCC, IOVCC and then VCI and have to change the order, please follow the following note. Note Internal operation of the R61509V is unstable until VCC rises. If IOVCC rose before VCC rises, the R61509V may be in “output” status. In this case, do not send or receive any data before power supply is completed. Changing order of voltage input will not cause troubles such as latchup or destruction of the LSI. Rev. 0.
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R61509V Target Spec Instruction Setting Sequence and Refresh Sequence Display ON/OFF Sequences and Refresh Sequence In setting instruction in the R61509V, follow the sequences below. To reduce malfunction caused by noise, execute refresh sequence 1 regularly. To exit shutdown mode, execute refresh sequence 2.
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R61509V Target Spec Shutdown Mode Sequences Shutdown Sequence (Exit shutdown mode by inputting CSX = “Low”) 㩷 18-/16-/9-/8-bit interface operation Display OFF sequence Set shutdown mode Set shutdown mode R100h: DSTB=1 CSX=”Low”(1) CSX=”Low”(2) VDD startup, Oscillation startup period 1ms or more Exit shutdown mode Input CSX = “Low” 6 times. CSX=”Low” (3) CSX=”Low” (4) CSX=”Low” (5) Initialize the R61509V. CSX=”Low” (6) 0.
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R61509V Target Spec Shutdown Sequence (Exit shutdown mode by inputting CSX = “Low” and WRX = “Low” (Index Write)) 㩷 interface operation (1) 18-/16-bit Display OFF sequence Set shutdown mode Set shutdown mode R100h: DSTB=1 Index Write (Data=16’h0000) Index Write (Data=16’h0000) VDD startup, Oscillation startup period 1ms or more Exit shutdown mode Index Write (Data=16’h0000) Initialize the R61509V. Index Write (Data=16’h0000) Index Write (Data=16’h0000) Index Write (Data=16’h0000) 0.
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R61509V Target Spec (2) 9-/8-bit interface operation Display OFF sequence Set shutdown mode Set shutdown mode R100h: DSTB=1 Index Write (Data=8’h00) Index Write (Data=8’h00) VDD startup, Oscillation startup period 1ms or more Exit shutdown mode Index Write (Data=8’h00) Initialize the R61509V.
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R61509V Target Spec 8-Color Mode Setting 262,144 color to 8 color mode 8 color to 262,144 color mode 262,144-color mode display 8-color mode display R00Bh: COL=1 R00Bh: COL=0 8-color mode display 262,144-color mode display Figure 75 Partial Display Setting Partial Display Setting Sequence Full-screen display Partial display setting R500h: PTDP[8:0] R501h: PTSA[8:0] R502h: PTEA[8:0] Base image display OFF Partial display ON R007h: BASEE=0, PTDE=1 8-color display, low power consumption settings
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R61509V Target Spec Absolute Maximum Ratings Table 82 Items Symbol Unit Value Note Power supply voltage 1 VCC, IOVCC V -0.3 ~ +4.6 1, 2 Power supply voltage 2 VCI – AGND V -0.3 ~ +4.6 1, 3 Power supply voltage 3 DDVDH – AGND V -0.3 ~ +6.5 1, 4 Power supply voltage 4 AGND – VCL V -0.3 ~ +4.6 1 Power supply voltage 5 DDVDH – VCL V -0.3 ~ +9.0 1, 5 Power supply voltage 7 AGND– VGL V -0.3 ~ +13.0 1, 6 Power supply voltage 8 VGH – VGL V -0.3 ~ +30.
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R61509V Target Spec Electrical Characteristics DC Characteristics (VCC= 2.50V~3.30V, VCI=2.50V~3.30V, IOVCC=1.65V~3.30V, Ta= -40°C~+85°C *See note 1) Table 83 Items Symbol Unit Test condition Min. Typ. Max. Notes Input high-level voltage VIH V IOVCC=1.65V～3.30V 0.80× IOVCC Input low-level voltage VIL V IOVCC=1.65V～3.30V -0.3 － 0.20× IOVCC 2, 3 VOH1 V IOVCC=1.65V～3.30V， 0.8× IOVCC －－ 2 VOL1 V －－ 0.
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R61509V Target Spec Ici2 mA IOVCC=1.8V, VCC=VCI=2.
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R61509V Target Spec Step-up Circuit Characteristics Table 84 Item Step-up output voltage Unit DDVDH VGH VGL VCLV Test condition Min. Typ. Max. Note V IOVCC=VCC=VCI=2.80[V], fosc=678[kHz], Ta=25℃, VC=3’h1, AP=3’h3, BT=3’h2, DC0=3’h4 (div. 1/8), DC1=3’h2 (div. 1/4), COL=0, D=2’h0, C11=C12=C13=C21=C22=1[uF]/B characteristics, DDVDH=VGH=VGL=VCL=1[uF]/B characteristics, Iload1=-3 [mA], No load on the panel. 4.8 5.1 - - V IOVCC=VCC=VCI=2.
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R61509V Target Spec Power Supply Voltage Range (Ta= -40°C~+85°C, GND=AGND=0V) Table 86 Symbol Unit Min. Typ. Max. Condition Power Supply Voltage IOVCC V 1.65 1.80/2.80 3.30 - Power Supply Voltage VCC V 2.50 2.80 3.30 - Power Supply Voltage VCI Item Power Supply Voltage VPP1 Power Supply Voltage VPP3A V 2.50 2.80 3.30 - V 8.9 9.2 9.5 Write V 8.9 9.2 9.5 Erase V -0.3 0.0 +0.3 Write V -9.5 -9.2 -8.
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R61509V Target Spec AC Characteristics (VCC= 2.50V~3.30V, IOVCC=1.65V~3.30V, Ta= -40°C~+85°C *See note 1) Clock Characteristics Table 88 Item Symbol Oscillation clock fosc Unit kHz Test condition Min. VCC=IOVCC=3.0V Typ. 631 Max. 678 725 9 80-system 18-/16-/9-/8-bit Bus interface Timing Characteristics (1-/2-/3-transfer, IOVCC=1.65V~3.30V) TBD Table 89 Items Bus cycle time Symbol Unit Test condition Min. Typ. Max.
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R61509V Target Spec Clock Synchronous Serial Interface Timing Characteristics (IOVCC=1.65V~3.30V) TBD Table 90 Item Serial clock cycle time Serial clock high-level width Serial clock low-level width Symbol Unit Test condition Min. Typ. Max.
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R61509V Target Spec LCD Driver Output Characteristics Table 92 Item Symbol Unit Test condition Min. Typ. Max. Note VCC=IOVCC =2.
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R61509V Target Spec Notes to Electrical Characteristics Note 1. The DC/AC electrical characteristics of bare die and wafer products are guaranteed at 85℃. Note 2. The following figures illustrate the configurations of input, I/O, and output pins.
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R61509V Target Spec Note 3: Test 1, 2 and 3 pins must be grounded. The VDDTEST and VREFC must be fixed to AGND. The IM0_ID pin must be fixed to IOVCC or be grounded. Note 4: This excludes the current in the output drive MOS. Note 5: This excludes the current in the input/output lines. Make sure that the input level is fixed because through current will increase in the input circuit when the CMOS input level takes a middle range level.
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R61509V Target Spec Timing Characteristics 80-system Bus Interface VIH VIH VIL VIL RS tAH tAS CSX VIH VIH VIL VIL Note 1 PWLW PWLR PWHW PWHR VIH WRX RDX VIH VIL VIH VIL tWRr tWRf tCYCW tCYCR tDSW tH Note 2 VIH VIH Write Data DB17-0 VIL VIL tDDR Note 2 tDHR VOH VOH Read Data DB17-0 VOL VOL Note 1: PWLW and PWLR are defined by the overlap period when CSX is "Low" and either of WRX or RDX is "Low". Note 2: Unused DB pins must be fixed at "IOVCC" or "GND".
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R61509V Target Spec Clock Synchronous Serial Interface Start: S End: P VIH CSX VIL tSCYC tscr tscf tCSU tSCH VIH SCL VIH VIL tSCL VIH VIL VIH VIL tSISU VIL tSISH VIH VIH Input Data SDI tCH VIL Input Data VIL tSOD tSOH VOH1 VOH1 Output Data SDO Output Data VOL1 VOL1 Figure B Clock Synchronous Serial Interface Timing Reset Operation trRES tRES VIH RESETX VIL VIL Figure C Reset Timing Rev. 0.
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R61509V Target Spec RGB Interface trgbf trgbr tSYNCS VSYNCX VIH VIH HSYNCX VIL VIL tENS ENABLE tENH VIH VIH VIL VIL trgbf trgbr PWDL DOTCLK PWDH VIH VIH VIL VIH VIL VIL tCYCD tPDS tPDH VIH DB17-0 VIH Write Data VIL VIL Figure D RGB Interface Timing LCD Driver and VCOM Output Characteristics tDDv Target voltage r35mV VCOM Target voltage r35mV tDDs Target voltage r35mV S1-720 Target voltage r35mV Figure E LCD Driver and VCOM Output Timing Rev. 0.
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Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.
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R61509V Target Spec Revision Record Rev. 0.11 Date 2008/04/25 Page No. Contents of Modification First issue Rev. 0.