User guide

5
SmartBook for Renesas R8C/Tiny Microcontrollers
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1.4 R8C/Tiny Architecture:
As you already know, R8C/Tiny CPU is compatible with other M16C devices to
maintain code compatibility. The architecture is derived using many registers.
Basically these devices are meant for single chip operations because bus
expansion facilities are not available with the controller. The program memory
space is made available within the device. The internal bus width is 8 bits. So, the
CPU accesses all the 16 bit data in two cycles.
The CPU register structure is given here. The CPU contains 13 registers of 16-bit
width. Of these, 4 registers, R0, R1, R2 and R3 are known as Data Registers
meant for data transfer and arithmetic/logic operations. Then comes two registers,