User guide

SmartBook for Renesas R8C/Tiny Microcontrollers

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The address registers A0 and A1 are joined together to

generate a 32 bit address when using 32 bit address register

indirect mode. However, off these 32 bits, only lower 20 bits

are considered to access the required memory location for the

subsequent processing. When using 32 bit register direct mode,

the register pairs R2 and R0, R3 and R1, A1 and A0 join together

to form a 32 bit space for the processing. These register pairs also

generate addresses for few jump operations.

The control register direct mode uses the registers, INTBL, INTBH, ISP, SP, SB,

FB and FLG as the object of the processing. Some times, the contents of these

registers are used as the addresses for the interrupt operations.

The program counter relative mode generates jump addresses to a nearby instruction

and far away instructions using different types of the displacements. For a nearby

jump, only three bits specify a range of zero to seven from the current location

indicated by the program counter. The displacement value can also be indicated

by a byte as well as 16 bit word. During the address calculation, sign bits of the

displacements are taken into account. However, if the result of addition goes beyond

the range of 00000H to FFFFFH, all the bits above 20 will be ignored and the

result is reset to either 00000H or FFFFFH.

4.3 Bit Instruction Addressing:

This category of modes caters to the addressing of bits of the device memory

during boolean operations. Here, the subject of these binary operations is a bit

position. A range of addressing modes is available to take care of these bits.

The control regis-

ter direct mode

uses the regis-

ters, INTBL,

INTBH,

ISP, SP,

SB, FB and FLG as the

object of the pro-

cessing.