User guide

SmartBook for Renesas R8C/Tiny Microcontrollers

www.MightyMicons.com

When any of these software interrupts in the range 0-

31 is executed, the U flag is saved in the stack and

then is cleared to make ISP active before starting the

interrupt service routine. This U flag is restored from the

stack when returning from the service routine.

For other interrupts in the range 32 - 63, the U flag is not

bothered and the SP is selected for further use.

5.3 Hardware Interrupts:

This hardware group contains a few special hardware interrupts and

all other interrupts resulting from the micon’s peripheral functions. These

special interrupts are of non maskable kind. Peripheral interrupts can be

maskable as per the requirements.

5.3.1 Watch Dog Interrupt.

Watch dog timer can generate an interrupt when timer underflow condition happens.

5.3.2 Oscillation Stop Detection Interrupt.

When the main clock is found not operating, this interrupt is activated for further

processing.

5.3.3 Voltage Detection Interrupt.

The internal voltage detector circuit keeps track of the supply voltage and it creates

an interrupt when the supply voltage comes down below or rises above the chip

reference voltage, Vdet.

5.3.4 Single Step Interrupt.

This interrupt is meant for the development tools and is not recommended for the

general use.

5.3.5 Address Match Interrupt.

When the micon executing its program, it keeps track of PC contents to compare

the address of the next instruction with the contents of the Address Match

Registers, RMADs. When there is a match, the micon generates an interrupt.

There are two address match registers, which can be enabled or disabled using



 The micon generates

an interrupt when

executing the UND,

undefined instruction,

with the opcode of

FFH.



In general,

overflow results indicate uncertain

and doubtful operations. Good

programming practices always

look for overflow

generation in all the

computations.