User guide

SmartBook for Renesas R8C/Tiny Microcontrollers

www.MightyMicons.com

5.5 Interrupt Control.

In general, you need to study the operations of

the micon’s interrupt mechanism with care when

you expect to manage many uncertain and

asynchronous events in your applications. The

knowledge on the time taken by the controller to

service the interrupt requests can give you an idea

on the number of uncertain events you can manage

in your project. As you know already, when the

controller gets an interrupt request, it has to finish

executing the current instruction as the first step and

then save the important registers in the stack area before

jumping to execute the service routine meant for that interrupt.

All these operations happening before executing the service

routines are collectively known as the Interrupt Sequence.

The maskable interrupts can be enabled or disabled using I flag of the FLG

which contains information on the priority level in 3 bits known as ILVL0 to ILVL2

and the interrupt active condition in the bit IR (Interrupt Request bit). When that

interrupt is activated, the IR bit contains a one level to indicate the active interrupt

status. These interrupts can be assigned a priority level from zero to seven using

these three bits. Following table gives details of interrupt control register.



 The maskable interrupts can

be enabled or disabled using I

flag of the FLG register. Each

of these interrupts is associated

with an Interrupt Control Reg-

ister, which contains infor-

mation on the priority level in 3 bits known as

ILVL0 to ILVL2 and the interrupt active con-

dition in the bit IR (Interrupt Request

bit).



 When an interrupt happens during

the execution of an instruction, the

micon finalizes the priority of that

interrupt and shifts the program-

ming control to that interrupt’s

service routine after fin-

ishing the current

instruction.