User guide

SmartBook for Renesas R8C/Tiny Microcontrollers

www.MightyMicons.com

all the interrupts are engaged or not available for further use.

The D flag is cleared to zero to indicate that the single step interrupt is disabled.

The U flag initialization is depending upon the interrupt number. This flag becomes

zero for the interrupts up to 31 and the flag does not change for the software

interrupts between 32 and 63 generated by the INT instruction.

4. The CPU’s internal temporary register, which contains the copy of FLG register,

is saved to the stack.

5. The PC is saved to the stack.

6. Now the interrupt priority level of the accepted interrupt is stored in IPL for

further use.

7. PC is set with the starting address of the relevant interrupt service routine.

Now, the processor starts executing instructions from this address.

Then, we proceed to find out the time taken by the controller to react on the

interrupt events that is also known as Interrupt Response Time. The interrupt

response time or interrupt acknowledge time starts when the interrupt is generated

and includes the time required to finish the current instruction and also to finish

the operations of the interrupt sequence which normally takes about 20 cycles.

Address match and single step interrupts require 21 cycles for the interrupt

sequence. The time required to execute the current instruction depends upon the

type of the instruction. A worst case is the execution of DIVX instruction that may

take up to 30 cycles. Considering all this, the worst-case interrupt response time

is about 50 cycles.(2.5 µSec @20MHz)

When the maskable interrupt is accepted, the priority level of that interrupt is

stored in the IPL. This priority level is the highest , level 7, for the interrupts

generated by the watch dog timer, oscillation stop detection and the voltage

detection. The IPL contents do not change for the address match, single step and

the software interrupts.