User guide

51
SmartBook for Renesas R8C/Tiny Microcontrollers
www.MightyMicons.com
5.5.1 Saving the Registers in the Interrupt
Sequence.
The controller saves the contents of the FLG
and PC registers in the stack during interrupt
sequence phase. Totally, a space of 4 bytes is
required to keep this information in the stack. The
four higher order bits of the PC and four higher bits
of FLG register are stored first. Then, eight lower bits
of FLG are saved. Next, higher and lower bytes of PC
are stored one by one.
Apart from above, if the application demands taking care of few more
registers, they should be also saved in the service routine.
When returning from the service routine, on executing the RETI instruction, the
FLG and PC registers will be restored with the original contents to enable the
micon continue from the place where the interrupt occurred.
5.5.2 Managing Multiple Interrupts.
When two or more interrupts are generated during the execution of an instruction,
the interrupt with the highest priority will be attended first and other interrupts are
kept in pending for further processing. Here, the contents of the IPL plays a major
role in determining the next higher priority interrupts.
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When two or
more interrupts
with the same
priority level
occur at the
same time,
the hardware circuit built in
the micon resolves the
interrupt priority
level.