User guide

SmartBook for Renesas R8C/Tiny Microcontrollers

www.MightyMicons.com

Under this mode, each receiving processor is addressed by an ID. A serial

communication cycle consists of an ID sending cycle that identifies the receiving

processor and then a data sending cycle. The multiprocessor bit distinguishes ID

cycles from the data cycles. The master processor starts by sending the ID of the

receiving processor with which it wants to communicate with multiprocessor bit

set to 1. Next, the master sends the data with the multiprocessor bit cleared to 0.

Slaves skip incoming data until they receive data with the multiprocessor bit

set to 1. When they receive data with the multiprocessor bit set to 1,

slaves compare data with their IDs. Processors with non-matching

IDs skip further incoming data until they again receive data with

the multiprocessor bit set to 1.

6.5 Serial Communication Interface – IIC/SSU:

Recently R8C/Tiny controllers come with few important

serial communication interfaces. Because of this, the R8C/

Tiny devices get the required power to interact with the

popular serial interfaces like IIC and SPI. These facilities

are available independent of other serial I/O ports. The

characteristics of these interfaces are given here:

The

multiprocessor

communicating facility

enables several processors to

share a common serial

communication line. Under this

mode, each receiving processor is

addressed by an ID. A serial

communication

cycle consists of an ID

sending cycle that

identifies the receiving

processor and then a

data sending cycle.