User guide

SmartBook for Renesas R8C/Tiny Microcontrollers

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7.12 PWM Mode of Timer RD:

When the timers of R8C/Tiny micon are config-

ured under the PWM mode, they generate pulse

width modulated waveforms in many output pins.

These timers generate many forms of PWM sig-

nals meeting a variety of demands of the system

designers. The PWM generating facility is available

in timers RC and RD.

Technically the PWM facilities can be treated as the ex-

tension of output compare match functions of these timers.

Now, we proceed with the timer RD to get more details of this

PWM generation.

The RD timer has two channels of 16 bit timers, which always count up-

wards. Each of these channels can control up to 4 output lines and generates

PWM waveforms in three of these port lines. These two timers can be used indi-

vidually or can be combined by synchronous signals to generate six PWM sig-

nals with the same period. These timers require two clock sources for the regular

operation. First clock source, anything from the options, f1,f2,f4,f8,f32 or external

clock and fOCO40M ( derived from the on chip high speed oscillator of 40 MHz ,

available only in R8C/Tiny 2X series onwards) should be connected with these

timers for the counting operation. Second clock source, either f1 or fOCO40M

should be connected with the timers for the internal operations.

Each of this 16 bit timer is associated with four compare match registers,

TRDGRAi, TRDGRBi, TRDGRCi and TRDGRDi, where i indicates the selected

timer, either 0 or 1. These four registers contain user defined data for the compare

The RD timer has two channels

of 16 bit timers, which always

count upwards. Each of these

channels can control up to 4

output lines and generates

PWM waveforms in three of

these port lines. These two timers can be used

individually or can be combined by syn-

chronous signals to generate six PWM

signals with the same period. Each of

this 16 bit timer is associated with

four compare match registers,

TRDGRAi, TRDGRBi,

TRDGRCi and

TRDGRDi,