User guide

SmartBook for Renesas R8C/Tiny Microcontrollers

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The status of all these compare match operations are indicated by the corre-

sponding flag bits in the Timer Status Register. These flags are set to one level

when the match is established during the counting operation. Similarly, these

compare match conditions can also be used to generate the interrupts.

7.13 PWM3 Mode of Timer RD:

PWM3 mode of almost similar to PWM mode of the timer with few differences. In

this mode, both the timer channels are combined to generate only two PWM

waveforms in output pins, TRDIOA0 and TRDIOB0. Compare match functions are

extensively used to generate these two PWM signals.

For the PWM signal generated at the TRDIOA0 pin, the compare registers,

TRDGRA0 and TRDGRA1 are used. Similarly, other registers, TRDGRB0 and

TRDGRB1 are responsible for generating the required waveform in the TRDIOB0

pin. There is a facility available with the RD timer to configure other compare

registers, TRDGRC0, TRDGRC1, TRDGRD0 and TRDGRD1 work as the buffer reg-

isters for the active registers TRDGRA0, TRDGRA1, TRDGRB0 and TRDGRB1

respectively. These buffer registers keep the copy of contents of active com-

pare registers and during the compare match operations, they transfer

the contents to the active registers for the continuous and proper opera-

tions.

To generate this type of PWM signals, active compare registers

are loaded with the proper data related to the active output

conditions. As usual, TRDGRA0 contains data meant for the

period of the PWM signal. The timer counter, TRDi is initialized

with zero and the start command is activated by the software.

In PWM3

mode

, both the timer

channels are combined to

generate only two PWM wave-

forms in

output pins,

TRDIOA0 and

TRDIOB0.