User guide

SmartBook for Renesas R8C/Tiny Microcontrollers

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To get the required PWM signals properly, the fol-

lowing conditions are to be met in the program:

(TRDGRB1 ) < ( TRDGRB0 ) < ( TRDGRA0 ) and (

TRDGRA1 ) < ( TRDGRA0).

7.14 Reset Synchronous PWM Mode:

The RD timer, when configured in the Reset Synchro-

nous mode generates three sets of PWM waveforms along

with the pulse signal indicating frequency of the PWM sig-

nal. Each set contains one normal phase PWM signal and

counter phase PWM signal which is just an inverted form of the

normal signal. These PWM signals are available in seven output

pins as shown below:

To enable this timer mode, both the 16 bit timers are combined and TRD0 be-

comes operational for the job. Other timer, TRD1 is ignored during this mode.

Like other modes, a variety of clock options, f1,f2,f4,f8,f32,fOCO40M and exter-

nal clock are available to drive this timer.

During the operation of this mode, four compare match registers, TRDGRB0,

TRDGRA1, TRDGRB1 and TRDGRA0 are used to generate active pulse level. As

usual, TRDRA0 keeps the data indicating the period of the PWM signals. The

following figure gives an idea of the pulse characteristics of the generated signal.

The RD timer, when config-

ured in the Reset Synchro-

nous mode

generates three

sets of PWM waveforms

along with the pulse sig-

nal indicating fre-

quency of the PWM signal. Each set con-

tains one normal phase PWM signal

and counter phase PWM signal which

is just an inverted form of the nor-

mal signal. These PWM sig-

nals are available in

seven output pins.