User guide

79
SmartBook for Renesas R8C/Tiny Microcontrollers
www.MightyMicons.com
The period of the PWM signal is 1/fk * ( m+1) where m is the count value kept in
the TRDGRA0 register and fk is the selected frequency for the counting opera-
tion. For the counter phase wave, the active level is 1/fk * ( n+1). For this discus-
sion, low level is taken as the active level. But, for the signal generation, either
low or high level can be defined as the active level.
Like other PWM generation, the timer TRD0 starts counting operation for a soft-
ware trigger using the defined clock input and for the every clock input, the TRD0
contents are checked with the contents of the compare registers for any match.
When the counting operation is started, the levels of all the output pins are in the
inactive conditions.