User guide

80
SmartBook for Renesas R8C/Tiny Microcontrollers
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Whenever the contents of the timer register, TRD0,
matches with the contents of the predefined compare reg-
isters, the corresponding output pins change the state to
the active level and stays in that state till the end of the
pulse width. At the end of the pulse width, for the match of
TRD0 and TRDGRA0, the output pin, TRDIOC0 changes its
state and generates a pulse waveform equivalent to half of the
PWM waveform generated in other six pins.
7.15 Complementary PWM Mode:
Most of the operations of this mode is similar to the other mode, Reset Syn-
chronous mode, in which the timer generates three sets of PWM waveforms along
with the signal indicating the pulse period of the PWM waveforms. However, there
is an important difference between these two types: The complementary PWM
mode introduces a dead time in the counter phase signals. There is a time delay
introduced between falling edge of counter phase and the rising edge of the nor-
mal phase signal.
In this timer mode, two channels of timer RD are combined to generate three sets
of normal phase and counter phase signals with the same period as shown below.
Another output pin generates a waveform indicating the PWM period. The counter
operating clock options are f1, f2, f4, f8, f32, fOCO40M and the external clock
input.
For this type of PWM signals, both the timers, TRD0 and TRD1 are to be used.
These timers get incremented for a period of PWM signal as defined by the com-
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The complementary
PWM mode
intro-
duces a dead time
in the counter
phase signals.
There is a time delay introduced
between falling edge of counter
phase and the rising edge
of the normal phase
signal.