User guide

SmartBook for Renesas R8C/Tiny Microcontrollers

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pare match register, TRDGRA0 and then get decremented for the next PWM pe-

riod as indicated in the following figure. Because of this kind of arrangement,

these PWM waveforms contain center aligned active output levels.

Like other types of PWM modes, three compare registers; TRDGRB0, TRDGRA1

and TRDGRB1 contain the data relevant to the three sets of complementary PWM

waveforms. Following indicates the period calculation for these PWM signals.

Operating Conditions:

PWM period : 1/fk x (m+2-p) x 2

Dead time : p

Active level width of normal-phase : 1/fk x (m-n-p+1) x 2

Active level width of counter-phase : 1/fk x (n+1-p) x 2

fk : Frequency of count source

m : Value set in the TRDGRA0 register

n : Value set in the TRDGRB0 register (PWM1 output)

Value set in the TRDGRA1 register (PWM2 output)

Value set in the TRDGRB1 register (PWM3 output)

p : Value set in the TRD0 register

During the initialization, TRD0 register is stored with the required dead time and

the other register, TRD1 is allowed to start from zero for every clock input. The

contents of these timers are checked with the compare match registers for every

clock input. All outputs stay in inactive levels.

When the TRDGRB0 register matches with TRD0, the counter phase PWM output

at the pin TRDIOD0 gets the active level. When the TRD1 matches with the other

Similarly, other PWM signals are generated.