SH7641 Series MPU/MCU SuperH RISC Engine Family Model SH7641(HD6417641) Hardware Manual

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Revision Date: Se

. 14

2005

Hardware Manual

Renesas 32-Bit RISC Microcomputer

SuperH™ RISC engine Family / SH7641 Series

SH7641 HD6417641

Rev.4.00

REJ09B0023-0400

SH7641

The revision list can be viewed directly by 

clicking the title page.



The revision list summarizes the locations of 

revisions and additions. Details should always 

be checked by referring to the relevant text.

Summary of content (1036 pages)

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REJ09B0023-0400 The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. 32 SH7641 Hardware Manual Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series SH7641 Rev.4.00 Revision Date: Sep.
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Rev. 4.00 Sep.
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Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.
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General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed. 2. Treatment of Unused Input Pins Note: Fix all unused input pins to high or low level. Generally, the input pins of CMOS products are high-impedance input pins.
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Important Notice on the Quality Assurance for this LSI Although the wafer process and assembly process of this LSI are entrusted to the external silicon foundries, the quality of this LSI is guaranteed for the customers under the quality assurance system of our company. However, if it is clear that our company is responsible for a defective product, we will only offer, after the agreement of both parties, to exchange it with a new product from stock.
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Configuration of This Manual This manual comprises the following items: 1. 2. 3. 4. 5. 6. General Precautions on Handling of Product Configuration of This Manual Preface Contents Overview Description of Functional Modules • CPU and System-Control Modules • On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the module.
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Rev. 4.00 Sep.
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Preface The SH7641 RISC (Reduced Instruction Set Computer) microcomputer includes a Renesas Technology original RISC CPU as its core, and the peripheral functions required to configure a system. Target Users: This manual was written for users who will be using this LSI in the design of application systems. Users of this manual are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers.
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Rules: Register name: The following notation is used for cases when the same or a similar function, e.g. serial communication, is implemented on more than one channel: XXX_N (XXX is the register name and N is the channel number) Bit order: The MSB (most significant bit) is on the left and the LSB (least significant bit) is on the right. Number notation: Binary is B'xxxx, hexadecimal is H'xxxx, decimal is xxxx.
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Abbreviations ADC Analog to digital converter ALU Arithmetic logic unit bpp bits per pixel bps bits per second BSC Bus state controller CODEC Coder-decoder CPG Clock pulse generator CPU Central processing unit CRC Cyclic redundancy check DMAC Direct memory access controller DSP Digital signal processor ESD Electrostatic discharge ECC Error checking and correction etu Elementary time unit FIFO First-in first-out Hi-Z High impedance H-UDI User debugging interface INTC Interr
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USB Universal serial bus WDT Watch dog timer Rev. 4.00 Sep.
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Rev. 4.00 Sep.
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Contents Section 1 Overview................................................................................................1 1.1 1.2 1.3 1.4 Features.................................................................................................................................. 1 Block Diagram ....................................................................................................................... 7 Pin Assignments..............................................................................
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3.2 3.1.5 Shift Operations .................................................................................................... 109 3.1.6 Most Significant Bit Detection Operation ............................................................ 112 3.1.7 Rounding Operation.............................................................................................. 115 3.1.8 Overflow Protection.............................................................................................. 117 3.1.
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6.2 6.3 Register Descriptions ......................................................................................................... 166 6.2.1 Standby Control Register (STBCR)...................................................................... 166 6.2.2 Standby Control Register 2 (STBCR2)................................................................. 167 6.2.3 Standby Control Register 3 (STBCR3)................................................................. 168 6.2.
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9.2 9.3 9.4 9.5 9.6 9.1.1 TRAPA Exception Register (TRA) ...................................................................... 198 9.1.2 Exception Event Register (EXPEVT)................................................................... 199 9.1.3 Interrupt Event Register 2 (INTEVT2)................................................................. 199 Exception Handling Function ............................................................................................ 200 9.2.
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10.6.2 Timing to Clear an Interrupt Source ..................................................................... 240 Section 11 User Break Controller (UBC) ..........................................................241 11.1 Features.............................................................................................................................. 241 11.2 Register Descriptions ......................................................................................................... 243 11.2.
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12.4.4 SDRAM Control Register (SDCR)....................................................................... 314 12.4.5 Refresh Timer Control/Status Register (RTCSR)................................................. 317 12.4.6 Refresh Timer Counter (RTCNT)......................................................................... 319 12.4.7 Refresh Time Constant Register (RTCOR) .......................................................... 319 12.4.8 Reset Wait Counter (RWTCNT) ....................................
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Section 14 U Memory........................................................................................451 14.1 14.2 14.3 14.4 14.5 14.6 14.7 Features.............................................................................................................................. 451 U Memory Access from CPU ............................................................................................ 452 U Memory Access from DSP................................................................................
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16.4 16.5 16.6 16.7 16.3.9 I2C Bus Shift Register (ICDRS)............................................................................ 487 16.3.10 NF2CYC Register (NF2CYC).............................................................................. 487 Operation ........................................................................................................................... 488 16.4.1 I2C Bus Format..................................................................................................
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18.4 18.5 18.6 18.7 18.3.7 Timer General Register (TGR) ............................................................................. 553 18.3.8 Timer Start Register (TSTR) ................................................................................ 554 18.3.9 Timer Synchro Register (TSYR) .......................................................................... 554 18.3.10 Timer Output Master Enable Register (TOER) .................................................... 556 18.3.
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18.7.13 Buffer Operation Setting in Complementary PWM Mode ................................... 636 18.7.14 Reset Sync PWM Mode Buffer Operation and Compare Match Flag .................. 637 18.7.15 Overflow Flags in Reset Sync PWM Mode.......................................................... 638 18.7.16 Conflict between Overflow/Underflow and Counter Clearing ............................. 638 18.7.17 Conflict between TCNT Write and Overflow/Underflow .................................... 639 18.7.
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19.3.12 Line Status Register (SCLSR) .............................................................................. 720 19.4 Operation ........................................................................................................................... 721 19.4.1 Overview............................................................................................................... 721 19.4.2 Operation in Asynchronous Mode ........................................................................ 723 19.
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20.5 20.6 20.7 20.8 20.9 20.10 20.4.4 EP1 Bulk-OUT Transfer (Dual FIFOs) ................................................................ 774 20.4.5 EP2 Bulk-IN Transfer (Dual FIFOs) .................................................................... 776 20.4.6 EP3 Interrupt-IN Transfer..................................................................................... 778 Processing of USB Standard Commands and Class/Vendor Commands .......................... 779 20.5.
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21.3.6 Input Sampling and A/D Conversion Time .......................................................... 810 21.4 Interrupt and DMAC Transfer Request.............................................................................. 812 21.5 Definitions of A/D Conversion Accuracy.......................................................................... 813 21.6 Usage Notes ....................................................................................................................... 815 21.6.
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23.5 23.6 23.7 23.8 23.9 23.4.2 Port D Data Register (PDDR)............................................................................... 850 Port E ................................................................................................................................. 851 23.5.1 Register Description ............................................................................................. 852 23.5.2 Port E Data Register (PEDR)...............................................................
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25.3.12 H-UDI Related Pin Timing................................................................................... 960 25.3.13 USB Module Signal Timing ................................................................................. 962 25.3.14 USB Transceiver Timing ...................................................................................... 963 25.3.15 AC Characteristics Measurement Conditions ....................................................... 964 25.4 A/D Converter Characteristics ......
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Rev. 4.00 Sep.
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Figures Section 1 Overview Figure 1.1 Block Diagram .............................................................................................................. 7 Figure 1.2 Pin Assignments (BGA-256)......................................................................................... 8 Section 2 CPU Figure 2.1 Register Configuration in Each Processing Mode (1) ................................................. 27 Figure 2.2 Register Configuration in Each Processing Mode (2) ............................
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Figure 3.14 Figure 3.15 Figure 3.16 Figure 3.17 Figure 3.18 Figure 3.19 Figure 3.20 Figure 3.21 Figure 3.22 Figure 3.23 Section 4 Figure 4.1 Figure 4.2 Figure 4.3 Data Transfer Operation Flow................................................................................. 119 Single Data-Transfer Operation Flow (Word)......................................................... 120 Single Data-Transfer Operation Flow (Longword) .................................................
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Section 11 User Break Controller (UBC) Figure 11.1 Block Diagram of User Break Controller................................................................ 242 Section 12 Figure 12.1 Figure 12.2 Figure 12.3 Figure 12.4 Bus State Controller (BSC) BSC Functional Block Diagram.............................................................................. 271 Address Space .........................................................................................................
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Figure 12.28 Single Write Timing (Bank Active, Different Row Addresses in the Same Bank) ................................ 364 Figure 12.29 Auto-Refresh Timing ............................................................................................ 366 Figure 12.30 Self-Refresh Timing .............................................................................................. 367 Figure 12.31 Low-Frequency Mode Access Timing ..................................................................
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Figure 13.8 Example of DMA Transfer Timing in Single Address Mode.................................. 436 Figure 13.9 DMA Transfer Example in the Cycle-Steal Normal Mode (Dual Address, DREQ Low Level Detection)......................................................... 437 Figure 13.10 Example of DMA Transfer in Cycle Steal Intermittent Mode (Dual Address, DREQ Low Level Detection)....................................................... 438 Figure 13.
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Figure 16.9 Slave Transmit Mode Operation Timing (1) ........................................................... 494 Figure 16.10 Slave Transmit Mode Operation Timing (2) ......................................................... 495 Figure 16.11 Slave Receive Mode Operation Timing (1)........................................................... 496 Figure 16.12 Slave Receive Mode Operation Timing (2)........................................................... 497 Figure 16.
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Figure 18.20 Figure 18.21 Figure 18.22 Figure 18.23 Figure 18.24 Figure 18.25 Figure 18.26 Figure 18.27 Figure 18.28 Figure 18.29 Figure 18.30 Figure 18.31 Figure 18.32 Figure 18.33 Figure 18.34 Figure 18.35 Figure 18.36 Figure 18.37 Figure 18.38 Figure 18.39 Figure 18.40 Figure 18.41 Figure 18.42 Figure 18.43 Figure 18.44 Figure 18.45 Figure 18.46 Figure 18.47 Figure 18.48 Figure 18.49 Figure 18.50 Figure 18.51 Figure 18.52 Example of PWM Mode Setting Procedure ............................................
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Figure 18.53 Example of Output Phase Switching by Means of UF, VF, WF Bit Settings (2) ............................................................................................... 615 Figure 18.54 Count Timing in Internal Clock Operation............................................................ 619 Figure 18.55 Count Timing in External Clock Operation .......................................................... 619 Figure 18.56 Count Timing in External Clock Operation (Phase Counting Mode)...............
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Figure 18.90 Error Occurrence in Normal Mode, Recovery in Reset-Synchronous PWM Mode........................................................................................................... 649 Figure 18.91 Error Occurrence in PWM Mode 1, Recovery in Normal Mode........................... 650 Figure 18.92 Error Occurrence in PWM Mode 1, Recovery in PWM Mode 1 .......................... 651 Figure 18.93 Error Occurrence in PWM Mode 1, Recovery in PWM Mode 2 .......................... 652 Figure 18.
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Figure 18.117 Output-Level Detection Operation ...................................................................... 682 Section 19 Serial Communication Interface with FIFO (SCIF) Figure 19.1 Block Diagram of SCIF........................................................................................... 687 Figure 19.2 Example of Data Format in Asynchronous Communication (8-Bit Data with Parity and Two Stop Bits) ........................................................... 723 Figure 19.
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Figure 20.16 EP2 PKTE Operation ............................................................................................ 785 Figure 20.17 Example of USB Function Module External Circuitry (For On-Chip Transceiver).................................................................................... 787 Figure 20.18 Example of USB Function Module External Circuitry (For External Transceiver) .................................................................................... 788 Figure 20.
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Section 25 Electrical Characteristics Figure 25.1 Power-On Sequence ................................................................................................ 908 Figure 25.2 EXTAL Clock Input Timing ................................................................................... 917 Figure 25.3 CKIO Clock Input Timing ...................................................................................... 917 Figure 25.4 CKIO and CKIO2 Clock Input Timing .............................................
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Figure 25.27 Synchronous DRAM Single Write Bus Cycle (Auto Precharge, TRWL = 1 Cycle) ..................................................................... 939 Figure 25.28 Synchronous DRAM Single Write Bus Cycle (Auto Precharge, WTRCD = 2 Cycles, TRWL = 1 Cycle) ............................................................... 940 Figure 25.29 Synchronous DRAM Burst Write Bus Cycle (Four Write Cycles) (Auto Precharge, WTRCD = 0 Cycle, TRWL = 1 Cycle) .................................... 941 Figure 25.
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Figure 25.48 Figure 25.49 Figure 25.50 Figure 25.51 Figure 25.52 Figure 25.53 Figure 25.54 Figure 25.55 Figure 25.56 MTU Clock Input Timing ..................................................................................... 956 POE Input/Output Timing ..................................................................................... 957 I2C Bus Interface Input/Output Timing ................................................................. 959 TCK Input Timing...........................................
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Tables Section 1 Overview Table 1.1 Features..................................................................................................................... 1 Table 1.2 Pin functions ............................................................................................................. 9 Table 1.3 Pin Functions .......................................................................................................... 18 Section 2 CPU Table 2.1 Initial Register Values...............................
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Table 2.31 Table 2.32 Table 2.33 DSP Operation Instructions .................................................................................... 90 DC Bit Update Definitions ..................................................................................... 96 Examples of NOPX and NOPY Instruction Codes................................................. 98 Section 3 DSP Operation Table 3.1 Variation of ALU Fixed-Point Operations............................................................ 100 Table 3.
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Table 7.8 LRU and Way Replacement (when W2LOCK = 1 and W3LOCK = 1)............... 186 Section 8 X/Y Memory Table 8.1 X/Y Memory Specifications ................................................................................. 193 Section 9 Exception Handling Table 9.1 Exception Event Vectors....................................................................................... 204 Table 9.2 Type of Reset........................................................................................................
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Table 12.10 Table 12.11 Table 12.11 Table 12.12 Table 12.12 Table 12.13 Table 12.13 Table 12.14 Table 12.15 Table 12.16 Table 12.17 Table 12.18 Table 12.19 Table 12.20 Table 12.21 Table 12.22 Relationship between BSZ1, 0, A2/3ROW1, 0, and Address Multiplex Output (3)........................................................................... 344 Relationship between BSZ1, 0, A2/3ROW1, 0, and Address Multiplex Output (4)-1........................................................................
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Section 14 U Memory Table 14.1 U Memory Specifications ..................................................................................... 451 Section 15 User Debugging Interface (H-UDI) Table 15.1 Pin Configuration.................................................................................................. 456 Table 15.2 H-UDI Commands................................................................................................ 458 Table 15.3 This LSI Pins and Boundary Scan Register Bits..........
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Table 18.27 Table 18.28 Table 18.29 Table 18.30 Table 18.31 Table 18.32 Table 18.33 Table 18.34 Table 18.35 Table 18.36 Table 18.37 Table 18.38 Table 18.39 Table 18.40 Table 18.41 Table 18.42 Table 18.43 Table 18.44 Table 18.45 Output Level Select Function ........................................................................... 558 Output level Select Function............................................................................. 560 Register Combinations in Buffer Operation ......................
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Table 21.4 Table 21.5 A/D Conversion Time (Multi Mode and Scan Mode) .......................................... 811 Interrupt and DMAC Transfer Request ................................................................ 812 Section 22 Pin Function Controller (PFC) Table 22.1 List of Multiplexed Pins........................................................................................ 819 Section 23 I/O Ports Table 23.1 Port A Data Register (PADR) Read/Write Operations ......................................
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Appendix Table A.1 Table A.2 Pin States in Reset State, Power Down Mode, and Bus-Released States When Other Function is Selected.......................................................................... 967 Pin States in Reset State, Power Down Mode, and Bus-Released States When I/O Port is Selected..................................................................................... 971 Rev. 4.00 Sep.
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Section 1 Overview Section 1 Overview This LSI is a single-chip RISC microprocessor that integrates a Renesas Technology original 32bit SuperH RISC engine architecture CPU with a digital signal processing (DSP) extension as its core, with 16-kbyte of cache memory, 16-kbyte of an on-chip X/Y memory, and peripheral functions required for system configuration such as an interrupt controller. This LSI comes in 256pin package.
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Section 1 Overview Items Specification DSP • Mixture of 16-bit and 32-bit instructions • 32-/40-bit internal data paths • Multiplier, ALU, barrel shifter and DSP register • Large DSP data registers  Six 32-bit data registers  Two 40-bit data registers • Extended Harvard Architecture for DSP data bus  Two data buses  One instruction bus Clock pulse generator (CPG) • Max.
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Section 1 Overview Items Specification Cache memory • 16-kbyte cache, mixed instruction/data • 256 entries, 4-way set associative, 16-byte block length • Write-back, write-through, LRU replacement algorithm • 1-stage write-back buffer • Maximum 2 ways of the cache can be locked • Three independent read/write ports X/Y memory  8-/16-/32-bit access from the CPU  Maximum two 16-bit accesses from the DSP  8-/16-/32-bit access from the DMAC Interrupt controller (INTC) User break controller (
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Section 1 Overview Items Specification Bus state controller (BSC) • Physical address space divided into eight areas, four areas (area 0, areas 2 to 4), each a maximum of 64 Mbytes and other four areas (areas 5A, 5B, areas 6A, 6B), each a maximum of 32 Mbytes • The following features settable for each area independently  Bus size (8, 16, or 32 bits), but different support size by each areas  Number of wait cycles (wait read/write settable independently area exists)  Idle wait cycles (same area/anot
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Section 1 Overview Items Specification Advanced user debugger (AUD) • Six output pins • Trace of branch source/destination address • Window data trace function • Full trace function  All trace data can be output by stalling the CPU even when the trace data is not output in time • Real-time trace function  Function to output trace data that can be output at the range not to stall the CPU Multi-function timer pulse unit (MTU) • Maximum 16-pulse input/output • Selection of 8 counter input c
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Section 1 Overview Items Specification Compare match timer • (CMT) • Serial communication interface with FIFO (SCIF) 16-bit counter × 2 channels Selection of four clocks • Interrupt request or DMA transfer request can be generated by compare-match • 3 channels • Asynchronous mode or clock synchronous mode can be selected • Simultaneous transmission/reception (full-duplex) capability • Built-in dedicated baud rate generator • Separate 16-stage FIFO registers for transmission and reception •
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Section 1 Overview 1.2 Block Diagram USB DSP CMT UBC MTU Peripheral-BUS I-BUS U Memory L-BUS X/Y Memory SH3 CPU X-BUS Y-BUS The block diagram of this LSI is shown in figure1.1.
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Section 1 Overview 1.3 Pin Assignments The pin assignments of this LSI is shown in figure 1.2. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 A A B B C C D D E E F F G G H H J K L SH7641 J BGA-256 K (Top view) M N N P P R R T T U U V V W W Y Y 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Figure 1.2 Pin Assignments (BGA-256) Rev. 4.00 Sep.
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Section 1 Overview 1.4 Pin functions Table 1.2 summarizes the pin functions. Table 1.2 Pin functions No. (BGA256) Pin Name Description B2 D7 Data bus C2 D6 Data bus D2 D5 Data bus B1 D4 Data bus E2 D3 Data bus E3 D2 Data bus C1 VssQ Ground for I/O circuits (0V) D3 D1 Data bus D1 VccQ Power supply for I/O circuits (3.3V) E4 D0 Data bus F2 CS3/PTA[3] Chip select 3/Port A F3 Vss Ground (0V) E1 CS2/PTA[2] Chip select 2/Port A F4 Vcc Power supply (1.
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Section 1 Overview No. (BGA256) Pin Name Description J1 DPLS/PTB[8] USB D+ input from Receiver/Port B K3 Vss Ground (0V) K2 A18 Address bus K4 Vcc Power supply (1.8V) K1 A19/PTA[8] Address bus/Port A L1 A20/PTA[9] Address bus/Port A L4 A21/PTA[10] Address bus/Port A M1 A22/PTA[11] Address bus/Port A L3 A23/PTA[12] Address bus/Port A L2 A24/PTA[13] Address bus/Port A M4 VssQ Ground for I/O circuits (0V) N1 AUDCK AUD clock M3 VccQ Power supply for I/O circuits (3.
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Section 1 Overview No. (BGA256) Pin Name Description W1 VccQ Power supply for I/O circuits (3.
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Section 1 Overview No. (BGA256) Pin Name Description W9 TIOC3C/PTE[5] Timer input output 3C/Port E U9 TIOC3A/PTE[7] Timer input output 3A/Port E Y9 TIOC2B/PTE[8] Timer input output 2B/Port E V10 Vss Ground (0V) W10 TIOC2A/PTE[9] Timer input output 2A/Port E U10 Vcc Power supply (1.
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Section 1 Overview No. (BGA256) Pin Name Description Y18 VssQ Ground for I/O circuits (0V) W17 PTF[7] Port F Y19 VccQ Power supply for I/O circuits (3.
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Section 1 Overview No. (BGA256) Pin Name N20 RESETP Power−on Reset request M18 VccQ Power supply for I/O circuits (3.3V) M19 VssQ Ground for I/O circuits (0V) M17 XTAL Clock oscillator pin M20 EXTAL External clock/Crystal oscillator pin L18 Vss Ground (0V) L19 RESETM Manual Reset request L17 Vcc Power supply (1.8V) L20 ASEMD0 ASE mode K20 Vss(PLL2) Ground for PLL 2 (0V) K17 Vcc(PLL2) Power supply for PLL 2 (1.8V) J20 Vcc(PLL1) Power supply for PLL 1 (1.
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Section 1 Overview No. (BGA256) Pin Name F19 DACK0/PTC[11] DMA request acknowledge/Port C D17 Vss Ground (0V) C20 VssQ Ground for I/O circuits (0V) D19 DACK1/PTC[12] DMA request acknowledge/Port C B20 VccQ Power supply for I/O circuits (3.
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Section 1 Overview No.
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Section 1 Overview No. (BGA256) Pin Name C6 A1 Address bus A4 A0/PTA[0] Address bus/Port A D5 Vcc Power supply (1.8V) B6 D15 Data bus D4 Vss Ground (0V) A3 VssQ Ground for I/O circuits (0V) B4 D14 Data bus A2 VccQ Power supply for I/O circuits (3.
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Section 1 Overview Table 1.3 lists the pin functions. Table 1.3 Pin Functions Classification Symbol I/O Name Function Power supply Vcc I Power supply Power supply for the internal LSI. Connect all Vcc pins to the system. There will be no operation if any pins are open. Vss I Ground Ground pin. Connect all Vss pins to the system power supply (0V). There will be no operation if any pins are open. VccQ I Power supply Power supply for I/O pins.
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Section 1 Overview Classification Symbol I/O Name Function Clock CKIO O System clock Supplies the system clock to external devices. CKIO2 O System clock Supplies the system clock to external devices. MD3, MD2, MD0 I Mode set Sets the operating mode. Do not change values on these pins during operation. Operating mode control MD2, MD0 set the clock mode, MD3 set the bus-width mode of area 0.
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Section 1 Overview Classification Symbol I/O Name Function Bus control RD/WR O Read/write Read/write signal BS O Bus start Bus-cycle start WE3/DQMUU/ AH O Byte specification Indicates that bits 31 to 24 of the data in the external memory or device are being written. Selects D31 to D24 when SDRAM is connected. Address hold signal for address/data multiplexed I/O. WE2/DQMUL O Byte specification Indicates that bits 23 to 16 of the data in the external memory or device are being written.
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Section 1 Overview Classification Symbol I/O Name Function Direct memory access controller (DMAC) DREQ0, DREQ1 I DMA-transfer request Input pin for external requests for DMA transfer. DACK0, DACK1 O DMA-transfer request receive Output pin for request receive, in response to external requests for DMA transfer. TEND0 O DMA-transfer end Output pin for DMA transfer end output signal TCK I Test clock TMS I Test mode select Inputs the test-mode select signal.
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Section 1 Overview Classification Symbol I/O Name Function I Clock input External clock input pins TIOC0A TIOC0B TIOC0C TIOC0D I/O Input capture/ output compare match The TGRA_0 to TGRD_0 input capture input/output compare output/PWM output pins. TIOC1A TIOC1B I/O Input capture/ output compare match The TGRA_1 to TGRB_1 input capture input/output compare output/PWM output pins.
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Section 1 Overview Classification Symbol I/O Name Function USB function module XVDATA I Data input Input pin for receive data from USB differential receiver DPLS I D+ input Input pin for D+ signal from USB receiver DMNS I D- input Input pin for D- signal from USB receiver TXDPLS O D+ output D+ transmit output pin to USB transceiver TXDMNS O D- output D- transmit output pin to USB transceiver TXENL O Output enable Output enable pin to USB transceiver VBUS I USB power supply m
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Section 1 Overview Classification Symbol I/O Name I/O ports PTA14 to PTA0 I/O General purpose 15 bits general purpose input/output port pins PTB8 to PTB0 I/O General purpose 9 bits general purpose input/output port pins PTC15 to PTC0 I/O General purpose 16 bits general purpose input/output port pins.
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Section 2 CPU Section 2 CPU 2.1 Registers This LSI has the same registers as the SH-3. In addition, this LSI also supports the same DSPrelated registers as in the SH-DSP. The basic software-accessible registers are divided into four distinct groups: • • • • General registers Control registers System registers DSP registers With the exception of some DSP registers, all of these registers are 32-bit width.
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Section 2 CPU The system registers are accessed by the LDS/STS instructions (the PC is software-accessible, but is included here because its contents are saved in, and restored from, SPC in exception handling). The system registers are: • • • • MACH: Multiply and accumulate high register MACL: Multiply and accumulate low register PR: Procedure register PC: Program counter This section explains the usage of these registers in different modes. Figures 2.1 and 2.
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Section 2 CPU 31 0 31 0 R0_BANK1*1, *2 R1_BANK1*2 R2_BANK1*2 R3_BANK1*2 R4_BANK1*2 R5_BANK1*2 R6_BANK1*2 R7_BANK1*2 R8 R9 R10 R11 R12 R13 R14 R15 R0_BANK0*1, *3 R1_BANK0*3 R2_BANK0*3 R3_BANK0*3 R4_BANK0*3 R5_BANK0*3 R6_BANK0*3 R7_BANK0*3 R8 R9 R10 R11 R12 R13 R14 R15 SR SSR SR SSR GBR MACH MACL PR VBR GBR MACH MACL PR PC SPC PC SPC R0_BANK0*1,*3 R1_BANK0*3 R2_BANK0*3 R3_BANK0*3 R4_BANK0*3 R5_BANK0*3 R6_BANK0*3 R7_BANK0*3 R0_BANK1*1, *2 R1_BANK1*2 R2_BANK1*2 R3_BANK1*2 R4_BANK1*2 R5_BANK1*2 R6_
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Section 2 CPU 39 0 32 31 A0G A1G A0 A1 M0 M1 X0 X1 Y0 Y1 DSR MS ME MOD (c) DSP mode register configuration (DSP = 1) Figure 2.2 Register Configuration in Each Processing Mode (2) Register values after a reset are shown in table 2.1. Table 2.
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Section 2 CPU 2.1.1 General Registers There are sixteen 32-bit general registers (Rn), designated R0 to R15. The general registers are used for data processing and address calculation. With SuperH microcomputer type instructions, R0 is used as an index register. With a number of instructions, R0 is the only register that can be used. With DSP type instructions, eight of the sixteen general registers are used for addressing of X and Y data memory and data memory (single data) that uses the L-bus.
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Section 2 CPU On the other hand, registers R2 to R9 are also used for DSP data address calculation when DSP extension is enabled (see figure 2.4). Other symbols that represent the purpose of the registers in DSP type instructions is shown in [ ]. 31 0 General Registers (DSP mode enabled) R0 R1 X or Y data transfer operation R4, 5 [Ax]: Address register set for X data memory. R8 [x]: Index register for address register set Ax.
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Section 2 CPU Ay1: .REG (R7) Iy: .REG (R9) As0: .REG (R4) ; This is optional, if another alias is required for single data transfer. As1: .REG (R5) ; This is optional, if another alias is required for single data transfer. As2: .REG (R2) As3: .REG (R3) Is: .REG (R8) 2.1.2 ; This is optional, if another alias is required for single data transfer. Control Registers This LSI has 8 control registers: SR, SSR, SPC, GBR, VBR, RS, RE, and MOD (figure 2.5).
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Section 2 CPU and end addresses of a loop (the contents of the RS and RE registers are slightly different from the actual loop start and end addresses). The modulo register, MOD, is provided to implement modulo addressing for circular data buffering. MOD holds the modulo start address (MS) and modulo end address (ME). In order to access RS, RE and MOD, load/store (control register) instructions for these registers are provided. An example for RS is as follows: LDC Rm,RS; Rm -> RS LDC.
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Section 2 CPU 31 0 28 27 1 RB BL 16 15 RC 13 12 0-0 11 10 9 8 7 6 5 4 3 2 1 0 DSP DMY DMX M Q I3 I2 I1 I0 RF1 RF0 S T SR (Status register) RB bit: Register bank bit; used to define the general registers. RB = 1: R0_BANK1 to R7_BANK1 are used as general registers. R0_BANK0 to R7_BANK0 accessed by LDC/STC instructions. RB = 0: R0_BANK0 to R7_BANK0 are used as general registers. R0_BANK1 to R7_BANK1 accessed by LDC/STC instructions. BL bit: Block bit; used to mask exception.
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Section 2 CPU 31 0 Saved status register (SSR) SSR 31 0 Saved program counter (SPC) SPC 31 0 GBR Global base register 31 0 VBR Vector base register 31 0 RS Repeat start register 31 0 RE 31 MOD Repeat end register 16 15 ME 0 MS Modulo register ME: Modulo end address, MS: Modulo start address Saved status register (SSR) Stores current SR value at time of exception to indicate processor status when returning to instruction stream from exception handler.
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Section 2 CPU 2.1.3 System Registers This LSI has four system registers, MACL, MACH, PR and PC (figure 2.6). 31 0 Multiply and accumulate high and low registers (MACH and MACL) Store the results of multiplicationand accumulation operations. MACH MACL 31 0 PR 31 0 Procedure register (PR) Stores the subroutine procedure return address. Program counter (PC) Indicates the start address of the current instruction. PC Figure 2.
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Section 2 CPU When data is read into the upper 16 bits of a register (bits 31 to 16), the lower 16 bits of the register (bits 15 to 0) are automatically cleared. A0 and A1 can be stored in the X or Y memory by this operation, but no other registers can be stored. The third kind of operation is a single-data transfer instruction, "MOVS.W" or "MOVS.L". These instructions access any memory location through the LDB (figure 2.8).
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Section 2 CPU Table 2.2 Destination Register in DSP Instructions Guard Bits Registers A0, A1 Instructions DSP Data transfer A0G, A1G X0, X1 Y0, Y1 M0, M1 Data transfer DSP Data transfer 39 Register Bits 32 31 16 15 Fixed-point, PSHA, PMULS Sign-extended 40-bit result Integer, PDMSB Sign-extended 24-bit result Cleared Logical, PSHL Cleared Cleared MOVS.W Sign-extended 16-bit data MOVS.L Sign-extended 32-bit data MOVS.W Data No update MOVS.
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Section 2 CPU Table 2.3 Source Register in DSP Operations Guard Bits Registers A0, A1 Instructions DSP 39 Register Bits 32 31 Fixed-point, PDMSB, PSHA 40-bit data Integer 24-bit data Logical, PSHL, PMULS 16-bit data Data transfer MOVX/Y.W, MOVS.W 16-bit data MOVS.L 32-bit data A0G, A1G Data transfer MOVS.W Data MOVS.
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Section 2 CPU 39 32 31 0 A0G A0 A1 A1G M0 M1 X0 X1 Y0 Y1 (a) DSP Data Registers 31 8 7 6 5 4 GT Z N V 3 2 CS [2:0] 1 0 DC (b) DSP Status Register (DSR) Reset status DSR: All zeros Others: Undefined Figure 2.7 DSP Registers LDB 16 bits XDB 16 bits YDB 8 bits 32 bits MOVX.W MOVS.W, MOVS.L MOVY.W 31 39 16 MOVS.W, MOVS.L 32 0 A0 A0G A1 A1G M0 DSR 7 M1 0 X0 X1 Y0 Y1 Figure 2.8 Connections of DSP Registers and Buses Rev. 4.00 Sep.
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Section 2 CPU The DSP unit has one control register, the DSP status register (DSR). DSR holds the status of DSP data operation results (zero, negative, and so on) and has a DC bit which is similar to the T bit in the CPU. The DC bit indicates one of the status flags. A DSP data processing instruction controls its execution based on the DC bit. This control affects only the operations in the DSP unit; it controls the update of DSP registers only.
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Section 2 CPU Table 2.
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Section 2 CPU DSR is assigned as a system register and the following load/store instructions are provided: STS DSR,Rn; STS.L DSR,@-Rn; LDS Rn,DSR; LDS.L @Rn+,DSR; When DSR is read by an STS instruction, the upper bits (bits 31 to 8) are all 0. 2.2 Data Formats 2.2.1 Register Data Format (Non-DSP Type) Register operands are always longwords (32 bits) (figure 2.9). When the memory operand is only a byte (8 bits) or a word (16 bits), it is sign-extended into a longword when loaded into a register.
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Section 2 CPU DSP type fixed point 39 With guard bits 31 30 0 –28 to +28 – 2–31 S 31 30 Without guard bits 0 –1 to +1 – 2–31 S 39 31 30 Multiplier input 16 15 0 –1 to +1 – 2–15 S DSP type integer 39 With guard bits 32 31 0 16 15 –223 to +223 – 1 S 31 Without guard bits 0 16 15 –215 to +215 – 1 S 31 Shift amount for arithmetic shift (PSHA) 22 16 15 0 –32 to +32 S 31 Shift amount for logical shift (PSHL) 21 16 15 0 –16 to +16 S 39 31 16 15 0 DSP type logical CPU type inte
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Section 2 CPU 2.2.3 Memory Data Formats Memory data formats are classified into byte, word, and longword. Byte data can be accessed from any address, but an address error will occur if word data starting from an address other than 2n or longword data starting from an address other than 4n is accessed. In such cases, the data accessed cannot be guaranteed (figure 2.11).
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Section 2 CPU Table 2.5 Word Data Sign Extension This LSI's CPU Description Example of Other CPU MOV.W @(disp,PC),R1 R1,R0 Sign-extended to 32 bits, R1 becomes H'00001234, and is then operated on by the ADD instruction. ADD.W ADD ........ .DATA.W #H'1234,R0 H'1234 Note: Immediate data is referenced by @(disp,PC). Load/Store Architecture: Basic operations are executed between registers. In operations involving memory, data is first loaded into a register (load/store architecture).
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Section 2 CPU Table 2.7 T Bit This LSI's CPU Description Example of Other CPU CMP/GE R1,R0 If R0 ≥ R1, the T bit is set. CMP.W R1,R0 BT TRGET0 BGE TRGET0 BF TRGET1 A branch is made to TRGET0 if R0 ≥ R1, or to TRGET1 if R0 < R1. BLT TRGET1 ADD #–1,R0 The T bit is not set by ADD. SUB.W #1,R0 CMP/EQ #0,R0 If R0 = 0, the T bit is set. BEQ TRGET BT TRGET A branch is made if R0 = 0. Immediate Data: Byte immediate data is placed inside the instruction code.
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Section 2 CPU Table 2.9 Absolute Address Referencing Type This LSI's CPU Example of Other CPU Absolute address MOV.L @(disp,PC),R1 MOV.B MOV.B @R1,R0 @H'12345678,R0 ........ .DATA.L H'12345678 16-Bit/32-Bit Displacement: When data is referenced with a 16- or 32-bit displacement, the displacement value is placed in a table in memory beforehand.
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Section 2 CPU 2.4 Instruction Formats 2.4.1 CPU Instruction Addressing Modes The following table shows addressing modes and effective address calculation methods for instructions executed by the CPU core. Table 2.11 Addressing Modes and Effective Addresses for CPU Instructions Addressing Mode Instruction Format Effective Address Calculation Method Calculation Formula Register direct Rn Effective address is register Rn.  (Operand is register Rn contents.
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Section 2 CPU Addressing Mode Instruction Format Register indirect with displacement @(disp:4, Rn) Effective Address Calculation Method Calculation Formula Effective address is register Rn contents with Byte: Rn + disp 4-bit displacement disp added. After disp is Word: Rn + disp × 2 zero-extended, it is multiplied by 1 (byte), Longword: Rn + disp × 4 2 (word), or 4 (longword), according to the operand size.
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Section 2 CPU Addressing Mode Instruction Format PC-relative with @(disp:8, PC) displacement Effective Address Calculation Method Calculation Formula Effective address is PC with 8-bit displacement disp added. After disp is zeroextended, it is multiplied by 2 (word) or 4 (longword), according to the operand size. With a longword operand, the lower 2 bits of PC are masked.
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Section 2 CPU Addressing Mode Instruction Format Immediate 2.4.2 Effective Address Calculation Method Calculation Formula #imm:8 8-bit immediate data imm of TST, AND, OR, or XOR instruction is zero-extended.  #imm:8 8-bit immediate data imm of MOV, ADD, or CMP/EQ instruction is sign-extended.  #imm:8 8-bit immediate data imm of TRAPA instruction is zero-extended and multiplied by 4.  DSP Data Addressing Two different memory accesses are made with DSP instructions.
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Section 2 CPU X/Y Data Addressing: With DSP instructions, the X and Y data memory can be accessed simultaneously using the MOVX.W and MOVY.W instructions. Two address pointers are provided for DSP instructions to enable simultaneous access to X and Y data memory. Only pointer addressing can be used with DSP instructions; immediate addressing is not available.
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Section 2 CPU R8[Ix] R4[Ax] R5[Ax] +2 (INC) +0 (no update) ALU R9[Iy] R6[Ay] R7[Ay] +2 (INC) +0 (no update) AU [Legend] AU: Adder provided for DSP addressing Note: Three address processing methods: 1. Increment 2. Index register addition (Ix/Iy) 3. No increment Post-updating is used in all cases. The address pointer can be decremented by setting in the index register. Figure 2.
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Section 2 CPU The R8 register is the index register (Is) for the address pointer (As). Single data transfer addressing is shown in figure 2.13. 31 0 R2[As] 0 31 R3[As] R4[As] R8[Is] R5[As] –2/–4 (DEC) +2/+4 (INC) +0 (no update) ALU MAB 31 CAB 0 Note: Four address processing methods: 1. No update 2. Index register addition (Is) 3. Increment 4. Decrement Post-increment Pre-decrement Figure 2.
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Section 2 CPU ModAddr: MOV.L ModAddr,Rn; Rn=ModEnd, ModStart LDC Rn,MOD; ME=ModEnd, MS=ModStart .DATA.W mEnd; ModEnd .DATA.W mStart; ModStart ModStart: .DATA : ModEnd: .DATA The start and end addresses are specified in MS and ME, then the DMX or DMY bit is set to 1. When the X/Y data transfer instruction set in DMX/DMY is executed, the address register contents before update are compared with ME*1. If they match, modulo start address MS is stored in the address register as the updated value*2.
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Section 2 CPU An example of modulo addressing is given below. MS = H'7000; ME=H'7004; R4=H'A50070008; DMX = 1; DMY = 0: (Modulo addressing setting for address register Ax) As a result of the above settings, the R4 register changes as follows.
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Section 2 CPU DSP Addressing Operations: DSP addressing operations in the pipeline execution stage (EX), including modulo addressing, are shown below. if ( Operation is MOVX.W MOVY.W ) { ABx=Ax; ABy=Ay; /* memory access cycle uses ABx and ABy.
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Section 2 CPU 2.4.3 CPU Instruction Formats Table 2.13 shows the instruction formats, and the meaning of the source and destination operands, for instructions executed by the CPU core. The meaning of the operands depends on the instruction code. The following symbols are used in the table. xxxx: mmmm: nnnn: iiii: dddd: Instruction code Source register Destination register Immediate data Displacement Table 2.
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Section 2 CPU Instruction Format nm type 15 0 xxxx nnnn mmmm xxxx Source Operand Destination Operand mmmm: register direct nnnn: register direct ADD mmmm: register direct nnnn: register indirect MOV.L Rm,@Rn mmmm: postMACH, MACL increment register indirect (multiplyand-accumulate operation) Sample Instruction Rm,Rn MAC.
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Section 2 CPU Instruction Format d type 15 0 xxxx xxxx dddd dddd Source Operand Destination Operand dddddddd: GBR indirect with displacement R0 (register direct) MOV.
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Section 2 CPU 2.4.4 DSP Instruction Formats This LSI includes new instructions for digital signal processing. The new instructions are of the following two kinds. 1. Memory and DSP register double and single data transfer instructions (16-bit length) 2. Parallel processing instructions processed by the DSP unit (32-bit length) The instruction formats are shown in figure 2.15. 0 15 CPU core instructions 0000 .. .
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Section 2 CPU Double and Single Data Transfer Instructions: The format of double data transfer instructions is shown in table 2.14, and that of single data transfer instructions in table 2.15. Table 2.14 Double Data Transfer Instruction Formats Type Mnemonic X memory NOPX 15 14 13 12 11 10 9 1 1 1 1 0 0 8 7 6 5 4 3 2 0 0 0 0 0 Ax Dx 0 data MOVX.W @Ax,Dx 0 1 transfer MOVX.W @Ax+,Dx 1 0 MOVX.W @Ax+Ix,Dx 1 1 0 1 MOVX.W Da,@Ax+ 1 0 MOVX.W Da,@Ax+Ix 1 1 MOVX.
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Section 2 CPU Table 2.15 Single Data Transfer Instruction Formats Type Mnemonic 15 14 13 12 11 10 9 1 1 0 1 As 6 5 4 3 2 1 0 0 0 0 1 1 0 1 1 MOVS.W @-As,Ds Ds 0:(*) 0 0 data MOVS.W @As,Ds 0:R4 1:(*) 0 1 transfer MOVS.W @As+,Ds 1:R5 2:(*) 1 0 MOVS.W @As+Ix,Ds 2:R2 3:(*) 1 1 MOVS.W Ds,@-As 3:R3 * 1 7 Single Note: 1 8 4:(*) 0 0 MOVS.W Ds,@As 5:A1 0 1 MOVS.W Ds,@As+ 6:(*) 1 0 MOVS.W Ds,@As+Ix 7:A0 1 1 MOVS.L @-As,Ds 8:X0 0 0 MOVS.
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REJ09B0023-0400 Rev. 4.00 Sep. 14, 2005 Page 64 of 982 Note: 1 1 0 1 1 1 MOVY.W Da, @Ay+ MOVY.W Da, @Ay+Iy Da: 0 = A0, 1 = A1 Dy: 0 = Y0, 1 = Y1 Dx: 0 = X0, 1 = X1 Ay: 0 = R6, 1 = R7 Ax: 0 = R4, 1 = R5 MOVY.W Da, @Ay 0 1 0 1 MOVY.W @Ay+Iy, Dy Da 1 1 MOVY.W @Ay+, Dy 0 transfer 0 0 0 Dy MOVY.W @Ay, Dy data Ay 1 NOPY Y memory 0 1 MOVX.W Da, @Ax+Ix 0 0 1 0 1 0 MOVX.W Da, @Ax MOVX.W Da, @Ax+ 1 1 Da 0 0 1 0 Dx Ax 0 MOVX.W @Ax+Ix, Dx 0 0 0 1 0 1 1 0 1 MOVX.
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Type 0 1 0 1 0 1 1 1 0 0 1 1 PSUBC Sx, Sy, Dz PADDC Sx, Sy, Dz PCMP Sx, Sy Reserved Reserved Reserved 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 PABS Sx, Dz PRND Sx, Dz PABS Sy, Dz PRND Sy, Dz Reserved Reserved 1 1 0 0 1 0 1 1 0 PMULS Se, Sf, Dg PADD Sx, Sy, Du 0 0 1 1 0 PSUB Sx, Sy, Du PMULS Se, Sf, Dg 1 0 1 0 Reserved 0 1:Y0 1:M1 1:Y1 1:X1 1:Y1 1 1 0 1 0 1 0 0 0 0:(*1) 1:(*1) 2:(*1) 3:(*1) 4:(*1) 5:A1 6:(*1) 7:A0 8:X0 9:X1 A:Y0 B:Y1 C:M0 D:(*1) E:M1 F:(*1) 3:A1 3:A1 3:M1 3:A1
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REJ09B0023-0400 Rev. 4.00 Sep. 14, 2005 Page 66 of 982 Notes: 1 0 1 1 0 1 0 1 1 [if cc] PSTS MACL, Dz [if cc] PLDS Dz, MACH [if cc] PLDS Dz, MACL 2. [if cc]: DCT (DC bit True), DCF (DC bit False) or none (unconditional instruction) 1. Codes reserved for system use.
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Section 2 CPU 2.5 Instruction Set 2.5.1 CPU Instruction Set The SH-1/SH-2/SH-3 compatible instruction set consists of 67 basic instruction types divided into seven functional groups, as shown in table 2.18. Tables 2.19 to 2.24 show the instruction notation, machine code, execution time, and function. Table 2.
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Section 2 CPU Type Kinds of Instruction Op Code Function Arithmetic 21 MUL Double-precision multiplication (32 × 32 bits) MULS Signed multiplication (16 × 16 bits) operation instructions MULU Unsigned multiplication (16 × 16 bits) NEG Sign inversion NEGC Sign inversion with borrow SUB Binary subtraction SUBC Binary subtraction with carry SUBV Binary subtraction with underflow AND Logical AND operation NOT Bit inversion instructions OR Logical OR TAS Memory test and bit setti
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Section 2 CPU Type Branch instructions Kinds of Instruction Op Code Function Number of Instructions 9 BF Conditional branch, delayed conditional branch (T = 0) BT Conditional branch, delayed conditional branch (T = 1) BRA Unconditional branch BRAF Unconditional branch BSR Branch to subroutine procedure BSRF Branch to subroutine procedure JMP Unconditional branch JSR Branch to subroutine procedure RTS Return from subroutine procedure CLRT T bit clear control CLRMAC MAC register c
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Section 2 CPU The instruction code, operation, and number of execution states of the CPU instructions are shown in the following tables, classified by instruction type, using the format shown below. Instruction Indicated by mnemonic. Instruction Code Operation Execution States T Bit Indicated in MSB ↔ Indicates summary of Value Value of T bit LSB order. operation.
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Section 2 CPU Data Transfer Instructions Table 2.19 Data Transfer Instructions Instruction Instruction Code Operation Execution States T Bit MOV #imm,Rn 1110nnnniiiiiiii imm → Sign extension → Rn 1  MOV.W @(disp,PC),Rn 1001nnnndddddddd (disp × 2 + PC) → Sign extension → Rn 1  MOV.L @(disp,PC),Rn 1101nnnndddddddd (disp × 4 + PC) → Rn 1  MOV Rm,Rn 0110nnnnmmmm0011 Rm → Rn 1 — MOV.B Rm,@Rn 0010nnnnmmmm0000 Rm → (Rn) 1 — MOV.
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Section 2 CPU Instruction Instruction Code Operation Execution States T Bit MOV.L Rm,@(R0,Rn) 0000nnnnmmmm0110 Rm → (R0 + Rn) 1 — MOV.B @(R0,Rm),Rn 0000nnnnmmmm1100 (R0 + Rm) → Sign extension 1 → Rn — MOV.W @(R0,Rm),Rn 0000nnnnmmmm1101 (R0 + Rm) → Sign extension 1 → Rn — MOV.L @(R0,Rm),Rn 0000nnnnmmmm1110 (R0 + Rm) → Rn 1 — MOV.B R0,@(disp,GBR) 11000000dddddddd R0 → (disp + GBR) 1 — MOV.W R0,@(disp,GBR) 11000001dddddddd R0 → (disp × 2 + GBR) 1 — MOV.
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Section 2 CPU Arithmetic Operation Instructions Table 2.
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Section 2 CPU Instruction Instruction Code Operation Execution States 1 T Bit DMULU.L Rm,Rn 0011nnnnmmmm0101 Unsigned operation of Rn × Rm → MACH, MACL 32 × 32 → 4 bits 2(5) * — DT Rn 0100nnnn00010000 Rn – 1 → Rn, if Rn = 0, 1 → T, else 0 → T 1 Comparison result EXTS.B Rm,Rn 0110nnnnmmmm1110 A byte in Rm is sign-extended → Rn 1 — EXTS.W Rm,Rn 0110nnnnmmmm1111 A word in Rm is sign-extended 1 → Rn — EXTU.B Rm,Rn 0110nnnnmmmm1100 A byte in Rm is zero-extended 1 → Rn — EXTU.
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Section 2 CPU Execution States Instruction Instruction Code Operation SUBV 0011nnnnmmmm1011 Rn–Rm → Rn, Underflow → T 1 Rm,Rn T Bit Underflow Notes: 1. The normal minimum number of execution cycles is two, but five cycles are required when the operation result is read from the MAC register immediately after the instruction. 2.
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Section 2 CPU Shift Instructions Table 2.
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Section 2 CPU Branch Instructions Table 2.
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Section 2 CPU System Control Instructions Table 2.
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Section 2 CPU Execution States T Bit Instruction Instruction Code Operation LDC.L @Rm+, R4_BANK 0100mmmm11000111 (Rm) → R4_BANK, Rm + 4 → Rm 4 — LDC.L @Rm+, R5_BANK 0100mmmm11010111 (Rm) → R5_BANK, Rm + 4 → Rm 4 — LDC.L @Rm+, R6_BANK 0100mmmm11100111 (Rm) → R6_BANK, Rm + 4 → Rm 4 — LDC.
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Section 2 CPU Instruction Instruction Code Operation Execution States T Bit STC R7_BANK,Rn 0000nnnn11110010 R7_BANK→ Rn 1 — STC.L SR,@–Rn 0100nnnn00000011 Rn–4 → Rn, SR → (Rn) 1 — STC.L GBR,@–Rn 0100nnnn00010011 Rn–4 → Rn, GBR → (Rn) 1 — STC.L VBR,@–Rn 0100nnnn00100011 Rn–4 → Rn, VBR → (Rn) 1 — STC.L SSR,@–Rn 0100nnnn00110011 Rn–4 → Rn, SSR → (Rn) 1 — STC.L SPC,@–Rn 0100nnnn01000011 Rn–4 → Rn, SPC → (Rn) 1 — STC.
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Section 2 CPU 2.6 DSP Extended-Function Instructions 2.6.1 Introduction The newly added instructions are classified into the following three groups: 1. Additional system control instructions for the CPU unit 2. DSP unit memory-register single and double data transfer 3. DSP unit parallel processing Group 1 instructions are provided to support loop control and data transfer between CPU core registers or memory and new control registers added to the CPU core.
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Section 2 CPU 2.6.2 Added CPU System Control Instructions The new instructions in this class are treated as part of the CPU core functions, and therefore all the added instructions have a 16-bit code length. All the additional instructions belong to the system control instruction group. Table 2.25 summarizes the added system instructions.
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Section 2 CPU Instruction Instruction Code Operation Execution States T Bit STS.L DSR,@-Rn 0100nnnn01100010 Rn – 4 → Rn, DSR → (Rn) 1  STS.L A0,@-Rn 0100nnnn01110010 Rn – 4 → Rn, A0 → (Rn) 1  STS.L X0,@-Rn 0100nnnn10000010 Rn – 4 → Rn, X0 → (Rn) 1  STS.L X1,@-Rn 0100nnnn10010010 Rn – 4 → Rn, X1 → (Rn) 1  STS.L Y0,@-Rn 0100nnnn10100010 Rn – 4 → Rn, Y0 → (Rn) 1  STS.L Y1,@-Rn 0100nnnn10110010 Rn – 4 → Rn, Y1 → (Rn) 1  STC.
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Section 2 CPU 2.6.3 Single and Double Data Transfer for DSP Data Instructions The new instructions in this class are provided to reduce the program code size for DSP operations. All the new instructions in this class have a 16-bit code length. Instructions in this class are divided into two groups: single data transfer instructions and double data transfer instructions.
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Section 2 CPU Table 2.26 Double Data Transfer Instructions Execution States Instruction Instruction Code Operation X memory NOPX data MOVX.W @Ax,Dx transfer 1111000*0*0*00** X memory no access 1  111100A*D*0*01** (Ax) → MSW of Dx, 0 → LSW of Dx 1  111100A*D*0*10** (Ax) → MSW of Dx, 0 → LSW of Dx, Ax + 2 → Ax 1  MOVX.W @Ax+Ix,Dx 111100A*D*0*11** (Ax) → MSW of Dx, 0 → LSW of Dx, Ax + Ix → Ax 1  MOVX.W Da,@Ax 111100A*D*1*01** MSW of Da → (Ax) 1  MOVX.
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Section 2 CPU Table 2.27 Single Data Transfer Instructions Execution States DC Instruction Instruction Code Operation MOVS.W @-As,Ds 111101AADDDD0000 As – 2 → As, (As) → MSW of Ds, 0 → LSW of Ds 1  MOVS.W @As,Ds 111101AADDDD0100 (As) → MSW of Ds, 0 → LSW of Ds 1  MOVS.W @As+,Ds 111101AADDDD1000 (As) → MSW of Ds, 0 → LSW of Ds, As + 2 → As 1  MOVS.W @As+Is,Ds 111101AADDDD1100 (Asc) → MSW of Ds, 0 → LSW of Ds, As + Is → As 1  MOVS.
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Section 2 CPU The correspondence between DSP data transfer operands and registers is shown in table 2.28. CPU core registers are used as a pointer address that indicates a memory address. Table 2.
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Section 2 CPU 2.6.4 DSP Operation Instruction Set DSP operation instructions are instructions for digital signal processing performed by the DSP unit. These instructions have a 32-bit instruction code, and multiple instructions can be executed in parallel. The instruction code is divided into an A field and B field; a parallel data transfer instruction is specified in the A field, and a single or double data operation instruction in the B field.
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Section 2 CPU Table 2.
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Section 2 CPU Table 2.
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Section 2 CPU Instruction Instruction Code Operation DCF 111110********** If DC = 0 & Sy > = 0, Sx << Sy → Dz (arithmetic shift) PSHA Sx,Sy,Dz 10010011xxyyzzzz Execution States DC 1  1 * If DC = 0 & Sy < 0, Sx >> Sy → Dz If DC = 1, nop PSHL Sx,Sy,Dz 111110********** 10000001xxyyzzzz If Sy > = 0, Sx << Sy → Dz (logical shift) If Sy < 0, Sx >> Sy → Dz DCT PSHL Sx,Sy,Dz 111110********** 10000010xxyyzzzz If DC = 1 & Sy > = 0, 1 Sx << Sy → Dz (logical shift)  If DC = 1 & Sy < 0, Sx >> Sy →
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Section 2 CPU Instruction PDMSB Sx,Dz Operation 111110********** Sx → Dz normalization count 1 shift value * Sx → Dz normalization count 1 shift value * If DC = 1, normalization count shift value Sx → Dz 1  1  1  1  MSW of Sx → Dz 1 * MSW of Sy → Dz 1 * If DC = 1, MSW of Sx + 1 → Dz 1  1  1  1  1 * 10011101xx00zzzz PDMSB Sy,Dz 111110********** 1011110100yyzzzz DCT PDMSB Sx,Dz Execution States DC Instruction Code 111110********** 10011110xx00zzzz If DC = 0, no
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Section 2 CPU Instruction PNEG Sy,Dz Instruction Code Operation Execution States DC 111110********** 0 – Sy → Dz 1 * 1  1  1  1  1110100100yyzzzz DCT DCT DCF DCF PNEG Sx,Dz PNEG Sy,Dz PNEG Sx,Dz PNEG Sy,Dz POR Sx,Sy,Dz 111110********** If DC = 1, 0 – Sx → Dz 11001010xx00zzzz If DC = 0, nop 111110********** If DC = 1, 0 – Sy → Dz 1110101000yyzzzz If DC = 0, nop 111110********** If DC = 0, 0 – Sx → Dz 11001011xx00zzzz If DC = 1, nop 111110********** If DC = 0, 0 – Sy
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Section 2 CPU Instruction PDEC Sy,Dz Instruction Code Operation Execution States DC 111110********** Sy [31:16] – 1 → Dz 1 * If DC = 1, Sx [39:16] – 1 → Dz 1  1  1  1  h'00000000 → Dz 1 * 111110********** If DC = 1, h'00000000 → Dz 1  100011100000zzzz If DC = 0, nop 111110********** If DC = 0, h'00000000 → Dz 1  100011110000zzzz If DC = 1, nop 111110********** If imm > = 0, Dz << imm → Dz (arithmetic shift) 1 * 1 * MACH → Dz 1  If DC = 1, MACH → Dz 1  If
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Section 2 CPU Instruction Instruction Code Operation Execution States DC DCT 111110********** If DC = 1, MACL → Dz 1  If DC = 0, MACL → Dz 1  Dz → MACH 1  If DC = 1, Dz → MACH 1  If DC = 0, Dz → MACH 1  Dz → MACL 1  If DC = 1, Dz → MACL 1  If DC = 0, Dz → MACL 1  Sx + Sy + DC → Dz 1 Carry 1 Borrow PSTS MACL,Dz 110111100000zzzz DCF PSTS MACL,Dz 111110********** 110111110000zzzz PLDS Dz,MACH 111110********** 111011010000zzzz DCT PLDS Dz,MACH 111110**********
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Section 2 CPU Table 2.32 DC Bit Update Definitions CS [2:0] Condition Mode Description 0 0 Carry or borrow mode The DC bit is set if an ALU arithmetic operation generates a carry or borrow, and is cleared otherwise. 0 When a PSHA or PSHL shift instruction is executed, the last bit data shifted out is copied into the DC bit. When an ALU logical operation is executed, the DC bit is always cleared.
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Section 2 CPU Conditional Operations and Data Transfer: Some instructions belonging to this class can be executed conditionally, as described earlier. The specified condition is valid only for the B field of the instruction, and is not valid for data transfer instructions for which a parallel specification is made. Examples are shown in figure 2.17. DCT PADD X0,Y0,A0 MOVX.W @R4+,X0 MOVY.
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Section 2 CPU Assignment of NOPX and NOPY Instruction Codes: When there is no data transfer instruction to be parallel-processed simultaneously with a DSP operation instruction, an NOPX or NOPY instruction can be written as the data transfer instruction, or the instruction can be omitted. The instruction code is the same whether an NOPX or NOPY instruction is written or the instruction is omitted. Examples of NOPX and NOPY instruction codes are shown in table 2.33. Table 2.
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Section 3 DSP Operation Section 3 DSP Operation 3.1 Data Operations of DSP Unit 3.1.1 ALU Fixed-Point Operations Figure 3.1 shows the ALU arithmetic operation flow. Table 3.1 shows the variation of this type of operation and table 3.2 shows the correspondence between each operand and registers. 39 31 Guard 0 39 Guard Source 1 0 31 Source 2 ALU GT Z N V DC DSR Guard 39 Destination 31 0 Figure 3.
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Section 3 DSP Operation Table 3.1 Mnemonic Variation of ALU Fixed-Point Operations Function Source 1 Source 2 Destination PADD Addition Sx Sy Dz (Du) PSUB Subtraction Sx Sy Dz (Du) PADDC Addition with carry Sx Sy Dz PSUBC Subtraction with borrow Sx Sy Dz PCMP Comparison Sx Sy — PCOPY Data copy Sx All 0 Dz All 0 Sy Dz All 0 Dz PABS Absolute Sx All 0 Sy Dz PNEG Negation Sx All 0 Dz All 0 Sy Dz All 0 All 0 Dz PCLR Table 3.
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Section 3 DSP Operation Operation Sequence Example PADD X0, Y0, A0 Slot Stage IF MOVX.W @(R4, R8), X0 MOVX.W @R4+, X0 1 2 MOVX MOVX & PADD ID 3 4 5 6 MOVX & PADD MOVX Addressing EX Addressing MOVX MA/DSP MOVX & PADD Previous cycle result is used. Figure 3.2 Operation Sequence Example Every time an ALU arithmetic operation is executed, the DC, N, Z, V, and GT bits in DSR are basically updated in accordance with the operation result.
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Section 3 DSP Operation Negative Value Mode: CS[2:0] = 001: The DC flag indicates the same state as the MSB of the operation result. When the result is a negative number, the DC bit shows 1. When it is a positive number, the DC bit shows 0. The ALU always executes 40-bit arithmetic operation, so the sign bit to detect whether positive or negative is always got from the MSB of the operation result regardless of the destination operand. Some examples are shown in figure 3.4.
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Section 3 DSP Operation Signed Greater Than Mode: CS[2:0] = 100: The DC bit indicates whether or not the source 1 data (signed) is greater than the source 2 data (signed) as the result of compare operation PCMP. So, a PCMP operation should be executed in advance when a conditional operation is executed under this condition mode.
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Section 3 DSP Operation 3.1.2 ALU Integer Operations Figure 3.6 shows the ALU integer arithmetic operation flow. Table 3.3 shows the variation of this type of operation. The correspondence between each operand and registers is the same as ALU fixed-point operations as shown in table 3.2. 39 31 Guard 0 Source 1 39 0 31 Guard Source 2 ALU GT Z N V DC DSR Ignored Cleared Destination Guard 39 0 31 Figure 3.6 ALU Integer Arithmetic Operation Flow Table 3.
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Section 3 DSP Operation In ALU integer arithmetic operations, the lower word of the source operand is ignored and the lower word of the destination operand is automatically cleared. The guard-bit parts are effective in integer arithmetic operations if they are supported. Others are basically the same operation as ALU fixed-point arithmetic operations. As shown in table 3.3, however, this type of operation provides two kinds of instructions only, so that the second operand is actually either +1 or –1.
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Section 3 DSP Operation 39 31 Guard 0 39 Soruce 1 31 Guard 0 Source 2 ALU GT Z N V DC DSR Ignored Guard Cleared 39 Destination 0 31 Figure 3.7 ALU Logical Operation Flow Table 3.
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Section 3 DSP Operation 5. Signed Greater Than Mode: CS[2:0] = 100 The DC bit is always cleared. 6. Signed Greater Than or Equal Mode: CS[2:0] = 101 The DC bit is always cleared. The N bit always indicates the same state as the DC bit set in negative value mode by the CS[2:0] bits. See the negative value mode part above. The Z bit always indicates the same state as the DC bit set in zero value mode by the CS[2:0] bits. See the zero value mode part above.
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Section 3 DSP Operation Table 3.5 Variation of Fixed-Point Multiply Operation Mnemonic Function Source 1 Source 2 Destination PMULS Signed multiplication Se Sf Dg Table 3.6 Correspondence between Operands and Registers Register Se Sf Dg A0   Yes A1 Yes Yes Yes M0   Yes M1   Yes X0 Yes Yes  X1 Yes —  Y0 Yes Yes  Y1  Yes  Note: The multiply operations basically generate 32-bit operation results.
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Section 3 DSP Operation 3.1.5 Shift Operations Shift operations can use either register or immediate value as the shift amount operand. Other source and destination operands are specified by the register. There are two kinds of shift operations. Table 3.7 shows the variation of this type of operation. The correspondence between each operand and registers, except for immediate operands, is the same as the ALU fixed-point operations as shown in table 3.2. Table 3.
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Section 3 DSP Operation In this arithmetic shift operation, all bits of the source 1 and destination operands are activated. The shift amount is specified by the source 2 operand as an integer data. The source 2 operand can be specified by either a register or immediate operand. The available shift range is from –32 to +32. Here, a negative value means the right shift, and a positive value means the left shift.
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Section 3 DSP Operation Overflow Protection: The S bit in SR is also effective for arithmetic shift operation in the DSP unit. See section 3.1.8, Overflow Protection, for details. Logical Shift: Figure 3.10 shows the logical shift operation flow. Left Shift 7g 0g 31 Right Shift 16 15 0 0 Shift out 7g Ignored 0g 31 16 15 0 >=0 Shift amount data: (Source 2) 7g 0g 31 0 Shift out <0 +16 to –16 22 21 16 15 0 Updated GT Sy 5 Z N V DC DSR 0 Imm2 Cleared Figure 3.
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Section 3 DSP Operation 1. Carry or Borrow Mode: CS[2:0] = 000 The DC bit indicates the last shifted out data as the operation result. 2. Negative Value Mode: CS[2:0] = 001 Bit 31 of the operation result is loaded into the DC bit. 3. Zero Value Mode: CS[2:0] = 010 The DC bit is set when the operation result is zero; otherwise it is cleared. 4. Overflow Mode: CS[2:0] = 011 The DC bit is always cleared. 5. Signed Greater Than Mode: CS[2:0] = 100 The DC bit is always cleared. 6.
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Section 3 DSP Operation Every time a PDMSB operation is executed, the DC, N, Z, V, and GT bits in DSR are basically updated in accordance with the operation result. In case of a conditional operation, they are not updated, even though the specified condition is true, and the operation is executed. In case of an unconditional operation, they are always updated with the operation result. 39 31 0 Source 1 or 2 Guard GT Priority encoder Z N V DC DSR Guard 39 Destination 31 Cleared 0 Figure 3.
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Section 3 DSP Operation Table 3.
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Section 3 DSP Operation Table 3.9 Variation of PDMSB Operation Mnemonic Function PDMSB MSB detection Source Source 2 Destination Sx  Dz  Sy Dz The N bit always indicates the same state as the DC bit set in negative value mode by the CS[2:0] bits. See the negative value mode part above. The Z bit always indicates the same state as the DC bit set in zero value mode by the CS[2:0] bits. See the zero value mode part above.
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Section 3 DSP Operation 39 31 Guard 0 H'00008000 Source 1 or 2 Addition ALU GT Z N V DC DSR Destination Guard 39 Cleared 0 31 Figure 3.12 Rounding Operation Flow Rounded result H'00 0002 H'00 0001 Analog value True value H'00 0001 8000 H'00 0002 0000 H'00 0002 8000 0 Figure 3.13 Definition of Rounding Operation Table 3.
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Section 3 DSP Operation 3.1.8 Overflow Protection The S bit in SR is effective for any arithmetic operations executed in the DSP unit, including the SH's standard multiply and MAC operations. The S bit in SR, in SH's CPU core, is used as the overflow protection enable bit. The arithmetic operation overflows when the operation result exceeds the range of two's complement representation without guard-bit parts. Table 3.
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Section 3 DSP Operation 3.1.9 Data Transfer Operation This LSI can execute a maximum of two data transfer operations between the DSP register and the on-chip data memory in parallel for the DSP unit. Three types of data transfer instructions are provided for the DSP unit. 1. Parallel operation type (using XDB and YDB buses) 2. Double data transfer type (using XDB or YDB buses) 3.
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Section 3 DSP Operation X pointer (R4, R5) Y pointer (R6, R7) 0, +2, +R8 0, +2, +R9 XAB [15:1] YAB [15:1] X memory (RAM, ROM) Y memory (RAM, ROM) XDB [15:0] X0 YDB [15:0] Y0 X1 Y1 A0 M0 A1 M1 A0G Not affected for store and cleared for load A1G DSR Cannot be specitied Figure 3.14 Data Transfer Operation Flow Type 2 instructions execute just two data transfer operations. The 16-bit instruction code is used for this type of instructions.
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Section 3 DSP Operation Note: Data transfer by an LDS or STS instruction is possible since DSR is defined as a system register. Pointer (R2, R3, R4, R5) –2, 0, +2, +R8 LAB [31:0] Any memory areas LDB [15:0] X0 Y0 X1 Y1 A0 M0 A1 M1 A0G Not affected for store and cleared for load See description of A0G and A1G. A1G DSR Cannot be specified Figure 3.15 Single Data-Transfer Operation Flow (Word) Rev. 4.00 Sep.
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Section 3 DSP Operation Pointer (R2, R3, R4, R5) –4, 0, +4, +R8 LAB [31:0] Any memory areas LDB [31:0] X0 Y0 X1 Y1 A0 M0 A1 M1 A0G A1G DSR Cannot be specified Figure 3.16 Single Data-Transfer Operation Flow (Longword) All data transfer operations are executed in the MA stage of the pipeline. All data transfer operations do not update any condition code bits in DSR. Rev. 4.00 Sep.
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Section 3 DSP Operation 3.1.10 Local Data Move Instruction The DSP unit of this LSI provides additional two independent registers, MACL and MACH, in order to support SH's standard multiply/MAC operations. They can be also used as temporary storage registers by local data move instructions between MACH/L and other DSP registers Figure 3.17 shows the flow of seven local data move instructions. Table 3.13 shows the variation of this type of instruction.
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Section 3 DSP Operation 3.1.11 Operand Conflict When an identical destination operand is specified with multiple parallel instructions, data conflict occurs. Table 3.14 shows the correspondence between each operand and registers. Table 3.
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Section 3 DSP Operation 3.2 DSP Addressing 3.2.1 DSP Repeat Control This LSI prepares a special control mechanism for efficient repeat loop control. An instruction SETRC sets the repeat times into the repeat counter RC (12 bits), and an execution mode in which a program loop executes repetitively until RC is equal to 1. After completion of the repeat instructions, the RC value becomes 0. Repeat start address register RS keeps the start address of a repeat loop.
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Section 3 DSP Operation #imm is 8 bits while RC is 12 bits. Therefore, to set more than 256 into RC, use Rm. A sample program is shown below. LDRS RptStart; LDRE RptEnd3+4; SETRC #imm; RC = #imm instr0; ; instr1–5 executes repeatedly RptStart: instr1; RptEnd3: instr2; instr3; instr4; RptEnd: instr5; instr6; In this implementation, there are some restrictions to use this repeat control function as follows: 1.
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Section 3 DSP Operation 5. If a repeat loop has four or more instructions in it, any branch instructions (BRA, BSR, BT, BF, BT/S, BF/S, BSRF, RTS, BRAF, RTE, JSR and JMP), repeat control instructions (SETRC, LDRS and LDRE), load instructions for SR, RS, RE, and the TRAPA instruction must not be written within the last three instructions from the bottom of a repeat loop. If written, a general invalid instruction exception handling starts, and a certain address value shown in table 3.16 is stored into SPC.
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Section 3 DSP Operation In figure 3.18, exceptions generated by instructions marked as B and C are handled as follows: • Interrupt and DMA address errors An exception is accepted at neither instruction B or C, and the request is not even saved. A request is detected for the first time and accepted when the next instruction A is executed. Interrupts and DMA address errors are not accepted during a repeat loop with four or less instructions, as shown in 1 to 4 in figure 3.18.
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Section 3 DSP Operation A: Acceptable for any interrupts B and C: Acceptable for some interrupts RC >_1 : 2. 2 repeated steps 1. 1 repeated step Start(End): instr – 1 instr0 instr1 instr2 ;A ;B ;C ;A Start: End: 4. 4 repeated steps Start: End: instr – 1 instr0 instr1 instr2 instr3 instr4 instr4 instr – 1 instr0 instr1 instr2 instr3 3. 3 repeated steps ;A ;B ;C ;C ;A instr – 1 instr0 instr1 instr2 instr3 instr4 Start: End: ;A ;B ;C ;C ;C ;A 5.
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Section 3 DSP Operation Based on this table, the actual repeat programming for various cases should be described as in the following examples: CASE 1: 1 Repeated Instruction LDRS RptStart0+8; LDRE RptStart0+4; SETRC RptCount; - - - RptStart0: instr0; RptStart: instr1; Repeated instruction instr2; CASE 2: 2 Repeated Instructions LDRS RptStart0+6; LDRE RptStart0+4; SETRC RptCount; - - - RptStart0: instr0; RptStart: RptEnd: instr1; Repeated instruction 1 instr2; Repeated instruction 2 ins
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Section 3 DSP Operation CASE 4: 4 or More Repeated Instructions LDRS RptStart; LDRE RptEnd3+4; SETRC RptCount; - - - RptStart0: instr0; RptStart: instr1; Repeated instruction 1 instr2; Repeated instruction 2 instr3; Repeated instruction 3 ---------------------------------------------------------RptEnd3: RptEnd: instrN-3; Repeated instruction N-3 instrN-2; Repeated instruction N-2 instrN-1; Repeated instruction N-1 instrN; Repeated instruction N instrN+1; The examples above can be us
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Section 3 DSP Operation CASE 1: 1 Repeated Instruction REPEAT RptStart, RptStart, RptCount; - - - instr0; RptStart: instr1; Repeated instruction instr2; CASE 2: 2 Repeated Instructions REPEAT RptStart, RptEnd, RptCount; - - - instr0; RptStart: instr1; Repeated instruction 1 RptEnd: instr2; Repeated instruction 2 CASE 3: 3 Repeated Instructions REPEAT RptStart, RptEnd, RptCount; - - - instr0; RptStart: RptEnd: instr1; Repeated instruction 1 instr2; Repeated instruction 2 instr3; Repeated in
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Section 3 DSP Operation CASE 4: 4 or More Repeated Instructions REPEAT RptStart, RptEnd, RptCount; - - - instr0; RptStart instr1; Repeated instruction 1 instr2; Repeated instruction 2 instr3; Repeated instruction 3 ---------------------------------------------------------- RptEnd instrN-3; Repeated instruction N-3 instrN-2; Repeated instruction N-2 instrN-1; Repeated instruction N-1 instrN; Repeated instruction N instrN+1; The expanded results of each case corresponds to the same case num
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Section 3 DSP Operation Table 3.18 Summary of DSP Data Transfer Instructions X and Y Data Transfer Operation (MOVX.W and MOVY.W) Single Data Transfer Operation (MOVS.W and MOVS.
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Section 3 DSP Operation R8 [Ix] R4 [Ax] R5 [Ax] +2 (INC) +0 (Not update) R9 [Iy] R6 [Ay] R7 [Ay] +2 (INC) +0 (Not update) ALU Additional adder for DSP addressing AU Three address operation types: 1. Not update 2. Add-index-register (Ix/Iy) 3. Increment All operations are post-update type. To decrement an address pointer, set –2 in an index register. Figure 3.19 DSP Addressing Instructions for MOVX.W and MOVY.
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Section 3 DSP Operation R2 [As] R3 [As] R8 [Is] R4 [As] R5 [As] –2/–4 (DEC) +2/+4 (INC) +0 (No update) ALU Four address operation types: 1. Not update 2. Add-index-register (Is) 3. Increment 4. Decrement Post-update Pre-update Figure 3.20 DSP Addressing Instructions for MOVS Modulo Addressing: This LSI provides modulo addressing mode, which is common in DSPs. In modulo addressing mode, the address register is updated as explained above.
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Section 3 DSP Operation MS and ME are set to specify the start and end addresses, and then later to set the DMX or DMY bit to 1. When the X/Y data transfer instruction set in DMX/DMY is executed, the address register contents before update are compared with ME*1. If they match, modulo start address MS is stored in the address register as the updated value*2.
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Section 3 DSP Operation An example is shown below. MS=H'7000; ME=H'7004; R4=H'A5007000; DMX=1; DMY=0 (modulo addressing for address register Ax) As a result of the above settings, the R4 register changes as follows. ; R4: H'A5007000 (Initial value) MOVX.W @R4+,Dx ; R4: H'A5007000 → H'A5007002 MOVX.W @R4+,Dx ; R4: H'A5007002 → H'A5007004 MOVX.W @R4+,Dx ; R4: H'A5007004 → H'A5007000 (After reading H'A5007004, MS value is written to address register) MOVX.
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Section 3 DSP Operation Addressing Instructions in Execution Stage: Address instructions, including modulo addressing, are executed in the execution stage of the pipeline. Behavior of the DSP data addressing in the execution stage is shown below. if ( Operation is MOVX.W MOVY.W ) { ABx=Ax; ABy=Ay; /* Memory access cycle uses ABx and ABy. The addresses to be used have not been updated.
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Section 3 DSP Operation /* The value to be added to the address register depends on addressing instructions. For example, (+2 or R8[Ix] or +0) means that +2: if instruction is increment R8[Ix]: if instruction is add-index-register +0: if instruction is not-update */ function modulo ( AddrReg, Index ) { if ( AddrReg[15:1]==ME[15:1] ) AddrReg[15:1]==MS[15:1]; else AddrReg=AddrReg+Index; return AddrReg; } X and Y Data Transfer Instructions (MOVX.W and MOVY.
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Section 3 DSP Operation 31 0 31 Instruction code for X data-transfer operation R6 [Ay] R5 [Ax] R7 [Ay] 15 Input/output control for DSP data registers X0/X1, A0/A1 1 15 ABx Control for X memory 0 R4 [Ax] Instruction code for Y data-transfer operation 1 ABy Control for Y memory XAB 16-bit YAB 16-bit X_MEM X R/W X data memory 4 kbytes XDB YDB Input/output control for DSP data registers Y0/Y1, A0/A1 Y_MEM Y data memory 4 kbytes Y R/W 16-bit 16-bit X_MEM and Y_MEM: Select X and Y data me
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Section 3 DSP Operation Single-Data Transfer Instructions (MOVS.W and MOVS.L): This LSI has single load/store instructions for the DSP registers. It is similar to a load/store instruction for a system register. It transfers data between memory and DSP data registers using LAB and LDB buses. There may be access conflict between data access and instruction fetch. The single-data transfer instruction has word and longword access modes. Figure 3.23 shows a block diagram of single-data transfer.
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Section 3 DSP Operation Control LAB=MAB; if ( Ms!=NLS && W/L is word access ) { /* MOVS.
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Section 4 Clock Pulse Generator (CPG) Section 4 Clock Pulse Generator (CPG) This LSI has a clock pulse generator (CPG) that generates an internal clock (Iφ), a peripheral clock (Pφ), and a bus clock (Bφ). The CPG consists of an oscillator, PLL circuit, and divider circuit. 4.1 Features The CPG has the following features.
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Section 4 Clock Pulse Generator (CPG) Clock pulse generator Divider ×1 ×1/2 ×1/3 ×1/4 PLL circuit 1 (×1, 2, 3, 4) Internal clock (Iφ) CKIO CKIO2 Crystal oscillator XTAL Bus clock (Bφ = CKIO) PLL circuit 2 (× 2,4) EXTAL Peripheral clock (Pφ) CPG control unit MD2 MD0 Clock frequency control circuit Standby control circuit FRQCR STBCR STBCR2 STBCR3 Bus interface Internal bus [Legend] FRQCR: Frequency control register STBCR: Standby control register STBCR2: Standby control register 2 STBCR3:
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Section 4 Clock Pulse Generator (CPG) The clock pulse generator blocks function as follows: PLL Circuit 1: PLL circuit 1 doubles, triples, or quadruples, the input clock frequency from the CKIO pin. The multiplication rate is set by the frequency control register. When this is done, the phase of the rising edge of the internal clock is controlled so that it will agree with the phase of the rising edge of the CKIO pin.
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Section 4 Clock Pulse Generator (CPG) 4.2 Input/Output Pins Table 4.1 lists the CPG pins and their functions. Table 4.1 Pin Configuration and Functions of the Clock Pulse Generator Pin Name Symbol I/O Function (clock operating modes 2 and 6) Mode control pins MD0 Input Set the clock operating mode. MD2 Input Set the clock operating mode.
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Section 4 Clock Pulse Generator (CPG) Mode 2: The frequency of the signal received from the EXTAL pin or crystal resonator LSI is quadrupled by the PLL circuit 2 before it is supplied as the clock signal. This lowers the frequency required of the externally generated clock. Either a crystal resonator with a frequency in the range from 10 to 12.5 MHz or an external signal in the same frequency range input on the EXTAL pin may be used. The frequency range of CKIO is from 40 to 50 MHz.
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Section 4 Clock Pulse Generator (CPG) PLL frequency Clock multiplier FRQCR Selectable frequency ranges (MHz) Ratio of internal operating register PLL PLL clock frequencies mode setting Circuit 1 Circuit 2 (I:B:P) Input clock (CKIO pin) Internal clock Bus clock Peripheral clock 6 H'1303 ON (×4) ON (×2) 8:2:2 10 to 12.5 20 to 25 80 to 100 20 to 25 20 to 25 H'1313 ON (×4) ON (×2) 4:2:2 10 to 16.66 20 to 33.33 40 to 66.66 20 to 33.33 20 to 33.
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Section 4 Clock Pulse Generator (CPG) 4.4 Register Descriptions The CPG's control register is called the frequency control register (FRQCR). Refer the section 24, List of Registers, for the addresses of the registers and the state of each register in each processor state. 4.4.
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Section 4 Clock Pulse Generator (CPG) Bit Bit Name Initial Value R/W Description 11, 10  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 9 STC1 0 R/W Frequency multiplication ratio of PLL circuit 1 8 STC0 0 R/W 00: × 1 time 01: × 2 times 10: × 3 times 11: × 4 times 7, 6  All 0 R Reserved These bits are always read as 0. The write value should always be 0.
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Section 4 Clock Pulse Generator (CPG) 4.5 Changing the Frequency The frequency of the internal clock and peripheral clock can be changed either by changing the multiplication rate of PLL circuit 1 or by changing the division rates of divider. All of these are controlled by software through the frequency control register. The methods are described below. 4.5.1 Changing the Multiplication Rate A PLL settling time is required when the multiplication rate of PLL circuit 1 is changed.
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Section 4 Clock Pulse Generator (CPG) 4.6 Notes on Board Design Note on Using an External Crystal Resonator: Place the crystal resonator, capacitors CL1 and CL2, and feedback resistor R1 as close to the XTAL and EXTAL pins as possible. In addition, to minimize induction and thus obtain oscillation at the correct frequency, the capacitors to be attached to the resonator must be grounded to the same ground. Do not bring wiring patterns close to these components.
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Section 4 Clock Pulse Generator (CPG) • A pair of Vss and Vcc for the input/output power supply nearest the USB module H3 to H4 • A pair of Vss and Vcc for the A/D converter. W19 to U20 Notes on Using a PLL Oscillator Circuit: In the Vcc and Vss connection pattern for the PLL, signal lines from the board power supply pins must be as short as possible and pattern width must be as wide as possible to reduce inductive interference.
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Section 4 Clock Pulse Generator (CPG) Rev. 4.00 Sep.
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Section 5 Watchdog Timer (WDT) Section 5 Watchdog Timer (WDT) This LSI includes the watchdog timer (WDT), which enables reset the LSI on overflow of the counter when the value of the counter has not been updated because of a system malfunction. The WDT is a single channel timer that counts up the clock-settling period when the system leaves standby mode or the temporary periods on standby that occur when the clock frequency is changed. It can also be used as a watchdog timer or interval timer. 5.
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Section 5 Watchdog Timer (WDT) Figure 5.1 shows a block diagram of the WDT. WDT Standby cancellation Standby mode Peripheral clock Standby control Internal reset request Reset control Interrupt request Interrupt control Divider Clock selection Clock selector Overflow Clock WTCSR WTCNT Bus interface [Legend] WTCSR: Watchdog timer control/status register WTCNT: Watchdog timer counter Figure 5.1 Block Diagram of the WDT 5.2 Register Descriptions The WDT has the following two registers.
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Section 5 Watchdog Timer (WDT) 5.2.2 Watchdog Timer Control/Status Register (WTCSR) The watchdog timer control/status register (WTCSR) is an 8-bit readable/writable register composed of bits to select the clock used for the count, overflow flags, and timer enable bit. The WTCSR register holds its value in an internal reset due to WDT overflow. The WTCSR register is initialized to H'00 only by a power-on reset caused by the RESETP pin.
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Section 5 Watchdog Timer (WDT) Bit Bit Name Initial Value R/W Description 4 WOVF 0 R/W Watchdog Timer Overflow Indicates that the WTCNT has overflowed in watchdog timer mode. This bit is not set in interval timer mode. 0: No overflow 1: WTCNT has overflowed in watchdog timer mode 3 IOVF 0 R/W Interval Timer Overflow Indicates that the WTCNT has overflowed in interval timer mode. This bit is not set in watchdog timer mode.
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Section 5 Watchdog Timer (WDT) 5.2.3 Notes on Register Access The watchdog timer counter (WTCNT) and watchdog timer control/status register (WTCSR) are more difficult to write to than other registers. The procedures for reading or writing to these registers are given below. Writing to WTCNT and WTCSR: These registers must be written by a word transfer instruction. They cannot be written by a byte or longword transfer instruction.
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Section 5 Watchdog Timer (WDT) 5. When the WDT count overflows, the CPG starts supplying the clock and the processor resumes operation. The WOVF flag in WTCSR is not set when this happens. 6. Since the WDT continues counting from H'00, set the STBY bit in the STBCR register to 0 in the interrupt processing program and this will stop the WDT. When the STBY bit remains 1, the LSI again enters the standby mode when the WDT has counted up to H'80. This standby mode can be canceled by power-on resets. 5.3.
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Section 5 Watchdog Timer (WDT) 5.3.4 Using Interval Timer Mode When operating in interval timer mode, interval timer interrupts are generated at every overflow of the counter. This enables interrupts to be generated at set periods. 1. Clear the WT/IT bit in the WTCSR to 0, set the type of count clock in the CKS2 to CKS0 bits, and set the initial value of the counter in the WTCNT. 2. Set the TME bit in WTCSR to 1 to start the count in interval timer mode. 3.
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Section 5 Watchdog Timer (WDT) Rev. 4.00 Sep.
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Section 6 Power-Down Modes Section 6 Power-Down Modes In the low power-consumption modes, operation of some of the internal peripheral modules and of the CPU stops. This leads to reduced power consumption. These modes are canceled by a reset or interrupt. 6.1 Features 6.1.1 Power-Down Modes This LSI has the following power-down modes and function: 1. Sleep mode 2. Standby mode 3. Module standby function Table 6.
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Section 6 Power-Down Modes Table 6.1 States of Power-Down Modes State* On-Chip CPU Peripheral External Canceling Mode Transition Conditions CPG CPU Register Memory Modules Memory Procedure Sleep mode Execute SLEEP Runs Halts Held 1. Interrupt 2. Reset Standby mode Halts The UBC stops. Refreshed instruction with STBY bit (The contents Other modules automati-cally cleared to 0 in STBCR are retained.) continue to run.
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Section 6 Power-Down Modes • Manual-on reset 1. A low signal is input to the RESETM pin. 2. The WDT counter overflows if WDT starts counting while the WT/IT and RSTS bits of the WTCSR are set to 1. 6.1.3 Input/Output Pins Table 6.2 lists the pins used for the power-down modes. Table 6.2 Pin Configuration Pin Name Symbol I/O Description Processing state 1 STATUS1 Output Indicates the operational state of this LSI.
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Section 6 Power-Down Modes 6.2 Register Descriptions The following registers are used in the low power-consumption modes. For the addresses and access sizes of these registers, see section 24, List of Registers. • • • • Standby control register (STBCR) Standby control register 2 (STBCR2) Standby control register 3 (STBCR3) Standby control register 4 (STBCR4) 6.2.
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Section 6 Power-Down Modes 6.2.2 Standby Control Register 2 (STBCR2) The standby control register 2 (STBCR2) is a readable/writable 8-bit register that controls the operation of modules in the power-down mode. STBCR2 is initialized (to H'00) by a power-on reset but retains its previous value after a manual reset or a period in the standby mode. Only byte access is valid.
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Section 6 Power-Down Modes Bit Bit Name Initial Value R/W Description 2 MSTP5 0 R/W Module Stop 5 When the MSTP5 bit is set to 1, the supply of the clock to the cache memory is halted. 0: The cache memory runs. 1: Clock supply to the cache memory halted. 1 MSTP4 0 R/W Module Stop 4 When the MSTP4 bit is set to 1, the supply of the clock to the U memory is halted. 0: The U memory runs. 1: Clock supply to the U memory halted.
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Section 6 Power-Down Modes Bit Bit Name Initial Value R/W Description 6  0 R/W Reserved This bit is always read as 0. The write value should always be 0. 5 MSTP35 0 R/W Module Stop 35 When the MSTP35 bit is set to 1, supply of the clock to the CMT0 stops. 0: The CMT0 runs. 1: Supply of the clock to the GMT0 stops. 4  0 R Reserved This bit is always read as 0. The write value should always be 0.
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Section 6 Power-Down Modes 6.2.4 Standby Control Register 4 (STBCR4) STBCR4 is a readable/writable 8-bit register used to select whether or not individual modules operate in power-down mode. STBCR4 is initialized (to H'00) by a power-on reset, but retains its previous value after a manual reset or a period in the standby mode. Only byte access is valid. Bit Bit Name Initial Value R/W Description 7  0 R Reserved This bit is always read as 0. The write value should always be 0.
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Section 6 Power-Down Modes 6.3 Operation 6.3.1 Sleep Mode 1. Transition to Sleep Mode Executing the SLEEP instruction when the STBY bit in STBCR is 0 causes a transition from the program execution state to sleep mode. Although the CPU halts immediately after executing the SLEEP instruction, the contents of its internal registers remain unchanged. The on-chip modules continue to run in sleep mode, but the on-chip memory is not accessible.
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Section 6 Power-Down Modes 6.3.2 Standby Mode 1. Transition to Standby Mode The LSI switches from a program execution state to a standby mode by executing the SLEEP instruction when the STBY bit is 1 in STBCR register. In standby mode, not only the CPU but also the clock and on-chip peripheral modules halt. The clock outputs from the CKIO and CKIO2 pins also halt. The contents of the CPU and cache registers remain unchanged. Some registers of on-chip peripheral modules are, however, initialized. Table 6.
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Section 6 Power-Down Modes 2. Canceling Standby Mode Standby mode is canceled by interrupts (NMI, IRQ) or a reset. • Canceling with an Interrupt The on-chip WDT can be used for hot starts. When an interrupt request is detected at the rising or falling edge of NMI or IRQ, the clock will be supplied to the entire chip and standby mode canceled after the time set in the WDT's timer control/status register has elapsed. The STATUS1 and STATUS0 pins go low.
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Section 6 Power-Down Modes 6.3.3 Module Standby Function 1. Transition to Module Standby Function Setting the standby control register MSTP bits to 1 halts the supply of clocks to the corresponding on-chip peripheral modules (however, the initial state of the USB stops). This function can be used to reduce the power consumption in normal mode and sleep mode. Disable a module before placing it in the module standby mode.
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Section 6 Power-Down Modes 1. Manual Reset CKIO RESETM normal *3 STATUS reset *2 normal*3 0 Bcyc to *1,*4 0 to 30 Bcyc*4 Notes 1. In manual reset, STATUS = HH (reset) after the current bus cycle is completed and then internal reset is initiated. 2. reset: HH (STATUS1 = High, STATUS0 = High) 3. normal: LL (STATUS1 = Low, STATUS0 = Low) 4. Bcyc: Bus clock cycle Figure 6.2 STATUS Output at Manual Reset 2.
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Section 6 Power-Down Modes B Standby mode is canceled by a manual reset Oscillation stops Reset CKIO RESETM *1 normal *4 STATUS standby *3 reset *2 Notes: 1. If a standby mode is canceled by a manual reset, the WDT stops counting. RESETM must be kept low for the PLL oscillation stabilization time. 2. reset : HH (STATUS1 = High, STATUS0 = High) 3. standby : LH (STATUS1 = Low, STATUS0 = High) 4. normal : LL (STATUS1 = Low, STATUS0 = Low) 5. Bcyc : Bus clock cycle normal*4 0 to 20 Bcyc *5 Figure 6.
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Section 6 Power-Down Modes B Sleep standby mode is canceled by a manual reset Reset CKIO RESETM *1 STATUS Notes: 1. 2. 3. 4. 5. normal *4 sleep *3 0 to 80 Bcyc *5 RESETM must be kept low until STATUS = reset. reset:HH (STATUS1 = High, STATUS0 = High) sleep:HL(STSTUS1= High, STATUS0= Low) normal:LL (STATUS1 = Low, STATUS0 = Low) Bcyc:Bus clock cycle reset *2 normal *4 0 to 30 Bcyc *5 Figure 6.6 STATUS Output When Sleep Mode is Canceled by a Manual Reset Rev. 4.00 Sep.
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Section 6 Power-Down Modes Rev. 4.00 Sep.
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Section 7 Cache Section 7 Cache 7.1 Features The cache specifications are listed in table 7.1. Table 7.
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Section 7 Cache 7.1.1 Cache Structure The cache mixes data and instructions and uses a 4-way set associative system. It is composed of four ways (banks), each of which is divided into an address section and a data section. Each of the address and data sections is divided into 256 entries. The data section of the entry is called a line. Each line consists of 16 bytes (4 bytes × 4). The data capacity per way is 4 kbytes (16 bytes × 256 entries), with a total of 16 kbytes in the cache as a whole (4 ways).
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Section 7 Cache Data Array: Holds a 16-byte instruction or data. Entries are registered in the cache in line units (16 bytes). The data array is not initialized by a power-on or manual reset, standby mode, module standby mode, and sleep mode. LRU: With the 4-way set associative system, up to four instructions or data with the same entry address (address bits 11 to 4) can be registered in the cache. When an entry is registered, LRU shows which of the four ways it is recorded in.
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Section 7 Cache 7.2 Register Descriptions The cache has the following registers. • Cache control register 1 (CCR1) • Cache control register 2 (CCR2) 7.2.1 Cache Control Register 1 (CCR1) The cache is enabled or disabled using the CE bit in CCR1. CCR1 also has the CF bit (which invalidates all cache entries), and the WT and WB bits (which select either write-through mode or write-back mode). Programs that change the contents of CCR1 should be placed in an address space that is not cached.
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Section 7 Cache Bit Bit Name Initial Value R/W Description 0 CE 0 R/W Cache Enable Indicates whether the cache function is used. 0: Cache not used 1: Cache used 7.2.2 Cache Control Register 2 (CCR2) CCR2 is used to enable or disable the cache locking function and is valid in cache locking mode only. In cache locking mode, the DSP bit (bit 12) in the status register (SR) of the CPU is set to 1. Alternatively, the lock enable bit (bit 16) in CCR2 is set to 1.
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Section 7 Cache Bit Bit Name Initial value R/W Description 31 to 17  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 16 LE 0 R/W Lock Enable This bit enables or disables the cache locking function. 0: Cache locking mode is entered when SR.DSP=1 1: Cache locking mode is entered regardless of the value of SR.DSP 15 to 10  All 0 R Reserved These bits are always read as 0. The write value should always be 0.
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Section 7 Cache Table 7.4 Way to be Replaced when a Cache Miss Occurs in PREF Instruction Cache Locking Mode Bit W3LOAD W3LOCK W2LOAD W2LOCK Way to be Replaced 0 * * * * Decided by LRU (table 7.3) 1 * 0 * 0 Decided by LRU (table 7.3) 1 * 0 0 1 Decided by LRU (table 7.6) 1 0 1 * 0 Decided by LRU (table 7.7) 1 0 1 0 1 Decided by LRU (table 7.
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Section 7 Cache Table 7.7 LRU and Way Replacement (when W2LOCK=0 and W3LOCK=1) LRU (Bits 5 to 0) Way to be Replaced 000000, 000001, 000011, 001011, 100000, 100001, 101001, 101011 2 000100, 000110, 000111, 001111, 010100, 010110, 011110, 011111 1 110000, 110100, 111000, 111001, 111011, 111100, 111110, 111111 0 Table 7.
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Section 7 Cache Address 31 12 11 4 3 210 Entry selection Longword (LW) selection Address array (ways 0 to 3) 0 MMU V U Tag address Data array (ways 0 to 3) LW0 LW1 LW2 LW3 1 255 Physical address CMP0 CMP1 CMP2 CMP3 [Legend] CMP0: Comparison circuit CMP1: Comparison circuit CMP2: Comparison circuit CMP3: Comparison circuit Hit signal (1) for way 0 for way 1 for way 2 for way 3 Figure 7.2 Cache Search Scheme Rev. 4.00 Sep.
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Section 7 Cache 7.3.2 Read Access Read Hit: In a read access, instructions and data are transferred from the cache to the CPU. LRU is updated so that the hit way is the latest. Read Miss: An external bus cycle starts and the entry is updated. The way replaced follows table 7.5. Entries are updated in 16-byte units.
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Section 7 Cache 7.3.5 Write-Back Buffer When the U bit of the entry to be replaced in the write-back mode is 1, it must be written back to the external memory. To increase performance, the entry to be replaced is first transferred to the write-back buffer and fetching of new entries to the cache takes priority over writing back to the external memory. After the cache completes to fetch the new entry, the write-back buffer writes the entry back to external memory.
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Section 7 Cache 7.4 Memory-Mapped Cache To allow software management of the cache, cache contents can be read and written by means of MOV instructions. The cache is mapped onto the P4 area. The address array is mapped onto addresses H'F0000000 to H'F0FFFFFF, and the data array onto addresses H'F1000000 to H'F1FFFFFF. Only longword can be used as the access size for the address array and data array, and instruction fetches cannot be performed. 7.4.
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Section 7 Cache Data Array Read: The data specified by L (bits 3 and 2) in the address is read from the entry address specified by the address and the entry corresponding to the way. Data Array Write: The longword data specified by the data is written to the position specified by L (bits 3 and 2) in the address from the entry address specified by the address and the entry corresponding to the way. 1.
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Section 7 Cache 7.4.3 Usage Examples Invalidating Specific Entries Specific cache entries can be invalidated by writing 0 to the entry's V bit in the memory mapping cache access. When the A bit is 1, the address tag specified by the write data is compared to the address tag within the cache selected by the entry address, and data is written to the bits V and U specified by the write data when a match is found. If no match is found, there is no operation.
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Section 8 X/Y Memory Section 8 X/Y Memory This LSI has on-chip X-RAM and Y-RAM. It can be used by CPU, DSP and DMAC to store instructions or data. 8.1 Features The X/Y Memory features are listed in table 8.1. Table 8.
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Section 8 X/Y Memory 8.2 X/Y Memory Access from CPU The X/Y memory can be accessed by the CPU from spaces P0 and P2. Access from space P0 uses the I bus, and access from space P2 use the L bus. To use the L bus, one cycle access is performed unless page conflict occurs. Using the I bus takes more than one cycle access. Figure 8.1 shows X/Y memory address mapping.
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Section 8 X/Y Memory 8.4 X/Y Memory Access from DMAC The X/Y memory can be accessed by the DMAC via the I bus. Use the addresses between H'05007000 and H'05008FFF or H'05017000 and H'05018FFF. 8.5 Usage Note When accessing the X/Y memory from the CPU and DSP, if the cache is on, access must be performed from space P2 (non-cacheable space). Operation during access from space P0 cannot be guaranteed. When the cache is off, spaces P0 and P2 can both be used.
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Section 8 X/Y Memory Rev. 4.00 Sep.
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Section 9 Exception Handling Section 9 Exception Handling Exception handling is separate from normal program processing, and is performed by a routine separate from the normal program. For example, if an attempt is made to execute an undefined instruction code or an instruction protected by the CPU processing mode, a control function may be required to return to the source program by executing the appropriate operation or to report an abnormality and carry out end processing.
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Section 9 Exception Handling 9.1 Register Descriptions There are three registers for exception handling. A register with an undefined initial value should be initialized by the software. • TRAPA exception register (TRA) • Exception event register (EXPEVT) • Interrupt event register 2 (INTEVT2) Figure 9.1 shows the bit configuration of each register. 31 10 9 0 21 0 TRA 31 12 11 0 TRA 0 0 EXPEVT 31 12 11 0 EXPEVT 0 INTEVT2 INTEVT2 Figure 9.1 Register Bit Configuration 9.1.
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Section 9 Exception Handling 9.1.2 Exception Event Register (EXPEVT) EXPEVT is assigned to address H'FFFFFFD4 and consists of a 12-bit exception code. Exception codes to be specified in EXPEVT are those for resets and general exceptions. These exception codes are automatically specified the hardware when an exception occurs. Only bits 11 to 0 of EXPEVT can be re-written using the software. Bit Bit Name Initial Value R/W Description 31 to 12  All 0 R Reserved These bits are always read as 0.
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Section 9 Exception Handling 9.2 Exception Handling Function 9.2.1 Exception Handling Flow In exception handling, the contents of the program counter (PC) and status register (SR) are saved in the saved program counter (SPC) and saved status register (SSR), respectively, and execution of the exception handler is invoked from a vector address.
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Section 9 Exception Handling The above operations from 1 to 3 are executed in sequence. During these operations, no other exceptions may be accepted. By changing the SPT and SSR before executing the RTE instruction, a status different from that in effect before the exception handling can also be specified. Note: For details on the CPU processing mode in which RTE delay slot instructions are executed, please refer to section 9.6, Usage Notes. 9.2.
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Section 9 Exception Handling other than the CPU are not initialized, the contents of EXPEVT, SPC, and SSR are undefined, and this status is not detected by an external device. To enable acceptance of multiple exceptions, the contents of SPC and SSR must be saved while the BL bit is set to 1 after an exception has been accepted, and then the BL bit must be cleared to 0. Before restoring the SPC and SSR, the BL bit must be set to 1. 9.2.
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Section 9 Exception Handling If multiple general exceptions occur simultaneously in the same instruction, the priority is determined as follows. 1. 2. 3. 4. 5. 6. 7. 8.
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Section 9 Exception Handling Table 9.
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Section 9 Exception Handling 9.3 Individual Exception Operations This section describes the conditions for specific exception handling, and the processor operations. 9.3.1 Resets Power-On Reset: • Conditions Power-on reset is request • Operations Set EXPEVT to H'000, initialize the CPU and on-chip peripheral modules, and branch to the reset vector H'A0000000. For details, refer to the register descriptions in the relevant sections.
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Section 9 Exception Handling Table 9.2 Type of Reset Internal state Type Condition to reset CPU On-chip peripheral module Power-on reset RESETP = Low level Initialization Manual reset RESETM = Low level Refer to the register configurations in the relevant sections. H-UDI reset H-UDI reset command entry 9.3.
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Section 9 Exception Handling Illegal general instruction exception: • Conditions  When undefined code not in a delay slot is decoded Delayed branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S Note: For details on undefined code, refer to SH-3/SH-3E/SH-3DSP Software Manual. When an undefined code other than H'FC00 to H'FFFF is decoded, operation cannot be guaranteed.
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Section 9 Exception Handling Unconditional trap: • Conditions TRAPA instruction executed • Types Instruction synchronous, processing-completion type • Save address An address of an instruction following TRAPA • Exception code H'160 • Remarks The exception is a processing-completion type, so PC of the instruction after the TRAPA instruction is saved to SPC. The 8-bit immediate value in the TRAPA instruction is quadrupled and set in TRA9 to TRA0.
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Section 9 Exception Handling DMA address error: • Conditions  Word data accessed from addresses other than word boundaries (4n + 1, 4n + 3)  Longword accessed from addresses other than longword boundaries (4n + 1, 4n + 2, 4n + 3) • Types Instruction synchronous, processing-completion type • Save address An address of the instruction following the instruction where a break occurs (a delayed branch instruction destination address if an instruction is assigned to a delay slot) • Exception code H'5C0 • Remar
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Section 9 Exception Handling 9.4 Exception Processing While DSP Extension Function is Valid When the DSP extension function is valid (the DSP bit of SR is set to 1), some exception processing acceptance conditions or exception processing may be changed. 9.4.1 Illegal Instruction Exception and Slot Illegal Instruction Exception In the DSP mode, a DSP extension instruction can be executed.
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Section 9 Exception Handling • Example 1: Repeat loop consisting of four instructions LDRS RptStart ; [A] LDRS RptDtct + 4 ; [A] SETRCT #4 ; [A] instr0 ; [A] RptStart: instr1 ; [A] RptDtct: RptEnd: ……… ; [A] ……… ; [A] RptDtct ; [B] A repeat detection instruction is an instruction three instructions before a repeat end instruction RptDtct1 ; [C1] RptDtct2 ; [C2] RptDtct3 ; [C2][Repeat end instruction] InstrNext ; [A] • Example 2: Repeat loop consisting of three instructions LDRS Rpt
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Section 9 Exception Handling • Example 3: Repeat loop consisting of two instructions LDRS RptDtct + 6 ; [A] LDRS RptDtct + 4 ; [A] SETRCT #4 RptDtct: RptDtct RptStart: RptEnd: RptDtct1 ; [A] ; [B] A repeat detection instruction is an instruction prior to a repeat start instruction ; [C1][Repeat start instruction] RptDtct3 ; [C2][Repeat end instruction] InstrNext ; [A] • Example 4: Repeat loop consisting of one instruction LDRS RptDtct + 8 ; [A] LDRS RptDtct + 4 ; [A] SETRCT #4 ; [A] R
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Section 9 Exception Handling Table 9.4 SPC Value When a Re-Execution Type Exception Occurs in Repeat Control Instruction Where an Exception Occurs Number of Instructions in a Repeat Loop 1 2 3 4 or Greater RptDtct RptDtct RptDtct RptDtct RptDtct RptDtct1 RptDtct1 RptDtct1 RptDtct1 RptDtct1 RptDtct2  RptDtct1 RptDtct1 RS-4 RptDtct3   RptDtct1 RS-2 Note: The following labels are used here.
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Section 9 Exception Handling An Exception Retained in Repeat Control Period: In the repeat control period, an interrupt or some exception will be retained to prevent an exception acceptance at an instruction where returning from the exception cannot be performed correctly. For details, refer to repeat loop program example 1 to 4. In the examples, exceptions generated at instructions indicated as [B], [C], [C1], or [C2], the following processing is executed.
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Section 9 Exception Handling CPU Address Error in Repeat Control Period: If a CPU address error occurs in the repeat control period, the exception is accepted but an exception code (H'070) indicating the repeat loop period is specified in the EXPEVT. If a CPU address error occurs in instructions following a repeat detection instruction to repeat end instruction, an exception code for instruction access or data access is specified in the EXPEVT.
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Section 9 Exception Handling 9.5 Note on Initializing this LSI This LSI needs to be initialized by a software reset before the power is turned on. Execute the following program immediately after a power-on reset. Note that the following program overwrites contents of CPU general registers. Save contents of registers which should not be overwritten before executing the following program. Rev. 4.00 Sep.
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Section 9 Exception Handling ;----------------------------------------------------------; Intialization of sh7641 for power-on reset ;----------------------------------------------------------; ATTENTION: ; 1. Please execute below instructions on power-on reset. ; 2. This routine would overwrite the general registers on the CPU. ; 3. Do not modify these codes. ;----------------------------------------------------------MOV.L #H'A5007000,R4; MOV.L #H'A5008000,R5; MOV.L #H'A5017000,R6; MOV.
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Section 9 Exception Handling 9.6 1. 2. 3. Usage Notes An instruction assigned at a delay slot of the RTE instruction is executed after the contents of the SSR is restored into the SR. An acceptance of an exception related to instruction access is determined according to the SR before restore. An acceptance of other exceptions is determined by the SR after restore, processing mode, and BL bit value.
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Section 10 Interrupt Controller (INTC) Section 10 Interrupt Controller (INTC) The interrupt controller (INTC) ascertains the priority of interrupt sources and controls interrupt requests to the CPU. The INTC registers set the order of priority of each interrupt, allowing the user to process interrupt requests according to the user-set priority. 10.
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Section 10 Interrupt Controller (INTC) Figure 10.1 shows a block diagram of the INTC.
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Section 10 Interrupt Controller (INTC) 10.2 Input/Output Pins Table 10.1 shows the INTC pin configuration. Table 10.1 Pin Configuration Name Abbreviation I/O Nonmaskable interrupt input pin NMI Interrupt input pins 10.3 IRQ7 to IRQ0 Description Input Input of interrupt request signal, not maskable by the interrupt mask bits in SR Input Input of interrupt request signals, maskable by the interrupt mask bits in SR Register Descriptions The INTC has the following registers.
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Section 10 Interrupt Controller (INTC) • • • • • • • • • • • • • • • • Interrupt mask register 6 (IMR6) Interrupt mask register 7 (IMR7) Interrupt mask register 8 (IMR8) Interrupt mask register 9 (IMR9) Interrupt mask register 10 (IMR10) Interrupt mask clear register 0 (IMCR0) Interrupt mask clear register 1 (IMCR1) Interrupt mask clear register 2 (IMCR2) Interrupt mask clear register 3 (IMCR3) Interrupt mask clear register 4 (IMCR4) Interrupt mask clear register 5 (IMCR5) Interrupt mask clear register 6
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Section 10 Interrupt Controller (INTC) 10.3.1 Interrupt Priority Registers B to J (IPRB to IPRJ) IPRB to IPRJ are 16-bit readable/writable registers in which priority levels from 0 to 15 are set for on-chip peripheral module and IRQ interrupts. These registers are initialized to H'0000 by a power-on reset or manual reset, but are not initialized in standby mode.
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Section 10 Interrupt Controller (INTC) Table 10.
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Section 10 Interrupt Controller (INTC) 10.3.2 Interrupt Control Register 0 (ICR0) ICR0 is a register that sets the input signal detection mode of external interrupt input pin NMI, and indicates the input signal level at the NMI pin. This register is initialized to H'0000 or H'8000 by a power-on reset or manual reset, but is not initialized in standby mode. Bit Bit Name Initial Value R/W Description 15 NMIL 0/1* R NMI Input Level Sets the level of the signal input at the NMI pin.
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Section 10 Interrupt Controller (INTC) 10.3.3 Interrupt Control Register 1 (ICR1) ICR1 is a 16-bit register that specifies the detection mode for external interrupt input pins IRQ5 to IRQ0 individually: rising edge, falling edge, high level, or low level. This register is initialized to H'4000 by a power-on reset or manual reset, but is not initialized in standby mode. Bit Bit Name Initial Value R/W Description 15  0 R Reserved This bit is always read as 0. The write value should always be 0.
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Section 10 Interrupt Controller (INTC) 10.3.4 Interrupt Control Register 3 (ICR3) ICR3 is a 16-bit register that specifies the detection mode for external interrupt input pins IRQ7 and IRQ6 individually: rising edge, falling edge, high level, or low level. This register is initialized to H'0000 by a power-on reset or manual reset, but is not initialized in standby mode. Bit Bit Name Initial Value R/W Description 15 to 4  All 0 R Reserved These bits are always read as 0.
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Section 10 Interrupt Controller (INTC) 10.3.5 Interrupt Request Register 0 (IRR0) IRR0 is an 8-bit register that indicates interrupt requests from external input pins IRQ7 to IRQ0. This register is initialized to H'00 by a power-on reset or manual reset, but is not initialized in standby mode. Bit Bit Name Initial Value R/W Description 7 IRQ7R 0 R/W IRQn Interrupt Request 6 IRQ6R 0 R/W 5 IRQ5R 0 R/W 4 IRQ4R 0 R/W Indicates whether there is interrupt request input to the IRQn pin.
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Section 10 Interrupt Controller (INTC) 10.3.6 Interrupt Mask Registers 0 to 10 (IMR0 to IMR10) IMR0 to IMR10 are 8-bit readable/writable registers that mask the IRQ and on-chip peripheral module interrupts. When an interrupt source is masked, interrupt requests may be mistakenly detected, depending on the operation state of the IRQ pins and on-chip peripheral modules. To prevent this, set IMR0 to IMR9 while no interrupts are set to be generated, and then read the new settings from these registers.
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Section 10 Interrupt Controller (INTC) Table 10.
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Section 10 Interrupt Controller (INTC) 10.3.7 Interrupt Mask Clear Registers 0 to 10 (IMCR0 to IMCR10) IMCR0 to IMCR10 are 8-bit writable registers that clear the mask settings for the IRQ and onchip peripheral module interrupts. Table 10.4 shows the relationship between IMCR and each interrupt source. Bit Bit Name Initial Value R/W Description 7 IMC7  W Interrupt Mask Clear 6 IMC6  W 5 IMC5  W Table 10.
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Section 10 Interrupt Controller (INTC) Table 10.
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Section 10 Interrupt Controller (INTC) 10.4 Interrupt Sources There are four types of interrupt sources: NMI, H-UDI, IRQ, and on-chip peripheral modules. Each interrupt has a priority level (0 to 16), with 1 the lowest and 16 the highest. Priority level 0 masks an interrupt, so the interrupt request is ignored. 10.4.1 NMI Interrupt The NMI interrupt has the highest priority level of 16. When the BL bit in the status register (SR) is 0, NMI interrupts are accepted. NMI interrupts are edge-detected.
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Section 10 Interrupt Controller (INTC) Edge input interrupt detection requires input of a pulse width of more than two cycles on a P clock basis. When using level-sensing for IRQ interrupts, the pin levels must be retained until the CPU samples the pins. Therefore, the interrupt source must be cleared by the interrupt handler. The interrupt mask bits (I3 to I0) in the status register (SR) are not affected by IRQ interrupt handling. 10.4.
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Section 10 Interrupt Controller (INTC) 10.4.5 Interrupt Exception Handling and Priority There are three types of interrupt sources: NMI, IRQ, and on-chip peripheral modules. The priority of each interrupt source is set within level 0 to level 16; level 16 is the highest and level 1 is the lowest. When the priority is set to level 0, that interrupt is masked and the interrupt request is ignored. Table 10.5 lists the codes for the interrupt event register (INTEVT2) and the order of interrupt priority.
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Section 10 Interrupt Controller (INTC) Table 10.
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Section 10 Interrupt Controller (INTC) Interrupt Source Exception Interrupt Priory Code (Initial Value) IPR (Bit Number) Priority within IPR Default Setting Unit Priority MTU0 TGI0A H'A80 IPRG (15 to 12) High TGI0B H'AA0 MTU1 MTU2 MTU3 MTU4 TGI0C H'AC0 TGI0D H'AE0 TCI0V H'B00 TGI1A H'C00 TGI1B H'C20 TCI1V H'C40 TCI1U H'C60 TGI2A H'C80 TGI2B H'CA0 TCI2V H'CC0 TCI2U H'CE0 TGI3A H'D00 TGI3B H'D20 TGI3C H'D40 TGI3D H'D60 TCI3V H'D80 TGI4A H'E00 TGI4B H'E20 TGI
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Section 10 Interrupt Controller (INTC) 10.5 INTC Operation 10.5.1 Interrupt Sequence The sequence of interrupt operations is described below. Figure 10.2 is a flowchart of the operations. 1. The interrupt request sources send interrupt request signals to the interrupt controller. 2. The interrupt controller selects the highest-priority interrupt from the interrupt requests sent, following the priority levels set in interrupt priority registers B to J (IPRB to IPRJ).
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Section 10 Interrupt Controller (INTC) Program execution state Interrupt generated? No Yes No SR.
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Section 10 Interrupt Controller (INTC) 10.5.2 Multiple Interrupts When handling multiple interrupts, an interrupt handler should include the following procedures: 1. Branch to a specific interrupt handler corresponding to a code set in INTEVT2. The code in INTEVT2 can be used as an offset for branching to the specific handler. 2. Clear the interrupt source in each specific handler. 3. Save SSR and SPC to memory. 4.
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Section 11 User Break Controller (UBC) Section 11 User Break Controller (UBC) The user break controller (UBC) provides functions that simplify program debugging. These functions make it easy to design an effective self-monitoring debugger, enabling the chip to debug programs without using an in-circuit emulator. Break conditions that can be set in the UBC are instruction fetch or data read/write access, data size, data contents, address value, and stop timing in the case of instruction fetch. 11.
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Section 11 User Break Controller (UBC) Figure 11.1 shows a block diagram of the UBC.
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Section 11 User Break Controller (UBC) 11.2 Register Descriptions The user break controller has the following registers. For details on register addresses and access sizes, refer to section 24, List of Registers.
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Section 11 User Break Controller (UBC) 11.2.2 Break Address Mask Register A (BAMRA) BAMRA is a 32-bit readable/writable register. BAMRA specifies bits masked in the break address specified by BARA. Bit Bit Name 31 to 0 BAMA31 to BAMA0 Initial Value R/W Description All 0 R/W Break Address Mask A Specify bits masked in the channel A break address bits specified by BARA (BAA31 to BAA0).
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Section 11 User Break Controller (UBC) Bit Bit Name Initial Value R/W Description 5 IDA1 0 R/W Instruction Fetch/Data Access Select A 4 IDA0 0 R/W Select the instruction fetch cycle or data access cycle as the bus cycle of the channel A break condition.
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Section 11 User Break Controller (UBC) 11.2.4 Break Address Register B (BARB) BARB is a 32-bit readable/writable register. BARB specifies the address used as a break condition in channel B. Control bits CDB1, CDB0, XYE, and XYS in BBRB select one of the four address buses for break condition B. Bit Bit Name 31 to 0 BAB31 to BAB0 Initial Value R/W Description All 0 R/W Break Address B Store an address which specifies a break condition in channel B.
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Section 11 User Break Controller (UBC) 11.2.5 Break Address Mask Register B (BAMRB) BAMRB is a 32-bit readable/writable register. BAMRB specifies bits masked in the break address specified by BARB. Bit Bit Name 31 to 0 BAMB31 to BAMB0 Initial Value R/W Description All 0 R/W Break Address Mask B Specify bits masked in the break address of channel B specified by BARB (BAB31 to BAB0).
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Section 11 User Break Controller (UBC) Table 11.2 Specifying Break Data Register Bus Selection in BBRB BDB31 to BDB16 BDB15 to BDB0 L bus LDB31 or LDB0 I bus IDB31 to IDB0 X bus XDB15 to XDB0 Don't care Y bus Don't care YDB15 to YDB0 Notes: 1. Specify an operand size when including the value of the data bus in the break condition. 2. When the byte size is selected as a break condition, the same byte data must be set in bits 15 to 8 and 7 to 0 in BDRB as the break data. 3.
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Section 11 User Break Controller (UBC) 11.2.8 Break Bus Cycle Register B (BBRB) Break bus cycle register B (BBRB) is a 16-bit readable/writable register, which specifies (1) X bus or Y bus, (2) L bus cycle or I bus cycle, (3) instruction fetch or data access, (4) read or write, and (5) operand size in the break conditions of channel B. Bit Bit Name Initial Value R/W Description 15 to 10  All 0 R Reserved These bits are always read as 0. The write value should always be 0.
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Section 11 User Break Controller (UBC) Bit Bit Name Initial Value R/W Description 5 IDB1 0 R/W Instruction Fetch/Data Access Select B 4 IDB0 0 R/W Select the instruction fetch cycle or data access cycle as the bus cycle of the channel B break condition.
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Section 11 User Break Controller (UBC) 11.2.9 Break Control Register (BRCR) BRCR sets the following conditions: 1. Channels A and B are used in two independent channel conditions or under the sequential condition. 2. A break is set before or after instruction execution. 3. Specify whether to include the number of execution times on channel B in comparison conditions. 4. Determine whether to include data bus on channel B in comparison conditions. 5. Enable PC trace.
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Section 11 User Break Controller (UBC) Bit Bit Name Initial Value R/W Description 13 SCMFDA 0 R/W I Bus Cycle Condition Match Flag A When the I bus cycle condition in the break conditions set for channel A is satisfied, this flag is set to 1 (not cleared to 0). In order to clear this flag, write 0 into this bit.
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Section 11 User Break Controller (UBC) Bit Bit Name Initial Value R/W Description 6 PCBB 0 R/W PC Break Select B Selects the break timing of the instruction fetch cycle for channel B as before or after instruction execution. 0: PC break of channel B is set before instruction execution 1: PC break of channel B is set after instruction execution 5, 4  All 0 R Reserved These bits are always read as 0. The write value should always be 0.
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Section 11 User Break Controller (UBC) 11.2.10 Execution Times Break Register (BETR) BETR is a 16-bit readable/writable register. When the execution-times break condition of channel B is enabled, this register specifies the number of execution times to make the break. The maximum number is 212 – 1 times. When a break condition is satisfied, it decreases BETR. A break is issued when the break condition is satisfied after BETR becomes H'0001.
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Section 11 User Break Controller (UBC) 11.2.12 Branch Destination Register (BRDR) BRDR is a 32-bit read-only register. BRDR stores bits 27 to 0 in the address of the branch destination instruction. BRDR has the flag bit that is set to 1 when a branch occurs. This flag bit is cleared to 0 when BRDR is read, the setting to enable PC trace is made, or BRDR is initialized by a power-on reset. Other bits are not initialized by a power-on reset.
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Section 11 User Break Controller (UBC) 11.3 Operation 11.3.1 Flow of the User Break Operation The flow from setting of break conditions to user break exception processing is described below: 1. The break addresses is set in the break address registers (BARA or BARB). The masked addresses are set in the break address mask registers (BAMRA or BAMRB). The break data is set in the break data register (BDRB). The masked data is set in the break data mask register (BDMRB).
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Section 11 User Break Controller (UBC)  If a logical address issued on the L bus by the CPU is an address to be cached and a cache miss occurs, its bus cycle is issued as a cache fill cycle on the I bus. In this case, it is issued in longwords and its address is rounded to match longword boundaries. However note that cache fill is not performed for a write miss in write through mode. In this case, the bus cycle is issued with the data size specified on the L bus and its address is not rounded.
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Section 11 User Break Controller (UBC) 4. When an instruction fetch cycle is set for channel B, the break data register B (BDRB) is ignored. Therefore, break data cannot be set for the break of the instruction fetch cycle. 5. If the I bus is set for a break of an instruction fetch cycle, the condition is determined for the instruction fetch cycles on the I bus. For details, see 5 in section 11.3.1, Flow of the User Break Operation. 11.3.3 Break on Data Access Cycle 1.
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Section 11 User Break Controller (UBC) word data in bits 31 to 16 in BDRB and BDMRB when including the value of the data bus as a break condition for the MOVS.W @-As,Ds, MOVS.W @As,Ds, MOVS.W @As+,Ds, or MOVS.W @As+Ix,Ds instruction (bits 15 to 0 are ignored). 4. Access by a PREF instruction is handled as read access in longword units without access data. Therefore, if including the value of the data bus when a PREF instruction is specified as a break condition, a break will not occur. 5.
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Section 11 User Break Controller (UBC) 11.3.5 Sequential Break 1. By setting the SEQ bit in BRCR to 1, the sequential break is issued when a channel B break condition matches after a channel A break condition matches. A user break is not generated even if a channel B break condition matches before a channel A break condition matches. When channels A and B conditions match at the same time, the sequential break is not issued.
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Section 11 User Break Controller (UBC) 4. When data access (address + data) is specified as a break condition: When a data value is added to the break conditions, the address of an instruction that is within two instructions of the instruction that matched the break condition is saved in the SPC. At which instruction the break occurs cannot be determined accurately. When a delay slot instruction matches the condition, the branch destination address is saved in the SPC.
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Section 11 User Break Controller (UBC) 11.3.
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Section 11 User Break Controller (UBC) After an instruction with and address H'00037226 is executed, a user break occurs before an instruction with and address H'0003722E is executed.
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Section 11 User Break Controller (UBC) (Example 1-5) • Register specifications BARA = H'00000500, BAMRA = H'00000000, BBRA = H'0057, BARB = H'00001000, BAMRB = H'00000000, BBRB = H'0057, BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00000001, BETR = H'0005 Specified conditions: Channel A/channel B independent mode Address: H'00000500, Address mask: H'00000000 Bus cycle: L bus/instruction fetch (before instruction execution)/read/longword Address: H'00001000, Address mask: H'000000
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Section 11 User Break Controller (UBC) Break Condition Specified for L Bus Data Access Cycle: (Example 2-1) • Register specifications BARA = H'00123456, BAMRA = H'00000000, BBRA = H'0064, BARB = H'000ABCDE, BAMRB = H'000000FF, BBRB = H'006A, BDRB = H'0000A512, BDMRB = H'00000000, BRCR = H'00000080 Specified conditions: Channel A/channel B independent mode Address: H'00123456, Address mask: H'00000000 Bus cycle: L bus/data access/read (operand size is not included in the condition) A
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Section 11 User Break Controller (UBC) Break Condition Specified for I Bus Data Access Cycle: (Example 3-1) • Register specifications BARA = H'00314156, BAMRA = H'00000000, BBRA = H'0094, BARB = H'00055555, BAMRB = H'00000000, BBRB = H'00A9, BDRB = H'00007878, BDMRB = H'00000F0F, BRCR = H'00000080 Specified conditions: Channel A/channel B independent mode Address: H'00314156, Address mask: H'00000000 Bus cycle: I bus/instruction fetch/read (operand size is not included in the condition)
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Section 11 User Break Controller (UBC) 4. When a user break and another exception occur at the same instruction, which has higher priority is determined according to the priority levels defined in table 9.1 in section 9, Exception Handling. If an exception with higher priority occurs, the user break is not generated.  Pre-execution break has the highest priority.
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Section 11 User Break Controller (UBC) Rev. 4.00 Sep.
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Section 12 Bus State Controller (BSC) Section 12 Bus State Controller (BSC) The bus state controller (BSC) outputs control signals for various types of memory that is connected to the external address space and external devices. BSC functions enable this LSI to connect directly with SRAM, SDRAM, and other memory storage devices, and external devices. 12.1 Features The BSC has the following features: 1.
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Section 12 Bus State Controller (BSC)  Supports low-frequency and power-down modes.  Issues MRS and EMRS commands. 6. Byte-selection SRAM interface  Can connect directly to a byte-selection SRAM 7. Burst MPX-IO interface  Can connect directly to a peripheral LSI that needs an address/data multiplexing.  Supports burst transfer 8. Burst ROM interface (clock synchronous)  Can connect directly to a ROM of the clock synchronous type 9.
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Section 12 Bus State Controller (BSC) Bus mastership controller BACK BREQ Internal bus BSC functional block diagram is shown in figure 12.1. CMNCR CS0WCR ... ... Wait controller WAIT CS6BWCR RWTCNT Module bus CS0BCR ... Area controller ... CS0, CS2, CS3, CS4, CS5A, CS5B, CS6A, CS6B CS6BBCR ...
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Section 12 Bus State Controller (BSC) 12.2 Input/Output Pins Table 12.1 shows pin configuration of the BSC. Table 12.1 Pin Configuration Name I/O Function A25 to A0 Output Address bus D31 to D0 I/O Data bus BS Output Bus cycle start CS0, CS2 to CS4 Output Chip select CS5A Output Chip select Active only for address map 1 RD/WR Output Read/write Connects to WE pins when SDRAM or byte-selection SRAM is connected.
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Section 12 Bus State Controller (BSC) Name I/O Function WE0 Output Indicates that D7 to D0 are being written to. Connected to the byte select signal when a byte-selection SRAM is connected. Functions as the selection signals for D7 to D0 when SDRAM is connected. RASU Output Connects to RAS pin when SDRAM is connected. Output Connects to CAS pin when SDRAM is connected.
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Section 12 Bus State Controller (BSC) 12.3.2 Shadow Area Areas 0, 2 to 4, 5A, 5B, 6A, and 6B are decoded by addresses A28 to A26, which correspond to areas 000 to 110. Address bits 31 to 29 are ignored. This means that the range of area 0 addresses, for example, is H'00000000 to H'03FFFFFF, and its corresponding shadow space is the address space between P0 and P3 obtained by adding to it H'20000000 × n (n = 1 to 6). The address range for area 7 is H'1C000000 to H'1FFFFFFF.
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Section 12 Bus State Controller (BSC) 12.3.3 Address Map The external address space has a capacity of 384 Mbytes and is used by dividing 8 partial spaces. The kind of memory to be connected and the data bus width are specified in each partial space. The address map for the external address space is listed below. Table 12.2 Address Space Map 1 (CMNCR.
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Section 12 Bus State Controller (BSC) Table 12.3 Address Space Map 2 (CMNCR.
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Section 12 Bus State Controller (BSC) 12.3.4 Area 0 Memory Type and Memory Bus Width The memory bus width in this LSI can be set for each area. In area 0, external pins can be used to select word (16 bits), or longword (32 bits) on power-on reset. The correspondence between the external pin MD3 and memory size is listed in the table below. Table 12.4 Correspondence between External Pin MD3 and Bus Width of Area 0 MD3 Bus Width of Area 0 0 16 bits 1 32 bits 12.
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Section 12 Bus State Controller (BSC) • • • • Refresh timer control/status register (RTCSR) Refresh timer counter (RTCNT) Refresh time constant register (RTCOR) Reset wait counter (RWTCNT) 12.4.1 Common Control Register (CMNCR) CMNCR is a 32-bit register that controls the common items for each area. This register is only initialized by a power-on reset, and it is not initialized by a manual reset and in the standby mode.
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Section 12 Bus State Controller (BSC) Bit Bit Name Initial Value R/W Description 11 BLOCK 0 R/W Bus Clock Specifies whether or not the BREQ signal is received. 0: Receives BREQ. 1: Does not receive BREQ. 10 DPRTY1 0 R/W DMA Burst Transfer Priority 9 DPRTY0 0 R/W Specify the priority for a refresh request/bus mastership request during DMA burst transfer. 00: Accepts a refresh request and bus mastership request during DMA burst transfer.
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Section 12 Bus State Controller (BSC) Bit Bit Name Initial Value R/W Description 5 DMAIWA 0 R/W Method of inserting wait states between access cycles when DMA single address transfer is performed. Specifies the method of inserting the idle cycles specified by the DMAIW[2:0] bit. Clearing this bit will make this LSI insert the idle cycles when another device, which includes this LSI, drives the data bus after an external device with DACK drove it.
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Section 12 Bus State Controller (BSC) Bit Bit Name Initial Value R/W Description 0 HIZCNT 0 R/W High-Z Control Specifies the state in software standby mode and bus released for CKIO2, RASU, RASL, CASU, and CASL. 0: High impedance in software standby mode and bus released for CKIO2, RASU, RASL, CASU, and CASL. 1: Driven in standby mode and bus released for CKIO2, RASU, RASL, CASU, and CASL. 12.4.
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Section 12 Bus State Controller (BSC) Bit Bit Name Initial Value R/W Description 27 IWRWD2 1 R/W Idle Cycles for Another Space Read-Write 26 IWRWD1 1 R/W 25 IWRWD0 1 R/W Specify the number of idle cycles to be inserted after the access to a memory that is connected to the space. The target access cycle is a read-write one in which continuous accesses switch between different spaces.
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Section 12 Bus State Controller (BSC) Bit Bit Name Initial Value R/W Description 21 IWRRD2 1 R/W Idle Cycles for Read-Read in Another Space 20 WRRD1 1 R/W 19 IWRRD0 1 R/W Specify the number of idle cycles to be inserted after the access to a memory that is connected to the space. The target cycle is a read-read cycle of which continuous accesses switch between different spaces.
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Section 12 Bus State Controller (BSC) Bit Bit Name Initial Value R/W Description 14 TYPE2 0 R/W Specify the type of memory connected to a space. 13 TYPE1 0 R/W 0000: Normal space 12 TYPE0 0 R/W 0001: Burst ROM (clock synchronous) 0010: MPX-I/O 0011: Byte-selection SRAM 0100: SDRAM 0101: Reserved (Setting prohibited) 0110: Burst MPX-I/O 0111: Burst ROM (Clock synchronous) For details for memory type in each area, refer to tables 12.2 and 12.3.
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Section 12 Bus State Controller (BSC) Bit Bit Name Initial Value R/W Description 10 BSZ1 1* R/W Data Bus Size 9 BSZ0 1* R/W Specify the data bus sizes of spaces. The data bus sizes of areas 2, 3, 4 and 5A are shown below. 00: Reserved (setting prohibited) 01: 8-bit size 10: 16-bit size 11: 32-bit size For MPX-I/O, selects bus width by address Notes: 1.
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Section 12 Bus State Controller (BSC) 12.4.3 CSn Space Wait Control Register (CSnWCR) (n = 0, 2, 3, 4, 5A, 5B, 6A, 6B) This register specifies various wait cycles for memory accesses. The bit configuration of this register varies as shown below according to the memory type (TYPE2 to TYPE0) specified by the CSn space bus control register (CSnBCR). Specify the CSnWCR register before accessing the target area. Specify CSnBCR register first, then specify the CSnWCR register.
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Section 12 Bus State Controller (BSC) Bit Bit Name Initial Value R/W Description 10 WR3 1 R/W Number of Access Wait Cycles 9 WR2 0 R/W 8 WR1 1 R/W Specify the number of cycles that are necessary for read/write access.
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Section 12 Bus State Controller (BSC) Bit Bit Name Initial Value R/W Description 1 HW1 0 R/W 0 HW0 0 R/W Delay Cycles from RD, WEn Negation to Address, CSn Negation Specify the number of delay cycles from RD and WEn negation to address and CSn negation. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.
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Section 12 Bus State Controller (BSC) Bit Bit Name Initial Value R/W Description 10 WR3 1 R/W Number of Access Wait Cycles 9 WR2 0 R/W 8 WR1 1 R/W Specify the number of cycles that are necessary for read/write access.
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Section 12 Bus State Controller (BSC) • CS4WCR Bit Bit Name Initial Value R/W Description 31 to 21  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 20 BAS 0 R/W Byte-Selection SRAM Byte Access Selection Specifies the WEn and RD/WR signal timing when the byte-selection SRAM interface is used. 0: Asserts the WEn signal at the read timing and asserts the RD/WR signal during the write access cycle.
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Section 12 Bus State Controller (BSC) Bit Bit Name Initial Value R/W Description 12 SW1 0 R/W 11 SW0 0 R/W Number of Delay Cycles from Address, CSn Assertion to RD, WE Assertion Specify the number of delay cycles from address and CSn assertion to RD and WE assertion. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles 10 WR3 1 R/W Number of Read Access Wait Cycles 9 WR2 0 R/W 8 WR1 1 R/W Specify the number of cycles that are necessary for read access.
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Section 12 Bus State Controller (BSC) Bit Bit Name Initial Value R/W Description 5 to 2  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1 HW1 0 R/W 0 HW0 0 R/W Delay Cycles from RD, WEn Negation to Address, CSn Negation Specify the number of delay cycles from RD and WEn negation to address and CSn negation. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.
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Section 12 Bus State Controller (BSC) Bit Bit Name Initial Value R/W Description 12 SW1 0 R/W 11 SW0 0 R/W Number of Delay Cycles from Address, CSn Assertion to RD, WE Assertion Specify the number of delay cycles from address and CSn assertion to RD and WE assertion. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles 10 WR3 1 R/W Number of Read Access Wait Cycles 9 WR2 0 R/W 8 WR1 1 R/W Specify the number of cycles that are necessary for read access.
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Section 12 Bus State Controller (BSC) Bit Bit Name Initial Value R/W Description 5 to 2  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1 HW1 0 R/W 0 HW0 0 R/W Delay Cycles from RD, WEn Negation to Address, CSn Negation Specify the number of delay cycles from RD and WEn negation to address and CSn negation. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.
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Section 12 Bus State Controller (BSC) Bit Bit Name Initial Value R/W Description 20 MPX 0 R/W MPX-IO Interface Address Wait Specifies the address cycle insertion wait for MPX-IO interface. This bit setting is valid only when area 5B is specified as MPX-I/O. 0: Inserts no wait cycle 1: Inserts 1 wait cycle BAS 0 R/W Byte-Selection SRAM Byte Access Selection This bit setting is valid only when area 5B is specified as byte-selection SRAM.
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Section 12 Bus State Controller (BSC) Bit Bit Name Initial Value R/W Description 12 SW1 0 R/W 11 SW0 0 R/W Number of Delay Cycles from Address, CSn Assertion to RD, WE Assertion Specify the number of delay cycles from address and CSn assertion to RD and WE assertion. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles 10 WR3 1 R/W Number of Read Access Wait Cycles 9 WR2 0 R/W 8 WR1 1 R/W Specify the number of cycles that are necessary for read access.
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Section 12 Bus State Controller (BSC) Bit Bit Name Initial Value R/W Description 5 to 2  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1 HW1 0 R/W 0 HW0 0 R/W Delay Cycles from RD, WEn Negation to Address, CSn Negation Specify the number of delay cycles from RD and WEn negation to address and CSn negation. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.
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Section 12 Bus State Controller (BSC) Bit Bit Name Initial Value R/W Description 10 WR3 1 R/W Number of Access Wait Cycles 9 WR2 0 R/W 8 WR1 1 R/W Specify the number of cycles that are necessary for read/write access.
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Section 12 Bus State Controller (BSC) Bit Bit Name Initial Value R/W Description 1 HW1 0 R/W 0 HW0 0 R/W Delay Cycles from RD, WEn Negation to Address, CSn Negation Specify the number of delay cycles from RD and WEn negation to address and CSn negation. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles • CS6BWCR Bit Bit Name Initial Value R/W 31 to 21  All 0 R Description Reserved These bits are always read as 0. The write value should always be 0.
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Section 12 Bus State Controller (BSC) Bit Bit Name Initial Value R/W Description 10 WR3 1 R/W Number of Access Wait Cycles 9 WR2 0 R/W 8 WR1 1 R/W Specify the number of cycles that are necessary for read/write access.
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Section 12 Bus State Controller (BSC) Bit Bit Name Initial Value R/W Description 1 HW1 0 R/W 0 HW0 0 R/W Number of Delay Cycles from RD, WEn Negation to Address, CSn Negation Specify the number of delay cycles from RD, WEn negation to address, and CSn negation. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles Burst ROM (Clock Asynchronous): • CS0WCR Bit Bit Name Initial Value R/W Description 31 to 21  All 0 R Reserved These bits are always read as 0.
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Section 12 Bus State Controller (BSC) Bit Bit Name Initial Value R/W Description 17 BW1 0 R/W Number of Burst Wait Cycles 16 BW0 0 R/W Specify the number of wait cycles to be inserted between the second or later access cycles in burst access. 00: No cycle 01: 1 cycle 10: 2 cycles 11: 3 cycles 15 to 11  All 0 R Reserved These bits are always read as 0. The write value should always be 0.
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Section 12 Bus State Controller (BSC) Bit Bit Name Initial Value R/W Description 6 WM 0 R/W External Wait Mask Specification Specifies whether or not the external wait input is valid. The specification by this bit is valid even when the number of access wait cycle is 0. 0: External wait is valid 1: External wait is ignored 5 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0.
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Section 12 Bus State Controller (BSC) Bit Bit Name Initial Value R/W Description 17 BW1 0 R/W Number of Burst Wait Cycles 16 BW0 0 R/W Specify the number of wait cycles to be inserted between the second or later access cycles in burst access. 00: No cycle 01: 1 cycle 10: 2 cycles 11: 3 cycles 15 to 13  All 0 R Reserved These bits are always read as 0. The write value should always be 0.
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Section 12 Bus State Controller (BSC) Bit Bit Name Initial Value R/W Description 10 W3 1 R/W Number of Access Wait Cycles 9 W2 0 R/W 8 W1 1 R/W Specify the number of wait cycles to be inserted in the first access cycle.
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Section 12 Bus State Controller (BSC) Bit Bit Name Initial Value R/W Description 1 HW1 0 R/W 0 HW0 0 R/W Delay Cycles from RD, WEn Negation to Address, CSn Negation Specify the number of delay cycles from RD and WEn negation to address and CSn negation. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles SDRAM*: • CS2WCR Bit Bit Name Initial Value R/W Description 31 to 11  All 0 R Reserved These bits are always read as 0. The write value should always be 0.
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Section 12 Bus State Controller (BSC) • CS3WCR Bit Bit Name Initial Value R/W Description 31 to 15  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 14 WTRP1* 0 R/W Number of Auto-Precharge Completion Wait Cycles 13 WTRP0 0 R/W Specify the number of minimum precharge completion wait cycles during the periods shown below.
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Section 12 Bus State Controller (BSC) Bit Bit Name Initial Value R/W Description 9  0 R Reserved This bit is always read as 0. The write value should always be 0. 8 A3CL1 1 R/W CAS Latency for Area 3 7 A3CL0 0 R/W Specify the CAS latency for area 3. 00: 1 cycle 01: 2 cycles 10: 3 cycles 11: 4 cycles 6, 5  All 0 R Reserved These bits are always read as 0. The write value should always be 0.
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Section 12 Bus State Controller (BSC) Bit Bit Name Initial Value R/W Description 2  0 R Reserved This bit is always read as 0. The write value should always be 0. 1 WTRC1* 0 R/W 0 WTRC0 0 R/W Number of Idle Cycles from REF Command/SelfRefresh Release to ACTV/REF/MRS Command Specify the number of minimum idle cycles during the periods shown below.
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Section 12 Bus State Controller (BSC) Bit Bit Name Initial Value R/W Description 19 MPXMD 0 R/W Burst MPX-IO Interface Mode Specification Specify the access mode in 16-byte access 0: One 4-burst access by 16-byte transfer 1: Two 2-bursts accesses by quad word (8-byte) transfer Transfer size when MPXMD = 0 D31 D30 D29 : Transfer Size 0 0 0 : Byte (1 byte) 0 0 1 : Word (2 byte) 0 1 0 : Longword (4 bytes) 0 1 1 : Reserved (quad word) (8 bytes) 1 0 0 : 16 bytes 1 0 1 : Reserv
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Section 12 Bus State Controller (BSC) Bit Bit Name Initial Value R/W Description 15 to 11  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 10 W3 1 R/W Number of Access Wait Cycles 9 W2 0 R/W 8 W1 1 R/W Specify the number of wait cycles to be inserted in the first access cycle.
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Section 12 Bus State Controller (BSC) Burst ROM (Clock Synchronous): • CS0WCR Bit Bit Name Initial Value R/W 31 to 18  All 0 R Description Reserved These bits are always read as 0. The write value should always be 0. 17 BW1 0 R/W Number of Burst Wait Cycles 16 BW0 0 R/W Specify the number of wait cycles to be inserted between the second or later access cycles in burst access.
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Section 12 Bus State Controller (BSC) Bit Bit Name Initial Value R/W Description 10 W3 1 R/W Number of Access Wait Cycles 9 W2 0 R/W 8 W1 1 R/W Specify the number of wait cycles to be inserted in the first access cycle.
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Section 12 Bus State Controller (BSC) 12.4.4 SDRAM Control Register (SDCR) SDCR specifies the method to refresh and access SDRAM, and the types of SDRAMs to be connected. This register is initialized to H'00000000 by a power-on reset, and it is not initialized by a manual reset and in the standby mode. Bit Bit Name Initial Value R/W Description 31 to 21  All 0 R Reserved These bits are always read as 0. The write value should always be 0.
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Section 12 Bus State Controller (BSC) Bit Bit Name Initial Value R/W Description 13 DEEP 0 R/W Deep Power-Down Mode This bit is valid for low-power SDRAM. If the RFSH or RMODE bit is set to 1 while this bit is set to 1, the deep power-down entry command is issued and the lowpower SDRAM enters the deep power-down mode.
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Section 12 Bus State Controller (BSC) Bit Bit Name Initial Value R/W Description 9 PDOWN 0 R Power-Down Mode Specifies whether the SDRAM will enter the powerdown mode or not after the access to the external memory other than the SDRAM or to the internal I/O resister. With this bit being set to 1, the access to the external memory other than the SDRAM or to the internal I/O register drives the CKE signal low and causes the SDRAM to enter the power-down mode.
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Section 12 Bus State Controller (BSC) Bit Bit Name Initial Value R/W Description 2  0 R Reserved This bit is always read as 0. The write value should always be 0. 1 A3COL1 0 R/W Number of Bits of Column Address for Area 3 0 A3COL0 0 R/W Specify the number of bits of the column address for area 3. 00: 8 bits 01: 9 bits 10: 10 bits 11: Reserved (Setting prohibited) 12.4.5 Refresh Timer Control/Status Register (RTCSR) RTCSR specifies various items about refresh for SDRAM.
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Section 12 Bus State Controller (BSC) Bit Bit Name Initial Value R/W Description 6  0 R Reserved This bit is always read as 0. The write value should always be 0. 5 CKS2 0 R/W Clock Select 4 CKS1 0 R/W 3 CKS0 0 R/W Select the clock input to count-up the refresh timer counter (RTCNT).
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Section 12 Bus State Controller (BSC) 12.4.6 Refresh Timer Counter (RTCNT) RTCNT is an 8-bit counter that increments using the clock selected by bits CKS2 to CKS0 in RTCSR. When RTCNT matches RTCOR, RTCNT is cleared to 0. The value in RTCNT returns to 0 after counting up to 255. When the RTCNT is written, the upper 16 bits of the write data must be H'A55A to cancel write protection.
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Section 12 Bus State Controller (BSC) 12.4.8 Reset Wait Counter (RWTCNT) RWTCNT is a 7-bit counter. This counter starts to increment by synchronizing the CKIO after a power-on reset is released, and stops when the value reaches H'007F. External bus access is suspended while the counter is operating. This counter is provided to minimize the time from releasing a reset for flash memory to the first access.
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Section 12 Bus State Controller (BSC) 12.5 Operating Description 12.5.1 Endian/Access Size and Data Alignment This LSI supports big endian, in which the 0 address is the most significant byte (MSByte) in the byte data. Three data bus widths (8 bits, 16 bits, and 32 bits) are available for normal memory and byteselection SRAM. Two data bus width (16 bits and 32 bits) are available for SDRAM. Data bus width for MPX-IO is fixed to 32 bits.
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Section 12 Bus State Controller (BSC) Table 12.
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Section 12 Bus State Controller (BSC) Table 12.
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Section 12 Bus State Controller (BSC) 12.5.2 Normal Space Interface Basic Timing: For access to a normal space, this LSI uses strobe signal output in consideration of the fact that mainly static RAM will be directly connected. When using SRAM with a byteselection pin, see section 12.5.8, Byte-Selection SRAM Interface. Figure 12.3 shows the basic timings of normal space access. A no-wait normal access is completed in two cycles. The BS signal is asserted for one cycle to indicate the start of a bus cycle.
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Section 12 Bus State Controller (BSC) It is necessary to output the data that has been read using RD when a buffer is established in the data bus. The RD/WR signal is in a read state (high output) when no access has been carried out. Therefore, care must be taken when controlling the external data buffer, to avoid collision. Figures 12.4 and 12.5 show the basic timings of normal space accesses.
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Section 12 Bus State Controller (BSC) T1 T2 T1 T2 CKIO A25 to A0 CSn RD/WR RD Read D15 to D0 WEn Write D15 to D0 BS DACKn * WAIT Note: * The waveform for DACKn is when active low is specified. Figure 12.5 Continuous Access for Normal Space 2 Bus Width = 16 Bits, Longword Access, CSnWCR.WN Bit = 1 (Access Wait = 0, Cycle Wait = 0) Rev. 4.00 Sep.
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Section 12 Bus State Controller (BSC) 128k × 8-bit SRAM •••• A0 CS OE I/O7 •••• I/O0 WE •••• •••• •••• •••• A16 A0 CS OE I/O7 •••• •••• D8 WE1 D7 •••• •••• D16 WE2 D15 •••• •••• D24 WE3 D23 I/O0 WE •••• D0 WE0 A16 •••• •••• A2 CSn RD D31 A16 •••• •••• •••• A18 •••• This LSI •••• A0 CS OE I/O7 •••• A16 A0 CS OE I/O7 •••• •••• •••• I/O0 WE I/O0 WE Figure 12.6 Example of 32-Bit Data-Width SRAM Connection Rev. 4.00 Sep.
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Section 12 Bus State Controller (BSC) 128k × 8-bit SRAM •••• A0 CS OE I/O7 •••• I/O0 WE •••• •••• •••• D0 WE0 A16 •••• •••• D8 WE1 D7 A0 CS OE I/O7 •••• •••• A1 CSn RD D15 A16 •••• •••• •••• A17 •••• This LSI I/O0 WE Figure 12.7 Example of 16-Bit Data-Width SRAM Connection 128k × 8-bit SRAM This LSI A0 CS RD OE D7 I/O7 ... A0 CSn ... ... A16 ... A16 D0 I/O0 WE0 WE Figure 12.8 Example of 8-Bit Data-Width SRAM Connection Rev. 4.00 Sep.
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Section 12 Bus State Controller (BSC) 12.5.3 Access Wait Control Wait cycle insertion on a normal space access can be controlled by the settings of bits WR3 to WR0 in CSnWCR. It is possible for areas 4, 5A, and 5B to insert wait cycles independently in read access and in write access. The areas other than 4, 5A, and 5B have common access wait for read cycle and write cycle. The specified number of Tw cycles are inserted as wait cycles in a normal space access shown in figure 12.9.
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Section 12 Bus State Controller (BSC) When the WM bit in CSnWCR is cleared to 0, the external wait input WAIT signal is also sampled. WAIT pin sampling is shown in figure 12.10. A 2-cycle wait is specified as a software wait. The WAIT signal is sampled on the falling edge of CKIO at the transition from the T1 or Tw cycle to the T2 cycle.
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Section 12 Bus State Controller (BSC) 12.5.4 CSn Assert Period Expansion The number of cycles from CSn assertion to RD, WEn assertion can be specified by setting bits SW1 and SW0 in CSnWCR. The number of cycles from RD, WEn negation to CSn negation can be specified by setting bits HW1 and HW0. Therefore, a flexible interface to an external device can be obtained. Figure 12.11 shows an example. A Th cycle and a Tf cycle are added before and after an ordinary cycle, respectively.
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Section 12 Bus State Controller (BSC) 12.5.5 MPX-I/O Interface Access timing for the MPX space is shown below. In the MPX space, CS5B, AH, RD, and WEn signals control the accessing. The basic access for the MPX space consists of 2 cycles of address output followed by an access to a normal space. The bus width for the address output cycle or the data input/output cycle is fixed to 8 bits or 16 bits. Alternatively, it can be 8 bits or 16 bits depending on the address to be accessed.
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Section 12 Bus State Controller (BSC) Ta1 Tadw Ta2 Ta3 T1 T2 CKIO A25 to A16 CSn RD/WR AH Read RD D7 to D0 or D15 to D0 Address Data WEn Write D7 to D0 or D15 to D0 Address Data BS DACKn* Note: * The waveform for DACKn is when active low is specified. Figure 12.13 Access Timing for MPX Space (Address Cycle Wait 1, Data Cycle No Wait) Rev. 4.00 Sep.
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Section 12 Bus State Controller (BSC) Ta1 Tadw Ta2 Ta3 T1 Tw Twx T2 CKIO A25 to A16 CS5B RD/WR AH RD Read D7 to D0 or D15 to D0 Address Data WEn Write D7 to D0 or D15 to D0 Address Data WAIT BS DACKn* Note: * The waveform for DACKn is when active low is specified. Figure 12.14 Access Timing for MPX Space (Address Cycle Access Wait 1, Data Cycle Wait 1, External Wait 1) Rev. 4.00 Sep.
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Section 12 Bus State Controller (BSC) 12.5.6 SDRAM Interface SDRAM Direct Connection: The SDRAM that can be connected to this LSI is a product that has 11/12/13 bits of row address, 8/9/10 bits of column address, 4 or less banks, and uses the A10 pin for setting precharge mode in read and write command cycles. The control signals for direct connection of SDRAM are RASU, RASL, CASU, CASL, RD/WR, DQMUU, DQMUL, DQMLU, DQMLL, CKE, CS2, and CS3.
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Section 12 Bus State Controller (BSC) Figures 12.15 to 12.17 show examples of the connection of the SDRAM with the LSI. As shown in figure 12.17, two sets of SDRAMs of 32 Mbytes or smaller can be connected to the same CS space by using RASU, RASL, CASU, and CASL. In this case, a total of 8 banks are assigned to the same CS space: 4 banks specified by RASL and CASL, and 4 banks specified by RAS and CAS. When accessing the address with A25 = 0, RASL and CASL are asserted.
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Section 12 Bus State Controller (BSC) 64M SDRAM (1M × 16-bit × 4-bank) This LSI A13 ... ... A14 D0 DQMLU DQMLL A0 CKE CLK CS Unused Unused RAS CAS WE I/O15 ... ... A1 CKE CKIO CSn RASU CASU RASL CASL RD/WR D15 I/O0 DQMU DQML Figure 12.16 Example of 16-Bit Data Width SDRAM Connection (RASU and CASU are Not Used) Rev. 4.00 Sep.
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Section 12 Bus State Controller (BSC) 64M SDRAM (1M × 16-bit × 4-bank) ... A1 CKE CKIO CSn RASU CASU RASL CASL RD/WR D15 D16 DQMLU DQMLL A13 ... ... A14 A0 CKE CLK CS RAS CAS WE I/O15 ... This LSI I/O0 DQMU DQML ... A13 A0 CKE CLK CS ... RAS CAS WE I/O15 I/O0 DQMU DQML Figure 12.17 Example of 16-Bit Data Width SDRAM Connection (RASU and CASU are Used) Rev. 4.00 Sep.
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Section 12 Bus State Controller (BSC) Address Multiplexing: An address multiplexing is specified so that SDRAM can be connected without external multiplexing circuitry according to the setting of bits BSZ1 and BSZ0 in CSnBCR, AxROW[1:0] and AxCOL[1:0] in SDCR. Tables 12.8 to 12.13 show the relationship between the settings of bits BSZ1 and BSZ0, AxROW[1:0], and AxCOL[1:0] and the bits output at the address pins.
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Section 12 Bus State Controller (BSC) Table 12.
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Section 12 Bus State Controller (BSC) Table 12.
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Section 12 Bus State Controller (BSC) Table 12.
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Section 12 Bus State Controller (BSC) Table 12.
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Section 12 Bus State Controller (BSC) Table 12.
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Section 12 Bus State Controller (BSC) Table 12.
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Section 12 Bus State Controller (BSC) Table 12.
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Section 12 Bus State Controller (BSC) Table 12.
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Section 12 Bus State Controller (BSC) Table 12.
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Section 12 Bus State Controller (BSC) Table 12.
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Section 12 Bus State Controller (BSC) Table 12.
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Section 12 Bus State Controller (BSC) Burst Read: A burst read occurs in the following cases with this LSI. • Access size in reading is larger than data bus width. • 16-byte transfer in cache error. • 16-byte transfer in DMAC This LSI always accesses the SDRAM with burst length 1. For example, read access of burst length 1 is performed consecutively 4 times to read 16-byte continuous data from the SDRAM that is connected to a 32-bit data bus. Table 12.
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Section 12 Bus State Controller (BSC) number of cycles from the Tc1 cycle where the READ command is output to the Td1 cycle where the read data is latched can be specified for the CS2 and CS3 spaces independently, using the A2CL1 and A2CL0 bits in the CS2WCR register or the A3CL1 and A3CL0 bits in the CS3WCR register and WTRCD0 bit in the CS3WCR register. The number of cycles from Tc1 to Td1 corresponds to the SDRAM CAS latency. The CAS latency for the SDRAM is normally defined as up to three cycles.
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Section 12 Bus State Controller (BSC) Tr Trw Tc1 Tw Tc2 Td1 Tc3 Td2 Tc4 Td3 Td4 Tde (Tap) CKIO A25 to A0 A12/A11*1 CSn RASL, RASU CASL, CASU RD/WR DQMxx D31 to D0 BS DACKn*2 Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 12.19 Burst Read Wait Specification Timing (CAS Latency 2, WTRCD1 and WTRCD0 = 1 Cycle, Auto Pre-Charge) Rev. 4.00 Sep.
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Section 12 Bus State Controller (BSC) Single Read: A read access ends in one cycle when data exists in non-cacheable region and the data bus width is larger than or equal to access size. As the burst length is set to 1 in synchronous DRAM burst read/single write mode, only the required data is output. Figure 12.20 shows the single read basic timing. Tr Tc1 Td1 Tde Tap CKIO A25 to A0 A12/A11*1 CSn RASL, RASU CASL, CASU RD/WR DQMxx D31 to D0 BS DACKn*2 Notes: 1.
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Section 12 Bus State Controller (BSC) Burst Write: A burst write occurs in the following cases in this LSI. • Access size in writing is larger than data bus width. • Write-back of the cache • 16-byte transfer in DMAC This LSI always accesses SDRAM with burst length 1. For example, write access of burst length 1 is performed continuously 4 times to write 16-byte continuous data to the SDRAM that is connected to a 32-bit data bus.
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Section 12 Bus State Controller (BSC) Tr Tc1 Tc2 Tc3 Tc4 Trwl Tap CKIO A25 to A0 A12/A11*1 CSn RASL, RASU CASL, CASU RD/WR DQMxx D31 to D0 BS DACKn*2 Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 12.21 Basic Timing for Burst Write (Auto Pre-Charge) Rev. 4.00 Sep.
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Section 12 Bus State Controller (BSC) Single Write: A write access ends in one cycle when data is written in non-cacheable region and the data bus width is larger than or equal to access size. Figure 12.22 shows the single write basic timing. Tr Tc1 Trwl Tap CKIO A25 to A0 A12/A11*1 CSn RASL, RASU CASL, CASU RD/WR DQMxx D31 to D0 BS DACKn*2 Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 12.
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Section 12 Bus State Controller (BSC) Bank Active: The synchronous DRAM bank function is used to support high-speed accesses to the same row address. When the BACTV bit in SDCR is 1, accesses are performed using commands without auto-precharge (READ or WRIT). This function is called bank-active function. This function is valid only for either the upper or lower bits of area 3. When area 3 is set to bankactive mode, area 2 should be set to normal space.
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Section 12 Bus State Controller (BSC) When bank active mode is set, if only accesses to the respective banks in the area 3 space are considered, as long as accesses to the same row address continue, the operation starts with the cycle in figure 12.23 or 12.26, followed by repetition of the cycle in figure 12.24 or 12.27. An access to a different area during this time has no effect. If there is an access to a different row address in the bank active state, after this is detected the bus cycle in figure 12.
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Section 12 Bus State Controller (BSC) Tnop Tc1 Td1 Tc2 Td2 Tc3 Td3 Tc4 Td4 Tde CKIO A25 to A0 A12/A11*1 CSn RASL, RASU CASL, CASU RD/WR DQMxx D31 to D0 BS DACKn*2 Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 12.24 Burst Read Timing (Bank Active, Same Row Addresses in the Same Bank, CAS Latency 1) Rev. 4.00 Sep.
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Section 12 Bus State Controller (BSC) Tp Tpw Tr Tc1 Td1 Tc2 Td2 Tc3 Td3 Tc4 Td4 Tde CKIO A25 to A0 A12/A11*1 CSn RASL, RASU CASL, CASU RD/WR DQMxx D31 to D0 BS DACKn*2 Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 12.25 Burst Read Timing (Bank Active, Different Row Addresses in the Same Bank, CAS Latency 1) Rev. 4.00 Sep.
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Section 12 Bus State Controller (BSC) Tr Tc1 CKIO A25 to A0 A12/A11*1 CSn RASL, RASU CASL, CASU RD/WR DQMxx D31 to D0 BS DACKn*2 Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 12.26 Single Write Timing (Bank Active, Different Bank) Rev. 4.00 Sep.
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Section 12 Bus State Controller (BSC) Tnop Tc1 CKIO A25 to A0 A12/A11*1 CSn RASL, RASU CASL, CASU RD/WR DQMxx D31 to D0 BS DACKn*2 Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 12.27 Single Write Timing (Bank Active, Same Row Addresses in the Same Bank) Rev. 4.00 Sep.
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Section 12 Bus State Controller (BSC) Tp Tpw Tr Tc1 CKIO A25 to A0 A12/A11*1 CSn RASL, RASU CASL, CASU RD/WR DQMxx D31 to D0 BS DACKn*2 Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 12.28 Single Write Timing (Bank Active, Different Row Addresses in the Same Bank) Refreshing: This LSI has a function for controlling synchronous DRAM refreshing.
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Section 12 Bus State Controller (BSC) 1. Auto-refreshing Refreshing is performed at intervals determined by the input clock selected by bits CKS2 to CKS0 in RTCSR, and the value set by in RTCOR. The value of bits CKS2 to CKS0 in RTCOR should be set so as to satisfy the refresh interval stipulation for the synchronous DRAM used. First make the settings for RTCOR, RTCNT, and the RMODE and RFSH bits in SDCR, then make the CKS2 to CKS0 and RRC2 to RRC0 settings.
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Section 12 Bus State Controller (BSC) Tp Tpw Trr Trc Trc Trc CKIO A25 to A0 A12/A11*1 CSn RASL, RASU CASL, CASU RD/WR DQMxx D31 to D0 Hi-z BS DACKn*2 Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 12.29 Auto-Refresh Timing 2. Self-refreshing Self-refresh mode in which the refresh timing and refresh addresses are generated within the synchronous DRAM.
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Section 12 Bus State Controller (BSC) Self-refresh timing is shown in figure 12.30. Settings must be made so that self-refresh clearing and data retention are performed correctly, and auto-refreshing is performed at the correct intervals.
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Section 12 Bus State Controller (BSC) Relationship between Refresh Requests and Bus Cycles: If a refresh request occurs during bus cycle execution, the refresh cycle must wait for the bus cycle to be completed. If a refresh request occurs while the bus is released by the bus arbitration function, the refresh will not be executed until the bus mastership is acquired. If a new refresh request occurs while waiting for the previous refresh request, the previous refresh request is deleted.
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Section 12 Bus State Controller (BSC) Tr Tc1 Td1 Tde Tap Tr Tc1 Tnop Trwl Tap CKIO (High) CKE A25 to A0 A12/A11*1 CSn RASL, RASU CASL, CASU RD/WR DQMxx D31 to D0 BS DACKn*2 Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 12.
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Section 12 Bus State Controller (BSC) Power-down Tnop Tr Tc1 Td1 Tde Tap Power-down CKIO CKE A25 to A0 A12/A11*1 CSn RASL, RASU CASL, CASU RD/WR DQMxx D31 to D0 BS DACKn*2 Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 12.32 Power-Down Mode Access Timing The conditions to shift to the power-down mode are as follows.
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Section 12 Bus State Controller (BSC) Power-On Sequence: In order to use synchronous DRAM, mode setting must first be performed after powering on. To perform synchronous DRAM initialization correctly, the bus state controller registers must first be set, followed by a write to the synchronous DRAM mode register. In synchronous DRAM mode register setting, the address signal value at that time is latched by a combination of the CSn, RASU, RASL, CASU, CASL, and RD/WR signals.
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Section 12 Bus State Controller (BSC) • Setting for Area 3 Burst read/single write (burst length 1): Data Bus Width CAS Latency Access Address External Address Pin 16 bits 2 H'A4FD5440 H'0000440 3 H'A4FD5460 H'0000460 2 H'A4FD5880 H'0000880 3 H'A4FD58C0 H'00008C0 32 bits Burst read/burst write (burst length 1): Data Bus Width CAS Latency Access Address External Address Pin 16 bits 2 H'A4FD5040 H'0000040 3 H'A4FD5060 H'0000060 2 H'A4FD5080 H'0000080 3 H'A4FD50C0 H'00000C0
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Section 12 Bus State Controller (BSC) Tp PALL Tpw Trr REF Trc Trc Trr REF Trc Trc Tmw MRS Tnop CKIO A25 to A0 A12/A11*1 CSn RASL, RASU CASL, CASU RD/WR DQMxx D31 to D0 Hi-Z BS DACKn*2 Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 12.33 Synchronous DRAM Mode Write Timing (Based on JEDEC) Low-Power SDRAM: The low-power SDRAM can be accessed using the same protocol as the normal SDRAM.
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Section 12 Bus State Controller (BSC) Table 12.
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Section 12 Bus State Controller (BSC) • Deep power-down mode The low-power SDRAM supports the deep power-down mode as a low-power consumption mode. In the partial self-refresh function, self-refresh is performed on a specific area. In the deep power-down mode, self-refresh will not be performed on any memory area. This mode is effective in systems where all of the system memory areas are used as work areas.
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Section 12 Bus State Controller (BSC) 12.5.7 Burst ROM (Clock Asynchronous) Interface The burst ROM (clock asynchronous) interface is used to access a memory with a high-speed read function using a method of address switching called the burst mode or page mode. In a burst ROM (clock asynchronous) interface, basically the same access as the normal space is performed, but the 2nd and subsequent accesses are performed only by changing the address, without negating the RD signal at the end of the 1st cycle.
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Section 12 Bus State Controller (BSC) T1 Tw Tw TB2 Twb TB2 Twb TB2 Twb T2 CKIO A25 to A0 CSn RD/WR RD D15 to D0 WAIT BS DACKn* Note: * The waveform for DACKn when active low is specified. Figure 12.36 Burst ROM Access Timing (Clock Asynchronous) (Bus Width = 32 Bits, 16-Byte Transfer (Number of Burst 4), Wait Cycles Inserted in First Access = 2, Wait Cycles Inserted in Second and Subsequent Accesses = 1) 12.5.
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Section 12 Bus State Controller (BSC) T2 T1 CKIO A25 to A0 CSn WEn RD/WR Read RD D31 to D0 RD/WR Write High RD D31 to D0 BS DACKn* Note: * The waveform for DACKn is when active low is specified. Figure 12.37 Byte-Selection RAM Basic Access Timing (BAS = 0) Rev. 4.00 Sep.
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Section 12 Bus State Controller (BSC) T1 T2 CKIO A25 to A0 CSn WEn RD/WR Read RD D31 to D0 RD/WR High Write RD D31 to D0 BS DACKn* Note: * The waveform for DACKn is when active low is specified. Figure 12.38 Byte-Selection RAM Basic Access Timing (BAS = 1) Rev. 4.00 Sep.
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Section 12 Bus State Controller (BSC) Th T1 Tw T2 Th CKIO A25 to A0 CSn WEn RD/WR RD Read D31 to D0 RD/WR High RD Write D31 to D0 BS DACKn* Note: * The waveform for DACKn is when active low is specified. Figure 12.39 Byte-Selection SRAM Wait Timing (BAS = 1) (SW[1:0] = 01, WR[3:0] = 0001, HW[1:0] = 01) Rev. 4.00 Sep.
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Section 12 Bus State Controller (BSC) 64k × 16-bit SRAM This LSI A17 ... ... A15 A2 A0 CSn CS RD OE RD/WR WE D31 ... ... I/O15 D16 I/O0 WE3 UB WE2 LB ... D15 ... A15 D0 WE1 A0 WE0 CS OE WE ... I/O15 I/O0 UB LB Figure 12.40 Example of Connection with 32-Bit Data-Width Byte-Selection SRAM 64k × 16-bit SRAM This LSI A16 A15 A1 A0 CSn CS RD RD/WR D15 D0 WE1 WE0 OE WE I/O 15 I/O 0 UB LB Figure 12.41 Example of Connection with 16-Bit Data-Width Byte-Selection SRAM Rev. 4.
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Section 12 Bus State Controller (BSC) 12.5.9 Burst MPX-I/O Interface Figure 12.42 shows an example of a connection between the LSI and an MPX device. Figures 12.43 to 12.46 show the burst MPX space access timings. Area 6 can be specified as the address/data multiplex I/O (MPX-I/O) interface using the TYPE2 to TYPE0 bits in the CS6BCR register. This MPX-I/O interface enables the LSI to be easily connected to an external memory controller chip that uses an address/data multiplexed 32-bit single bus.
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Section 12 Bus State Controller (BSC) Tm1 Tmd1w Tmd1 CKIO FRAME D31 to D0 A D A25 to A0 CS6B RD/WR WAIT BS DACKn* Note: * The waveform for DACKn is when active low is specified. Figure 12.43 Burst MPX Space Access Timing (Single Read, No Wait, or Software Wait 1) Rev. 4.00 Sep.
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Section 12 Bus State Controller (BSC) Tm1 Tmd1w Tmd1w Tmd1 CKIO FRAME D31 to D0 A D A25 to A0 CS6B RD/WR WAIT BS DACKn* Note: * The waveform for DACKn is when active low is specified. Figure 12.44 Burst MPX Space Access Timing (Single Write, Software Wait 1, Hardware Wait 1) Rev. 4.00 Sep.
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Section 12 Bus State Controller (BSC) Tm1 Tmd1w Tmd1 Tmd2 Tmd3 Tmd4 CKIO FRAME D31 to D0 A D0 D1 D2 D3 A25 to A0 CS6B RD/WR WAIT BS DACKn* Note: * The waveform for DACKn is when active low is specified. Figure 12.45 Burst MPX Space Access Timing (Burst Read, No Wait, or Software Wait 1, CS6BWCR.MPXMD = 0) Rev. 4.00 Sep.
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Section 12 Bus State Controller (BSC) Tm1 Tmd1 Tmd2 Tmd3 Tmd4 D1 D2 D3 CKIO FRAME D31 to D0 A D0 A25 to A0 CS6B RD/WR WAIT BS DACKn* Note: * The waveform for DACKn is when active low is specified. Figure 12.46 Burst MPX Space Access Timing (Burst Write, No Wait, CS6BWCR.MPXMD = 0) 12.5.10 Burst ROM Interface (Clock Synchronous) The burst ROM (clock synchronous) interface is supported to access a ROM with a synchronous burst function at high speed.
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Section 12 Bus State Controller (BSC) The burst ROM interface performs burst operations for all read accesses. For example, in a longword access over a 16-bit bus, valid 16-bit data is read two times and invalid 16-bit data is read six times. These invalid data read cycles increase the memory access time and degrade the program execution speed and DMA transfer speed. To prevent this problem, it is recommend using a 16-byte read by cache fill or 16-byte read by the DMAC.
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Section 12 Bus State Controller (BSC) 6. Data output from an external device caused by DMA single address transfer is followed by data output from another device that includes this LSI (DMAIWA = 0) For details, see the description of the DMAIWA bit in the CMNCR register. 7.
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Section 12 Bus State Controller (BSC) Tables 12.18 to 12.22 lists the minimum number of idle cycles to be inserted for the normal space interface and the SDRAM interface. The CSnBCR Idle Setting column in the tables describes the number of idle cycles to be set for IWW, IWRWD, IWRWS, IWRRD, and IWRRS. Table 12.18 Minimum Number of Idle Cycles between CPU Access Cycles for the Normal Space Interface When Access Size is Less than BSC Register Setting CSnWCR.
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Section 12 Bus State Controller (BSC) Table 12.19 Minimum Number of Idle Cycles between Access Cycles during DMAC Dual Address Mode Transfer for the Normal Space Interface BSC Register Setting When Access Size is Less than Bus Width When Access Size Exceeds Bus Width CSnWCR.
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Section 12 Bus State Controller (BSC) Table 12.20 Minimum Number of Idle Cycles during DMAC Single Address Mode Transfer to the Normal Space Interface from the External Device with DACK (1) Transfer from the external device with DACK to the normal space interface When Access Size is Less than Bus Width BSC Register Setting*3 CSnWCR.WM Setting CMNCR.DMAIWA CMNCR.
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Section 12 Bus State Controller (BSC) (2) Transfer from the normal space interface to the external device with DACK BSC Register Setting*4 When Access Size is Less than Bus Width CSnWCR.WM Setting CSnBCR Idle Setting Continuous Transfer*1 Non-Continuous Transfer*2 1 0 0 3 0 0 1 3 1 1 1 3 0 1 1 3 1 2 2 3 0 2 2 3 1 4 4 4 0 4 4 4 0, 1 n (n≥6) n n Notes: 1. 2. 3. 4. DMAC is operated by Bφ. The minimum number of idle cycles is not affected by changing a clock ratio.
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Section 12 Bus State Controller (BSC) Table 12.21 Minimum Number of Idle Cycles between Access Cycles of CPU and the DMAC Dual Address Mode for the SDRAM Interface BSC Register Setting CPU Access DMAC Access CSnBCR CS3WCR. CS3WCR.
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Section 12 Bus State Controller (BSC) BSC Register Setting CPU Access DMAC Access CSnBCR CS3WCR. CS3WCR.
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Section 12 Bus State Controller (BSC) BSC Register Setting CPU Access DMAC Access CSnBCR CS3WCR. CS3WCR.
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Section 12 Bus State Controller (BSC) Table 12.22 Minimum Number of Idle Cycles between Access Cycles of the DMAC Single Address Mode for the SDRAM Interface (1) Transfer from the external device with DACK to the SDRAM interface BSC Register Setting*2 CMNCR.DMAIW Setting CS3WCR.WTRP Setting CS3WCR.
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Section 12 Bus State Controller (BSC) BSC Register Setting*2 CMNCR.DMAIW Setting CS3WCR.WTRP Setting CS3WCR.
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Section 12 Bus State Controller (BSC) (2) Transfer from the SDRAM interface to the external device with DACK BSC Register Setting*2 CS3BCR Idle Setting CS3WCR.WTRP Setting Minimum Number of Idle Cycles 0 0 3 0 1 3 0 2 3 0 3 4 1 0 3 1 1 3 1 2 3 1 3 4 2 0 3 2 1 3 2 2 3 2 3 4 4 0 5 4 1 5 4 2 5 4 3 5 n (n>=6)  n+1 Notes: DMAC is operated by Bφ. The minimum number of idle cycles is not affected by changing a clock ratio. 1.
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Section 12 Bus State Controller (BSC) 12.5.12 Bus Arbitration The bus arbitration of this LSI has the bus mastership in the normal state and releases the bus mastership after receiving a bus request from another device. Bus mastership is transferred at the boundary of bus cycles. Namely, bus mastership is released immediately after receiving a bus request when a bus cycle is not being performed. The release of bus mastership is delayed until the bus cycle is complete when a bus cycle is in progress.
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Section 12 Bus State Controller (BSC) The sequence for reclaiming the bus mastership from an external device is described below. 1.5 cycles after the negation of BREQ is detected at the falling edge of CKIO, the bus control signals are driven high. The bus enable signal is negated at the next falling edge of the clock. The fastest timing at which actual bus cycles can be resumed after bus control signal assertion is at the rising edge of the CKIO where address and data signals are driven. Figure 12.
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Section 12 Bus State Controller (BSC) 12.5.13 Others Reset: The bus state controller (BSC) can be initialized completely only at power-on reset. When a power-on reset occurs, internal clocks are synchronized by the reset, then all signals are negated and output buffers are turned off regardless of the bus cycle state. All control registers are initialized. In standby, sleep, and manual reset, control registers of the bus state controller are not initialized.
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Section 12 Bus State Controller (BSC) If the CPU initiates read access for the cache, the cache is searched. If the cache stores data, the CPU latches the data and completes the read access. If the cache does not store data, the CPU performs four contiguous longword read cycles to perform cache fill operations via the internal bus.
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Section 12 Bus State Controller (BSC) DMA source and destination addresses exist in external memory space, the next write cycle will not be initiated until the previous write cycle is completed. If BSC registers are modified while the write buffer is functioning, correct access cannot be performed. Thus, do not modify BSC registers immediately after the writing has finished. If BSC registers need to be modified, modify the registers after dummy reading the write data.
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Section 12 Bus State Controller (BSC) Rev. 4.00 Sep.
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Section 13 Direct Memory Access Controller (DMAC) Section 13 Direct Memory Access Controller (DMAC) This LSI includes the direct memory access controller (DMAC). The DMAC can be used in place of the CPU to perform high-speed transfers between external devices that have DACK (transfer request acknowledge signal), external memory, on-chip memory, memory-mapped external devices, and on-chip peripheral modules. Figure 13.1 shows a block diagram of the DMAC. 13.
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Section 13 Direct Memory Access Controller (DMAC) • Transfer request acknowledge and transfer end signals: Active levels for DACK and TEND can be set independently. Figure 13.1 shows the block diagram of the DMAC.
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Section 13 Direct Memory Access Controller (DMAC) 13.2 Input/Output Pins The external pins for DMAC are described below. Table 13.1 lists the configuration of the pins that are connected to external bus. DMAC has pins for 2 channels (channels 0 and 1) for external bus use. Table 13.
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Section 13 Direct Memory Access Controller (DMAC) 13.3 Register Descriptions Register configuration is described below. See section 24, List of Registers, for the addresses of these registers and the state of them in each processing status.
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Section 13 Direct Memory Access Controller (DMAC) 13.3.1 DMA Source Address Registers (SAR) DMA source address registers (SAR) are 32-bit read/write registers that specify the source address of a DMA transfer. During a DMA transfer, these registers indicate the next source address. When the data of an external device with DACK is transferred in the single address mode, the SAR is ignored. To transfer data in 16 bits or in 32 bits, specify the address with 16-bit or 32-bit address boundary.
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Section 13 Direct Memory Access Controller (DMAC) 13.3.4 DMA Channel Control Registers (CHCR) DMA channel control registers (CHCR) are 32-bit read/write registers that control the DMA transfer mode. The CHCR is initialized to H'00000000 at reset and retains the current value in the standby or module standby mode.
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Section 13 Direct Memory Access Controller (DMAC) Bit Bit Name Initial Value R/W Descriptions 21 to 18  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 17 AM 0 R/W Acknowledge Mode AM specifies whether DACK is output in data read cycle or in data write cycle in dual address mode. In single address mode, DACK is always output regardless of the specification by this bit. This bit is valid only in CHCR_0 and CHCR_1.
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Section 13 Direct Memory Access Controller (DMAC) Bit Bit Name Initial Value R/W Descriptions 13 12 SM1 SM0 0 0 R/W R/W 11 10 9 8 RS3 RS2 RS1 RS0 0 0 0 0 R/W R/W R/W R/W Source Address Mode SM1 and SM0 select whether the DMA source address is incremented, decremented, or left fixed. (In single address mode, SM1 and SM0 bits are ignored when data is transferred from an external device with DACK.
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Section 13 Direct Memory Access Controller (DMAC) Bit Bit Name Initial Value R/W Descriptions 7 DL 0 R/W DREQ Level and DREQ Edge Select 6 DS 0 R/W These bits specify the sampling method of the DREQ pin input and the sampling level. These bits are valid only in CHCR_0 and CHCR_1. These bits are always read as 0 in CHCR_2 and CHCR_3. The write value should always be 0.
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Section 13 Direct Memory Access Controller (DMAC) Bit Bit Name Initial Value R/W Descriptions 2 IE 0 R/W Interrupt Enable This bit specifies whether or not an interrupt request is generated to the CPU at the end of the DMA transfer. Setting this bit to 1 generates an interrupt request (DEI) to the CPU when TE bit is set to 1. 0: Interrupt request is not generated 1: Interrupt request is generated 1 TE 0 R/W* Transfer End Flag This bit shows that DMA transfer ends.
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Section 13 Direct Memory Access Controller (DMAC) Bit Bit Name Initial Value R/W Descriptions 0 DE 0 R/W DMA Enable This bit enabler or disables the DMA transfer. In an auto request mode, DMA transfer starts by setting the DE bit and DME bit in DMAOR to 1. In this time, all of the bits TE, NMIF in DMAOR, and AE must be 0's.
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Section 13 Direct Memory Access Controller (DMAC) 13.3.5 DMA Operation Register (DMAOR) The DMA operation register (DMAOR) is a 32-bit read/write register that specifies the priority level of channels at the DMA transfer. This register shows the DMA transfer status. The DMAOR is initialized to H'00000000 at reset and retains the current value in the standby or module standby mode. Bit Bit Name Initial Value R/W Description 31, 30  All 0 R Reserved These bits are always read as 0.
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Section 13 Direct Memory Access Controller (DMAC) Bit Bit Name Initial Value R/W Description 25 PR1 0 R/W Priority Mode 1, 0 24 PR0 0 R/W PR1 and PR0 select the priority level between channels when there are transfer requests for multiple channels simultaneously. 00: Fixed mode 1: CH0 > CH1 > CH2 > CH3 01: Fixed mode 2: CH0 > CH2 > CH3 > CH1 10: The status of the channel select round-robin mode: RCn bit is reflected to the priority.
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Section 13 Direct Memory Access Controller (DMAC) Bit Bit Name Initial Value R/W Description 16 DME 0 R/W DMA Master Enable DME enables or disables DMA transfers on all channels. If the DME bit and the DE bit corresponding to each channel in CHCR are set to 1s, transfer is enabled in the corresponding channel. If this bit is cleared during transfer, transfers in all the channels can be terminated.
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Section 13 Direct Memory Access Controller (DMAC) If (PR1 and PR0) = (B'10) is specified, the channel priority is determined according to the settings of the round-robin select bits. In this case, the channel priority is changed between channels whose corresponding round-robin select bit is set to 1. If (PR1 and PR0) = (B'01) is specified, the channel priority is specified as fixed mode 2 (CH0 > CH2 > CH3 > CH1).
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Section 13 Direct Memory Access Controller (DMAC) Table 13.2 Combination of the Round-Robin Select Bits and Priority Mode Bits Round-robin Priority Level Transfer Select bit End Priority bit High Low Mode No. RC0 RC1 RC2 RC3 CH No.
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Section 13 Direct Memory Access Controller (DMAC) 13.3.6 DMA Extension Resource Selector 0 and 1 (DMARS0, DMARS1) DMARS is a 16-bit read/write register that specifies the DMA transfer sources from peripheral modules in each channel. DMARS0 specifies for channels 0 and 1, DMARS1 specifies for channels 2 and 3. This register can set the transfer request of SCIF0, SCIF1, SCIF2, MTU0, MTU1, MTU2, MTU3, MTU4, MTU, USB, A/D converter 1, and CMT1. This register is initialized to H'0000 by power-on manual reset.
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Section 13 Direct Memory Access Controller (DMAC) • DMARS1 Bit Bit Name Initial Value R/W Description 15 C3MID5 0 R/W 14 C3MID4 0 R/W Transfer request module ID for DMA channel 3 (MID). See table 13.3. 13 C3MID3 0 R/W 12 C3MID2 0 R/W 11 C3MID1 0 R/W 10 C3MID0 0 R/W 9 C3RID1 0 R/W 8 C3RID0 0 R/W 7 C2MID5 0 R/W 6 C2MID4 0 R/W 5 C2MID3 0 R/W 4 C2MID2 0 R/W 3 C2MID1 0 R/W 2 C2MID0 0 R/W 1 C2RID1 0 R/W 0 C2RID0 0 R/W Rev. 4.00 Sep.
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Section 13 Direct Memory Access Controller (DMAC) Transfer requests from the various modules are specified by the MID and RID as shown in table 13.3. Table 13.
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Section 13 Direct Memory Access Controller (DMAC) 13.4 Operation When there is a DMA transfer request, the DMAC starts the transfer according to the predetermined channel priority order; when the transfer end conditions are satisfied, it ends the transfer. Transfers can be requested in three modes: auto request, external request, and on-chip module request. The dual address mode has direct address transfer mode and indirect address transfer mode.
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Section 13 Direct Memory Access Controller (DMAC) Figure 13.2 is a flowchart of this procedure.
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Section 13 Direct Memory Access Controller (DMAC) 13.4.2 DMA Transfer Requests DMA transfer requests are basically generated in either the data transfer source or destination, but they can also be generated by devices and on-chip peripheral modules that are neither the source nor the destination. Transfers can be requested in three modes: auto request, external request, and on-chip module request.
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Section 13 Direct Memory Access Controller (DMAC) Table 13.5 Selecting External Request Detection with Dl, DS Bits CHCR DL 0 1 DS Detection of External Request 0 Low level detection 1 Falling edge detection 0 High level detection 1 Rising edge detection When DREQ is accepted, the DREQ pin becomes request accept disabled state (non-sensitive period). After issuing acknowledge signal DACK for the accepted DREQ, the DREQ pin again becomes request accept enabled state.
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Section 13 Direct Memory Access Controller (DMAC) On-Chip Peripheral Module Request: In this mode, the transfer is performed in response to the DMA transfer request signal of an on-chip peripheral module.
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Section 13 Direct Memory Access Controller (DMAC) CHCR DMARS RS[3:0] MID 1000 DMA Transfer Request RID Source Source Destination Bus Mode 101010 00 MTU0 TGI0A (input capture interrupt/ compare match interrupt) Any Any Burst/ cycle steal 110000 00 MTU1 TGI1A (input capture interrupt/ compare match interrupt) Any Any Burst/ cycle steal 110010 00 MTU2 TGI2A (input capture interrupt/ compare match interrupt) Any Any Burst/ cycle steal 110100 00 MTU3 TGI3A (input capture interrupt/ co
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Section 13 Direct Memory Access Controller (DMAC) These are selected by the PR1 and the PR0 bits in the DMA operation register (DMAOR). Round-Robin Mode: Each time one word, byte, or longword is transferred on one channel, the priority order is rotated. The channel on which the transfer was just finished rotates to the bottom of the priority order. The round-robin mode operation is shown in figure 13.3. The priority of the round-robin mode is CH0 > CH1 > CH2 > CH3 immediately after reset.
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Section 13 Direct Memory Access Controller (DMAC) Figure 13.4 shows how the priority order changes when channel 0 and channel 3 transfers are requested simultaneously and a channel 1 transfer is requested during the channel 0 transfer. The DMAC operates as follows: 1. Transfer requests are generated simultaneously to channels 0 and 3. 2. Channel 0 has a higher priority, so the channel 0 transfer begins first (channel 3 waits for transfer). 3.
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Section 13 Direct Memory Access Controller (DMAC) 13.4.4 DMA Transfer Types DMA transfer has two types; single address mode transfer and dual address mode transfer. They depend on the number of bus cycles of access to source and destination. A data transfer timing depends on the bus mode, which has cycle steal mode and burst mode. The DMAC supports the transfers shown in table 13.8. Table 13.
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Section 13 Direct Memory Access Controller (DMAC) Address Modes: 1. Dual Address Mode In the dual address mode, both the transfer source and destination are accessed (selected) by an address. The source and destination can be located externally or internally. DMA transfer requires two bus cycles because data is read from the transfer source in a data read cycle and written to the transfer destination in a data write cycle. At this time, transfer data is temporarily stored in the DMAC.
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Section 13 Direct Memory Access Controller (DMAC) Figure 13.6 shows an example of DMA transfer timing in dual address mode. CKIO A25 to A0 Transfer source address Transfer destination address CSn D31 to D0 RD WEn DACKn (Active-Low) Data read cycle Data write cycle (1st cycle) (2nd cycle) Note: In transfer between external memories, with DACK output in the read cycle, DACK output timing is the same as that of CSn. Figure 13.
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Section 13 Direct Memory Access Controller (DMAC) External address bus External data bus This LSI External memory DMAC External device with DACK DACK Data flow DREQ Figure 13.7 Data Flow in Single Address Mode Two kinds of transfer are possible in single address mode: (1) transfer between an external device with DACK and a memory-mapped external device, and (2) transfer between an external device with DACK and external memory.
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Section 13 Direct Memory Access Controller (DMAC) Figure 13.8 shows example of DMA transfer timing in single address mode.
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Section 13 Direct Memory Access Controller (DMAC) Figure 13.9 shows an example of DMA transfer timing in the cycle steal mode. Transfer conditions shown in the figure are: 1. Dual address mode 2. DREQ low level detection DREQ Bus mastership returned to CPU once Bus cycle CPU CPU CPU DMAC DMAC Read/Write CPU DMAC DMAC CPU Read/Write Figure 13.
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Section 13 Direct Memory Access Controller (DMAC) DREQ More than 16 or 64Bφ (change by the CPU's condition of using bus) Bus cycle CPU CPU CPU DMAC DMAC CPU CPU Read/Write DMAC DMAC CPU Read/Write Figure 13.10 Example of DMA Transfer in Cycle Steal Intermittent Mode (Dual Address, DREQ Low Level Detection) 2. Burst Mode Once the bus mastership is obtained, the transfer is performed continuously until the transfer end condition is satisfied.
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Section 13 Direct Memory Access Controller (DMAC) Table 13.
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Section 13 Direct Memory Access Controller (DMAC) Bus Mode and Channel Priority Order: When channel 1 is transferring data in burst mode and a request arrives for transfer on channel 0, which has higher-priority, the data transfer on channel 0 will begin immediately. In this case, if the transfer on channel 0 is also in burst mode, the transfer on channel 1 will only resume on completion of the transfer on channel 0.
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Section 13 Direct Memory Access Controller (DMAC) CKIO Bus cycle DREQ (Rising) CPU CPU DMAC 1st acceptance Non sensitive period CPU 2nd acceptance DACK (Active-high) Acceptance start Figure 13.
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Section 13 Direct Memory Access Controller (DMAC) CKIO Bus cycle DREQ (Rising) CPU CPU DMAC 1st acceptance 2nd acceptance Non sensitive period DACK (Active-high) Acceptance start CKIO Bus cycle DREQ (Overrun 1 at high level) CPU CPU 1st acceptance DMAC DMAC 2nd acceptance 3rd acceptance Non sensitive period DACK (Active-high) Acceptance start Acceptance start Figure 13.16 Example of DREQ Input Detection in Burst Mode Level Detection Figure 13.17 shows the TEND output timing.
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Section 13 Direct Memory Access Controller (DMAC) To execute a longword access to an 8-bit or 16-bit external device or to execute a word access to an 8-bit external device, the DACK and TEND outputs are divided for data alignment as shown in figure 13.18. T1 T2 Taw T1 T2 CKIO Address CSn RD Read D15 to D0 WEn Write D15 to D0 DACKn (Active low) TENDn (Active low) WAIT Note: TEND is asserted for the last transfer unit of DMA transfers.
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Section 13 Direct Memory Access Controller (DMAC) 13.4.6 Completion of DMA Transfer The conditions for the completion of DMA transfer differ according to whether we are considering completion of transfer on individual channels or simultaneous completion of transfer on all channels. 1. Conditions for the completion of transfer on individual channels Either of the following events indicates the completion of transfer on the corresponding channel.
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Section 13 Direct Memory Access Controller (DMAC) • When an address error occurs during a read cycle: Neither read cycles nor write cycles are generated; only the transfer request is cleared. However, when the transfer-request source was an on-chip peripheral module (MTU), use whichever of the following methods is appropriate to clear the transfer request. a. When the TC bit of CHCR is 1: Clear the corresponding flag to resume a transfer after address-error exception processing.
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Section 13 Direct Memory Access Controller (DMAC) 6. Note the followings when the DMA transfer request is sent from the SCIF. Even when the DMAC has completed the TCR times of transfers (the TE bit in CHCR = 1), the DMAC accepts and keeps the transfer request from the SCIF (max. one time of transfer) if all the conditions shown below are satisfied. The DMA transfer, however, is not executed because the TE bit is set to 1. Clearing the TE bit in this condition can immediately restart the transfer.
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Section 13 Direct Memory Access Controller (DMAC) • Idle cycles between read-read cycles in the same spaces (IWRRS = 01 or more) • External wait mask specification (WM = 0). In addition to the above conditions, the following conditions are included depending on the detection method of DREQ. • For DREQ level detection: only write access • For DREQ edge detection: both write access and read access Phenomenon: The detection timings of the DREQ pin in the above access are shown in figures 13.19 to 13.22.
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Section 13 Direct Memory Access Controller (DMAC) CKIO Bus cycle DREQ (Overrun 0, high-level) CPU DMAC write 3rd acceptance possible 1st acceptance 2nd acceptance Non-sensitive period Non-sensitive period DACK (High-active) CKIO Bus cycle DREQ (Overrun 1, high-level) DMAC write CPU 1st acceptance 2nd acceptance 3rd acceptance possible Non-sensitive period Non-sensitive period DACK (High-active) Figure 13.
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Section 13 Direct Memory Access Controller (DMAC) CKIO Bus cycle DREQ (Overrun 0, high-level) CPU DMAC write 1st acceptance 2nd acceptance 3rd acceptance possible Non-sensitive period Non-sensitive period DACK (High-active) CKIO Bus cycle DREQ (Overrun 1, high-level) CPU 1st acceptance DMAC write 2nd acceptance 3rd acceptance possible Non-sensitive period Non-sensitive period DACK (High-active) Figure 13.
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Section 13 Direct Memory Access Controller (DMAC) Rev. 4.00 Sep.
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Section 14 U Memory Section 14 U Memory This LSI has on-chip U memory. It can be used by the CPU, DSP, and DMAC to store instructions or data. 14.1 Features The U memory features are listed in table 14.1. Table 14.
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Section 14 U Memory 14.2 U Memory Access from CPU The U memory can be accessed by the CPU from spaces P0 and P2. Access from the CPU is via the I bus when U memory is space P0, and via the L bus when space P2. To use the L bus, one cycle access is performed unless page conflict occurs. Using the I bus takes more than one cycle.
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Section 14 U Memory 14.5 Usage Note When accessing the U memory by the CPU or the DSP, if the cache is on, access must be performed from space P2 (non-cacheable space). Operation during access from space P0 cannot be guaranteed. When the cache is off, spaces P0 and P2 can both be used. 14.6 Sleep Mode In sleep mode, the U memory cannot be accessed by the I bus master module such as DMAC. 14.
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Section 14 U Memory Rev. 4.00 Sep.
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Section 15 User Debugging Interface (H-UDI) Section 15 User Debugging Interface (H-UDI) This LSI incorporates a user debugging interface (H-UDI) and advanced user debugger (AUD) for a boundary scan function and emulator support. This section describes the H-UDI. The AUD is a function exclusively for use by an emulator. Refer to the User's Manual for the relevant emulator for details of the AUD. 15.
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Section 15 User Debugging Interface (H-UDI) 15.2 Input/Output Pins Table 15.1 shows the pin configuration of the H-UDI. Table 15.1 Pin Configuration Pin Name Input/Output Description TCK Input Serial data input/output clock pin Data is serially supplied to the H-UDI from the data input pin (TDI), and output from the data output pin (TDO), in synchronization with this clock.
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Section 15 User Debugging Interface (H-UDI) 15.3 Register Descriptions The H-UDI has the following registers. Refer the section 24, List of Registers, for the addresses and access size for these registers. • • • • Bypass register (SDBPR) Instruction register (SDIR) Boundary scan register (SDBSR) ID register (SDID) 15.3.1 Bypass Register (SDBPR) SDBPR is a 1-bit register that cannot be accessed by the CPU. When SDIR is set to the bypass mode, SDBPR is connected between H-UDI pins TDI and TDO.
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Section 15 User Debugging Interface (H-UDI) Table 15.
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Section 15 User Debugging Interface (H-UDI) Table 15.
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Section 15 User Debugging Interface (H-UDI) Bit Pin Name I/O Bit Pin Name I/O 424 DPLS/PTB8 OUT 392 CS3/PTA3 Control 423 A18 OUT 391 CS2/PTA2 Control 422 A19/PTA8 OUT 390 UCLK/PTB0 Control 421 A20/PTA9 OUT 389 VBUS/PTB1 Control 420 A21/PTA10 OUT 388 SUSPND/PTB2 Control 419 A22/PTA11 OUT 387 XVDATA/PTB3 Control 418 A23/PTA12 OUT 386 TXENL/PTB4 Control 417 A24/PTA13 OUT 385 TXDMNS/PTB5 Control 416 AUDCK OUT 384 TXDPLS/PTB6 Control 415 A25/PTA14 OU
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Section 15 User Debugging Interface (H-UDI) Bit Pin Name I/O Bit Pin Name I/O 360 IRQ7/PTJ7 Control 328 TCLKD/PTF8 IN 359 SCK0/PTH0 Control 327 TCLKC/PTF9 IN 358 CTS0/PTH1 IN 326 TCLKB/PTF10 IN 357 TxD0/PTH2 IN 325 TCLKA/PTF11 IN 356 RxD0/PTH3 IN 324 POE0/PTF12 IN 355 RTS0/PTH4 IN 323 POE1/PTF13 IN 354 SCK1/PTH5 IN 322 POE2/PTF14 IN 353 CTS1/PTH6 IN 321 POE3/PTF15 IN 352 TxD1/PTH7 IN 320 PTF0 IN 351 RxD1/PTH8 IN 319 PTF1 IN 350 RTS1/PTH9 I
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Section 15 User Debugging Interface (H-UDI) Bit Pin Name I/O Bit Pin Name I/O 296 CTS2/PTH11 OUT 264 PTF4 OUT 295 TxD2/PTH12 OUT 263 PTF5 OUT 294 RxD2/PTH13 OUT 262 PTF6 OUT 293 RTS2/PTH14 OUT 261 PTF7 OUT 292 TIOC4D/PTE0 OUT 260 PTG8 OUT 291 TIOC4C/PTE1 OUT 259 PTG9/SCL OUT 290 TIOC4B/PTE2 OUT 258 PTG10/SDA OUT 289 TIOC4A/PTE3 OUT 257 PTG11 OUT 288 TIOC3D/PTE4 OUT 256 PTG12 OUT 287 TIOC3B/PTE6 OUT 255 PTG13 OUT 286 TIOC3C/PTE5 OUT 254 C
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Section 15 User Debugging Interface (H-UDI) Bit Pin Name I/O Bit Pin Name I/O 232 TIOC2B/PTE8 Control 200 AN2/PTG2 IN 231 TIOC2A/PTE9 Control 199 AN3/PTG3 IN 230 TIOC1B/PTE10 Control 198 AN4/PTG4 IN 229 TIOC1A/PTE11 Control 197 AN5/PTG5 IN 228 TIOC0D/PTE12 Control 196 AN6/PTG6 IN 227 TIOC0C/PTE13 Control 195 AN7/PTG7 IN 226 TIOC0B/PTE14 Control 194 DREQ0/PTC9 IN 225 TIOC0A/PTE15 Control 193 DREQ1/PTC10 IN 224 TCLKD/PTF8 Control 192 STATUS0/PTC14 IN
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Section 15 User Debugging Interface (H-UDI) Bit Pin Name I/O Bit Pin Name I/O 168 D28/PTD12 IN 136 BREQ/PTC6 Control 167 D27/PTD11 IN 135 BACK/PTC7 Control 166 D26/PTD10 IN 134 ASEBRKAK/PTC13 Control 165 DREQ0/PTC9 OUT 133 CS6B/PTC4 Control 164 DREQ1/PTC10 OUT 132 CS6A/PTC3 Control 163 STATUS0/PTC14 OUT 131 CS5B/PTC2 Control 162 STATUS1/PTC15 OUT 130 CS5A/PTC1 Control 161 BREQ/PTC6 OUT 129 CS4/PTC0 Control 160 BACK/PTC7 OUT 128 CS0 Control 159 AS
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Section 15 User Debugging Interface (H-UDI) Bit Pin Name I/O Bit Pin Name I/O 104 RASU/PTA7 IN 72 RASL/PTA6 OUT 103 CKE/PTA1 IN 71 A17 OUT 102 CASL/PTA4 IN 70 A16 OUT 101 RASL/PTA6 IN 69 A15 OUT 100 A0/PTA0 IN 68 A14 OUT 99 D15 IN 67 A13 OUT 98 D14 IN 66 A12 OUT 97 D13 IN 65 A11 OUT 96 D12 IN 64 A10 OUT 95 D11 IN 63 A9 OUT 94 D10 IN 62 A8 OUT 93 D9 IN 61 A7 OUT 92 D8 IN 60 A6 OUT 91 D25/PTD9 OUT 59 A5 OUT 90 D24/PTD8
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Section 15 User Debugging Interface (H-UDI) Bit Pin Name I/O Bit Pin Name I/O 40 D20/PTD4 Control 19 A11 Control 39 D19/PTD3 Control 18 A10 Control 38 D18/PTD2 Control 17 A9 Control 37 D17/PTD1 Control 16 A8 Control 36 D16/PTD0 Control 15 A7 Control 35 RD/WR Control 14 A6 Control 34 WE0/DQMLL Control 13 A5 Control 33 WE1/DQMLU Control 12 A4 Control 32 CASU/PTA5 Control 11 A3 Control 31 WE3/DQMUU/AH Control 10 A2 Control 30 RASU/PTA7 Contro
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Section 15 User Debugging Interface (H-UDI) 15.3.4 ID Register (SDID) The ID register (SDID) is a 32-bit read-only register in which SDIDH and SDIDL are connected. Each register is a 16-bit that can be read by CPU. The IDCODE command is set from the H-UDI pin. This register can be read from the TDO when the TAP state is Shift-DR. Writing is disabled. Initial Value Bit Bit Name R/W 31 to 0 DID31 to DID0 H'0027200F R Description Device ID Device ID register that is stipulated by JTAG.
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Section 15 User Debugging Interface (H-UDI) 15.4 Operation 15.4.1 TAP Controller Figure 15.2 shows the internal states of the TAP controller. State transitions basically conform with the JTAG standard. 1 Test-logic-reset 0 0 Select-DR-scan Run-test/idle 1 1 Select-IR-scan 0 1 Capture-DR 0 Shift-DR 1 Capture-IR 0 0 Shift-IR 1 Exit1-DR Pause-DR 1 0 Exit1-IR 0 0 1 0 0 0 Pause-IR 1 Exit2-DR 1 Exit2-IR 1 Update-DR 1 0 Update-IR 1 0 0 Figure 15.
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Section 15 User Debugging Interface (H-UDI) 15.4.2 Reset Configuration Table 15.4 Reset Configuration ASEMD0*1 RESETP TRST Chip State H L L Normal reset and H-UDI reset H Normal reset H L L H L H-UDI reset only H Normal operation L Reset hold*2 H Normal reset L H-UDI reset only H Normal operation Notes: 1. Performs normal mode and ASE mode settings ASEMD0 = H, normal mode ASEMD0 = L, ASE mode 2.
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Section 15 User Debugging Interface (H-UDI) TCK TDO (when the H-UDI command is set) tTDOD TDO (when the boundary scan command is set) tTDOD Figure 15.3 H-UDI Data Transfer Timing 15.4.4 H-UDI Reset An H-UDI reset is executed by inputting an H-UDI reset assert command in SDIR. An H-UDI reset is of the same kind as a power-on reset. An H-UDI reset is released by inputting an H-UDI reset negate command.
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Section 15 User Debugging Interface (H-UDI) 15.5 Boundary Scan A command can be set in SDIR by the H-UDI to place the H-UDI pins in the boundary scan mode stipulated by JTAG. 15.5.1 Supported Instructions This LSI supports the three essential instructions defined in the JTAG standard (BYPASS, SAMPLE/PRELOAD, and EXTEST) and three option instructions (IDCODE, CLAMP, and HIGHZ). BYPASS: The BYPASS instruction is an essential standard instruction that operates the bypass register.
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Section 15 User Debugging Interface (H-UDI) EXTEST: This instruction is provided to test external circuitry when the this LSI is mounted on a printed circuit board. When this instruction is executed, output pins are used to output test data (previously set by the SAMPLE/PRELOAD instruction) from the boundary scan register to the printed circuit board, and input pins are used to latch test results into the boundary scan register from the printed circuit board.
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2 Section 16 I C Bus Interface 2 (IIC2) Section 16 I2C Bus Interface 2 (IIC2) The I2C bus interface 2 conforms to and provides a subset of the Philips I2C (Inter-IC) bus interface functions. However, the configuration of the registers that control the I2C bus differs partly from the Philips register configuration. Figure 16.1 shows a block diagram of the I2C bus interface 2. Figure 16.2 shows an example of I/O pin connections to external circuits. 16.
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2 Section 16 I C Bus Interface 2 (IIC2) Transfer clock generation circuit SCL Output control Transmission/ reception control circuit ICCR1 ICCR2 ICMR Internal data bus Noise canceler ICDRT SDA Output control ICDRS SAR Address comparator Noise canceler ICDRR NF2CYC Bus state decision circuit [Legend] ICCR1 : I2C bus control register 1 ICCR2 : I2C bus control register 2 ICMR : I2C bus mode register I2C bus status register ICSR : ICIER : I2C bus interrupt enable register ICDRT : I2C bus transmi
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2 Section 16 I C Bus Interface 2 (IIC2) VccQ* VccQ* SCL in SCL SCL SDA SDA SDA in (Master) SCL SDA SDA out SCL in SCL out SCL SDA SCL out SCL in SCL out SDA in SDA in SDA out SDA out (Slave 1) (Slave 2) I2C Note: * The bus power supply and this LSI's power supply (VccQ) must be switched ON or OFF simultaneously. Figure 16.2 External Circuit Connections of I/O Pins 16.2 Input/Output Pins Table 16.1 shows the pin configuration for the I2C bus interface 2. Table 16.
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2 Section 16 I C Bus Interface 2 (IIC2) 16.3 Register Descriptions The I2C bus interface 2 has the following registers: • • • • • • • • • • I2C bus control register 1 (ICCR1) I2C bus control register 2 (ICCR2) I2C bus mode register (ICMR) I2C bus interrupt enable register (ICIER) I2C bus status register (ICSR) I2C bus slave address register (SAR) I2C bus transmit data register (ICDRT) I2C bus receive data register (ICDRR) I2C bus shift register (ICDRS) NF2CYC register (NF2CYC) 16.3.
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2 Section 16 I C Bus Interface 2 (IIC2) Bit Bit Name Initial Value R/W Description 5 MST 0 R/W Master/Slave Select 4 TRS 0 R/W Transmit/Receive Select 2 In master mode with the I C bus format, when arbitration is lost, MST and TRS are both reset by hardware, causing a transition to slave receive mode. Modification of the TRS bit should be made between transfer frames.
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2 Section 16 I C Bus Interface 2 (IIC2) Table 16.2 Transfer Rate Bit 3 Bit 2 Bit 1 Bit 0 CKS3 CKS2 CKS1 CKS0 Clock 0 0 0 0 φ/28 179 kHz 357 kHz 589kHz 1 φ/40 125 kHz 250 kHz 413kHz 750kHz 825kHz 0 φ/48 104 kHz 208 kHz 344kHz 625kHz 688kHz 1 φ/64 78.1 kHz 156 kHz 258kHz 469KHz 516kHz 0 φ/80 62.5 kHz 125 kHz 206kHz 375kHz 413kHz 1 φ/100 50.0 kHz 100 kHz 165kHz 300kHz 330kHz 1 0 φ/112 44.6 kHz 89.3 kHz 147kHz 268kHz 295kHz 1 φ/128 39.1 kHz 78.
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2 Section 16 I C Bus Interface 2 (IIC2) 16.3.2 I2C Bus Control Register 2 (ICCR2) ICCR2 is an 8-bit readable/writable register that issues start/stop conditions, manipulates the SDA pin, monitors the SCL pin, and controls reset in the control part of the I2C bus interface 2. Bit Bit Name Initial Value R/W Description 7 BBSY 0 R/W Bus Busy 2 This bit enables to confirm whether the I C bus is occupied or released and to issue start/stop conditions in master mode.
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2 Section 16 I C Bus Interface 2 (IIC2) Bit Bit Name Initial Value R/W Description 4 SDAOP 1 R/W SDAO Write Protect This bit controls change of output level of the SDA pin by modifying the SDAO bit. To change the output level, clear SDAO and SDAOP to 0 or set SDAO to 1 and clear SDAOP to 0. This bit is always read as 1. 3 SCLO 1 R This bit monitors SCL output level. When SCLO is 1, SCL pin outputs high. When SCLO is 0, SCL pin outputs low.
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2 Section 16 I C Bus Interface 2 (IIC2) Bit Bit Name Initial Value R/W Description 5, 4  All 1  Reserved These bits are always read as 1. 3 BCWP 1 R/W BC Write Protect This bit controls the BC2 to BC0 modifications. When modifying BC2 to BC0, this bit should be cleared to 0. In clock synchronous serial mode, BC should not be modified. 0: When writing, values of BC2 to BC0 are set. 1: When reading, 1 is always read. When writing, settings of BC2 to BC0 are invalid.
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2 Section 16 I C Bus Interface 2 (IIC2) 16.3.4 I2C Bus Interrupt Enable Register (ICIER) ICIER is an 8-bit readable/writable register that enables or disables interrupt sources and acknowledge bits, sets acknowledge bits to be transferred, and confirms acknowledge bits received. ICIER is initialized to H'00 by a power-on reset.
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2 Section 16 I C Bus Interface 2 (IIC2) Bit Bit Name Initial Value R/W Description 3 STIE 0 R/W Stop Condition Detection Interrupt Enable This bit enables or disables the stop condition (STPI) when the STOP bit in ICSR is set . 0: Stop condition detection interrupt request (STPI) is disabled. 1: Stop condition detection interrupt request (STPI) is enabled.
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2 Section 16 I C Bus Interface 2 (IIC2) 16.3.5 I2C Bus Status Register (ICSR) ICSR is an 8-bit readable/writable register that confirms interrupt request flags and their status. ICSR is initialized to H'00 by a power-on reset.
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2 Section 16 I C Bus Interface 2 (IIC2) Bit Bit Name Initial Value R/W Description 4 NACKF 0 R/W No Acknowledge Detection Flag [Setting condition] • When no acknowledge is detected from the receive device in transmission while the ACKE bit in ICIER is 1 [Clearing condition] • 3 STOP 0 R/W When 0 is written in NACKF after reading NACKF =1 Stop Condition Detection Flag [Setting condition] • When a stop condition is detected after frame transfer [Clearing condition] • 2 AL/OVE 0 R/W Whe
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2 Section 16 I C Bus Interface 2 (IIC2) Bit Bit Name Initial Value R/W Description 1 AAS 0 R/W Slave Address Recognition Flag In slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits SVA6 to SVA0 in SAR. [Setting conditions] • When the slave address is detected in slave receive mode • When the general call address is detected in slave receive mode.
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2 Section 16 I C Bus Interface 2 (IIC2) 16.3.7 I2C Bus Transmit Data Register (ICDRT) ICDRT is an 8-bit readable/writable register that stores the transmit data. When ICDRT detects the space in the shift register (ICDRS), it transfers the transmit data which is written in ICDRT to ICDRS and starts transferring data. If the next transfer data is written to ICDRT during transferring data of ICDRS, continuous transfer is possible. 16.3.
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2 Section 16 I C Bus Interface 2 (IIC2) 16.4 Operation The I2C bus interface can communicate either in I2C bus mode or clocked synchronous serial mode by setting FS in SAR. 16.4.1 I2C Bus Format Figure 16.3 shows the I2C bus formats. Figure 16.4 shows the I2C bus timing. The first frame following a start condition always consists of eight bits.
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2 Section 16 I C Bus Interface 2 (IIC2) [Legend] S: Start condition. The master device drives SDA from high to low while SCL is high. SLA: Slave address R/W: Indicates the direction of data transfer: from the slave device to the master device when R/W is 1, or from the master device to the slave device when R/W is 0. A: Acknowledge. The receive device drives SDA to low. DATA: Transfer data P: Stop condition. The master device drives SDA from low to high while SCL is high. 16.4.
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2 Section 16 I C Bus Interface 2 (IIC2) SCL (Master output) 1 2 3 4 5 6 SDA (Master output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 7 8 Bit 1 Slave address 9 1 Bit 0 Bit 7 2 Bit 6 R/W SDA (Slave output) A TDRE TEND Address + R/W ICDRT ICDRS User processing Data 1 Address + R/W [2] Instruction of start condition issuance Data 2 Data 1 [4] Write data to ICDRT (second byte) [5] Write data to ICDRT (third byte) [3] Write data to ICDRT (first byte) Figure 16.
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2 Section 16 I C Bus Interface 2 (IIC2) 16.4.3 Master Receive Operation In master receive mode, the master device outputs the receive clock, receives data from the slave device, and returns an acknowledge signal. For master receive mode operation timing, refer to figures 16.7 and 16.8. The reception procedure and operations in master receive mode are shown below. 1. Clear the TEND bit in ICSR to 0, then clear the TRS bit in ICCR1 to 0 to switch from master transmit mode to master receive mode.
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2 Section 16 I C Bus Interface 2 (IIC2) Master transmit mode SCL (Master output) Master receive mode 9 1 2 3 4 5 6 7 8 SDA (Master output) 9 1 A SDA (Slave output) A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 TDRE TEND TRS RDRF ICDRS Data 1 ICDRR User processing Data 1 [3] Read ICDRR [1] Clear TDRE after clearing TEND and TRS [2] Read ICDRR (dummy read) Figure 16.7 Master Receive Mode Operation Timing (1) Rev. 4.00 Sep.
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2 Section 16 I C Bus Interface 2 (IIC2) SCL (Master output) 9 SDA (Master output) A SDA (Slave output) 1 2 3 4 5 6 7 8 9 A/A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RDRF RCVD ICDRS Data n Data n-1 ICDRR Data n Data n-1 User processing [5] Read ICDRR after setting RCVD [7] Read ICDRR, and clear RCVD [6] Issue stop condition [8] Set slave receive mode Figure 16.8 Master Receive Mode Operation Timing (2) 16.4.
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2 Section 16 I C Bus Interface 2 (IIC2) 5. Clear TDRE. Slave receive mode Slave transmit mode SCL (Master output) 9 1 2 3 4 5 6 7 8 9 SDA (Master output) 1 A SCL (Slave output) SDA (Slave output) A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 TDRE TEND TRS Data 1 ICDRT ICDRS Data 2 Data 1 Data 3 Data 2 ICDRR User processing [2] Write data to ICDRT (data 1) [2] Write data to ICDRT (data 2) [2] Write data to ICDRT (data 3) Figure 16.
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2 Section 16 I C Bus Interface 2 (IIC2) Slave receive mode Slave transmit mode SCL (Master output) 9 SDA (Master output) A 1 2 3 4 5 6 7 8 9 A SCL (Slave output) SDA (Slave output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TDRE TEND TRS ICDRT ICDRS Data n ICDRR User processing [3] Clear TEND [4] Read ICDRR (dummy read) after clearing TRS [5] Clear TDRE Figure 16.10 Slave Transmit Mode Operation Timing (2) Rev. 4.00 Sep.
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2 Section 16 I C Bus Interface 2 (IIC2) 16.4.5 Slave Receive Operation In slave receive mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. For slave receive mode operation timing, refer to figures 16.11 and 16.12. The reception procedure and operations in slave receive mode are described below. 1. Set the ICE bit in ICCR1 to 1. Set the MLS and WAIT bits in ICMR and bits CKS3 to CKS0 in ICCR1 to 1.
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2 Section 16 I C Bus Interface 2 (IIC2) SCL (Master output) 9 SDA (Master output) 1 2 3 4 5 6 7 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 9 SCL (Slave output) SDA (Slave output) A A RDRF ICDRS Data 2 Data 1 ICDRR Data 1 User processing [3] Set ACKBT [3] Read ICDRR [4] Read ICDRR Figure 16.12 Slave Receive Mode Operation Timing (2) 16.4.
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2 Section 16 I C Bus Interface 2 (IIC2) Transmit Operation: In transmit mode, transmit data is output from SDA, in synchronization with the fall of the transfer clock. The transfer clock is output when MST in ICCR1 is 1, and is input when MST is 0. For transmit mode operation timing, refer to figure 16.14. The transmission procedure and operations in transmit mode are described below. 1. Set the ICE bit in ICCR1 to 1. Set the MST and CKS3 to CKS0 bits in ICCR1 to 1. (Initial setting) 2.
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2 Section 16 I C Bus Interface 2 (IIC2) Receive Operation: In receive mode, data is latched at the rise of the transfer clock. The transfer clock is output when MST in ICCR1 is 1, and is input when MST is 0. For receive mode operation timing, refer to figure 16.15. The reception procedure and operations in receive mode are described below. 1. Set the ICE bit in ICCR1 to 1. Set the MST and CKS3 to CKS0 bits in ICCR1 to 1. (Initial setting) 2.
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2 Section 16 I C Bus Interface 2 (IIC2) SCL 1 2 7 8 1 7 8 1 2 SDA (Input) Bit 0 Bit 1 Bit 6 Bit 7 Bit 0 Bit 6 Bit 7 Bit 0 Bit 1 MST TRS RDRF Data 2 Data 1 ICDRS Data 2 Data 1 ICDRR User processing Data 3 [2] Set MST (when outputting the clock) [3] Read ICDRR [3] Read ICDRR Figure 16.
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2 Section 16 I C Bus Interface 2 (IIC2) 16.4.7 Noise Filter The logic levels at the SCL and SDA pins are routed through noise filters before being latched internally. Figure 16.17 shows a block diagram of the noise filter circuit. The noise filter consists of three cascaded latches and a match detector. The SCL (or SDA) input signal is sampled on the system clock. When NF2CYC is set to 0, this signal is not passed forward to the next circuit unless the outputs of both latches agree.
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2 Section 16 I C Bus Interface 2 (IIC2) 16.4.8 Example of Use Flowcharts in respective modes that use the I2C bus interface are shown in figures 16.18 to 16.21. Start Initialize Read BBSY in ICCR2 [1] Test the status of the SCL and SDA lines. [2] Set master transmit mode. [3] Issue the start candition. [1] No BBSY=0 ? Yes Set MST and TRS in ICCR1 to 1 [2] [4] Set the first byte (slave address + R/W) of transmit data. Write 1 to BBSY and 0 to SCP [3] [5] Wait for 1 byte to be transmitted.
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2 Section 16 I C Bus Interface 2 (IIC2) Mater receive mode [1] Clear TEND, select master receive mode, and then clear TDRE. [2] Set acknowledge to the transmit device. [3] Dummy-read ICDDR. [4] Wait for 1 byte to be received [5] Check whether it is the (last receive - 1). [6] Read the receive data last. [7] Set acknowledge of the final byte. Disable continuous reception (RCVD = 1). [8] Read the (final byte - 1) of received data. [9] Wait for the last byte to be receive.
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2 Section 16 I C Bus Interface 2 (IIC2) [1] Clear the AAS flag. Slave transmit mode Clear AAS in ICSR [1] Write transmit data in ICDRT [2] [3] Wait for ICDRT empty. [4] Set the last byte of transmit data. Read TDRE in ICSR [5] Wait for the last byte to be transmitted. [3] No TDRE=1 ? Yes Yes [6] Clear the TEND flag . [7] Set slave receive mode. Last byte? No [2] Set transmit data for ICDRT (except for the last byte). [8] Dummy-read ICDRR to release the SCL line.
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2 Section 16 I C Bus Interface 2 (IIC2) Slave receive mode [1] Clear the AAS flag. Clear AAS in ICSR [1] Clear ACKBT in ICIER to 0 [2] Dummy-read ICDRR [3] [2] Set acknowledge to the transmit device. [3] Dummy-read ICDRR. [5] Check whether it is the (last receive - 1). Read RDRF in ICSR No [4] RDRF=1 ? [6] Read the receive data. [7] Set acknowledge of the last byte. Yes Last receive - 1? [4] Wait for 1 byte to be received.
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2 Section 16 I C Bus Interface 2 (IIC2) 16.5 Interrupt Request There are six interrupt requests in this module; transmit data empty, transmit end, receive data full, NACK receive, STOP recognition, and arbitration lost/overrun error. Table 16.3 shows the contents of each interrupt request. Table 16.
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2 Section 16 I C Bus Interface 2 (IIC2) 16.6 Bit Synchronous Circuit In master mode, this module has a possibility that high level period may be short in the two states described below. • When SCL is driven to low by the slave device • When the rising speed of SCL is lowered by the load of the SCL line (load capacitance or pullup resistance) Therefore, it monitors SCL and communicates by bit with synchronization. Figure 16.22 shows the timing of the bit synchronous circuit and table 16.
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2 Section 16 I C Bus Interface 2 (IIC2) 16.7 Usage Note Start (retransmission) and stop conditions should be generated after the fall of the ninth clock pulse has been detected. To detect the fall of the ninth clock pulse, read the SCLO bit in the I2C Bus Control Register 2 (ICCR2). When the start (retransmission) or stop condition is attempt to be generated at the specific timing under the following two conditions, the start or stop condition may not be generated normally.
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Section 17 Compare Match Timer (CMT) Section 17 Compare Match Timer (CMT) This LSI has an on-chip compare match timer (CMT) consisting of a two-channel 16-bit timer. The CMT has a16-bit counter, and can generate interrupts at set intervals. 17.1 Features CMT has the following features. • Selection of four counter input clocks  Any of four internal clocks (Pφ/4, Pφ/8, Pφ/16, and Pφ/64) can be selected independently for each channel.
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Section 17 Compare Match Timer (CMT) 17.2 Register Descriptions The CMT has the following registers. Refer the section 24, List of Registers and access size for these registers.
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Section 17 Compare Match Timer (CMT) 17.2.2 Compare Match Timer Control/Status Register (CMCSR) CMCSR is a 16-bit register that indicates compare match generation, enables interrupts or DMA transfer requests, and selects the counter input clock. CMCSR is initialized to H'0000 by a power on reset, but is not initialized in standby mode. Bit Bit Name Initial value R/W 15 to 8  All 0 R Description Reserved These bits are always read as 0. The write value should always be 0.
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Section 17 Compare Match Timer (CMT) Bit Bit Name Initial value R/W Description 1 CKS1 0 R/W Clock Select 0 CKS0 0 R/W These bits select the clock to be input to CMCNT from four internal clocks obtained by dividing the peripheral operating clock (Pφ). When the STR bit in CMSTR is set to 1, CMCNT starts counting on the clock selected with bits CKS1 and CKS0. 00: Pφ/4 01: Pφ/8 10: Pφ/16 11: Pφ/64 Note: 17.2.3 * Only 0 can be written, to clear the flag.
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Section 17 Compare Match Timer (CMT) 17.3 Operation 17.3.1 Interval Count Operation When an internal clock is selected with the CKS1 and CKS0 bits in CMCSR and the STR bit in CMSTR is set to 1, CMCNT starts incrementing using the selected clock. When the values in CMCNT and CMCOR match, CMCNT is cleared to H'0000 and the CMF flag in CMCSR is set to 1. CMCNT then starts counting up again from H'0000. Figure 17.2 shows the operation of the compare match counter.
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Section 17 Compare Match Timer (CMT) 17.4 Compare Matches 17.4.1 Timing of Compare Match Flag Setting When CMCOR and CMCNT match, a compare match signal is generated and the CMF bit in CMCSR is set to 1. The compare match signal is generated in the last state in which the values match (when the CMCNT value is updated to H'0000). That is, after a match between CMCOR and CMCNT, the compare match signal is not generated until the next CMCNT counter clock input. Figure 17.
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Section 17 Compare Match Timer (CMT) 17.4.3 Timing of Compare Match Flag Clearing The CMF bit in CMCSR is cleared by first, reading as 1 then writing to 0. Rev. 4.00 Sep.
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Section 17 Compare Match Timer (CMT) Rev. 4.00 Sep.
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Section 18 Multi-Function Timer Pulse Unit (MTU) Section 18 Multi-Function Timer Pulse Unit (MTU) This LSI has an on-chip multi-function timer pulse unit (MTU) that comprises five 16-bit timer channels. The block diagram is shown in figure 18.1. 18.
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Section 18 Multi-Function Timer Pulse Unit (MTU) Table 18.
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Section 18 Multi-Function Timer Pulse Unit (MTU) Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 DMA activation TGRA_0 compare match or input capture TGRA_1 compare match or input capture TGRA_2 compare match or input capture TGRA_3 compare match or input capture TGRA_4 compare match or input capture A/D converter start trigger TGRA_0 compare match or input capture TGRA_1 compare match or input capture TGRA_2 compare match or input capture TGRA_3 compare match or input capture TGRA_
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TGRB TGRC TGRD TGRB TGRC TGRD TCBR TDDR TCNT TGRA TCNT TGRA TCNTS DMA transfer request signal Channel 0: TGI3A Channel 1: TGI4A BUS I/F TGRD TGRB TGRB TGRB Interrupt request signals Channel 0:TGI0A TGI0B TGI0C TGI0D TCI0V Channel 1:TGI1A TGI1B TCI1V TCI1U Channel 2:TGI2A TGI2B TCI2V TCI2U TGRC TCNT TGRA TCNT TGRA TCNT TGRA A/D converter conversion start signal REJ09B0023-0400 DMA transfer request signal Channel 0: TGI0A Channel 1: TGI1A Channel 2: TGI2A TIER: Timer interrupt enabl
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Section 18 Multi-Function Timer Pulse Unit (MTU) 18.2 Input/Output Pins Table 18.
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Section 18 Multi-Function Timer Pulse Unit (MTU) 18.3 Register Descriptions The MTU has the following registers. To distinguish registers in each channel, TCR for channel 0 is expressed as TCR_0.
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Section 18 Multi-Function Timer Pulse Unit (MTU) • • • • • • • • • • • • • • • • • • • Timer I/O control register L_3 (TIORL_3) Timer interrupt enable register_3 (TIER_3) Timer status register_3 (TSR_3) Timer counter_3 (TCNT_3) Timer general register A_3 (TGRA_3) Timer general register B_3 (TGRB_3) Timer general register C_3 (TGRC_3) Timer general register D_3 (TGRD_3) Timer control register_4 (TCR_4) Timer mode register_4 (TMDR_4) Timer I/O control register H_4 (TIORH_4) Timer I/O control register L_4 (T
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Section 18 Multi-Function Timer Pulse Unit (MTU) 18.3.1 Timer Control Register (TCR) The TCR registers are 8-bit readable/writable registers that control the TCNT operation for each channel. The MTU has a total of five TCR registers, one for each channel (channel 0 to 4). TCR register settings should be conducted only when TCNT operation is stopped.
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Section 18 Multi-Function Timer Pulse Unit (MTU) Table 18.
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Section 18 Multi-Function Timer Pulse Unit (MTU) Table 18.5 TPSC0 to TPSC2 (Channel 0) Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 Description 0 0 0 0 Internal clock: counts on Pφ/1 1 Internal clock: counts on Pφ/4 0 Internal clock: counts on Pφ/16 1 Internal clock: counts on Pφ/64 0 External clock: counts on TCLKA pin input 1 External clock: counts on TCLKB pin input 1 1 0 1 0 External clock: counts on TCLKC pin input 1 External clock: counts on TCLKD pin input Table 18.
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Section 18 Multi-Function Timer Pulse Unit (MTU) Table 18.
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Section 18 Multi-Function Timer Pulse Unit (MTU) 18.3.2 Timer Mode Register (TMDR) The TMDR registers are 8-bit readable/writable registers that are used to set the operating mode of each channel. The MTU has five TMDR registers, one for each channel. TMDR register settings should be changed only when TCNT operation is stopped. Bit Bit Name Initial value R/W Description 7, 6  All 1  Reserved These bits are always read as 1. The write value should always be 1.
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Section 18 Multi-Function Timer Pulse Unit (MTU) Table 18.
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Section 18 Multi-Function Timer Pulse Unit (MTU) 18.3.3 Timer I/O Control Register (TIOR) The TIOR registers are 8-bit readable/writable registers that control the TGR registers. The MTU has eight TIOR registers, two each for channels 0, 3, and 4, and one each for channels 1 and 2. Care is required as TIOR is affected by the TMDR setting. The initial output specified by TIOR is valid when the counter is stopped (the CST bit in TSTR is cleared to 0).
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Section 18 Multi-Function Timer Pulse Unit (MTU) • TIORL_0, TIORL_3, TIORL_4 Bit Bit Name Initial value R/W Description 7 IOD3 0 R/W I/O Control D3 to D0 6 IOD2 0 R/W Specify the function of TGRD. 5 IOD1 0 R/W 4 IOD0 0 R/W When TGRD is used as the buffer register of TGRB, this setting is disabled, and input capture/output compare does not occur. See the following tables. TIORL_0: Table 18.11 TIORL_3: Table 18.15 TIORL_4: Table 18.
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Section 18 Multi-Function Timer Pulse Unit (MTU) Table 18.
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Section 18 Multi-Function Timer Pulse Unit (MTU) Table 18.
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Section 18 Multi-Function Timer Pulse Unit (MTU) Table 18.
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Section 18 Multi-Function Timer Pulse Unit (MTU) Table 18.
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Section 18 Multi-Function Timer Pulse Unit (MTU) Table 18.
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Section 18 Multi-Function Timer Pulse Unit (MTU) Table 18.
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Section 18 Multi-Function Timer Pulse Unit (MTU) Table 18.
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Section 18 Multi-Function Timer Pulse Unit (MTU) Table 18.
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Section 18 Multi-Function Timer Pulse Unit (MTU) Table 18.
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Section 18 Multi-Function Timer Pulse Unit (MTU) Table 18.
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Section 18 Multi-Function Timer Pulse Unit (MTU) Table 18.
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Section 18 Multi-Function Timer Pulse Unit (MTU) Table 18.
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Section 18 Multi-Function Timer Pulse Unit (MTU) Table 18.
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Section 18 Multi-Function Timer Pulse Unit (MTU) Table 18.
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Section 18 Multi-Function Timer Pulse Unit (MTU) Table 18.
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Section 18 Multi-Function Timer Pulse Unit (MTU) Table 18.
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Section 18 Multi-Function Timer Pulse Unit (MTU) 18.3.4 Timer Interrupt Enable Register (TIER) The TIER registers are 8-bit readable/writable registers that control enabling or disabling of interrupt requests for each channel. The MTU has five TIER registers, one for each channel. Bit Bit Name Initial value R/W Description 7 TTGE 0 R/W A/D Conversion Start Request Enable Enables or disables generation of A/D conversion start requests by TGRA input capture/compare match.
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Section 18 Multi-Function Timer Pulse Unit (MTU) Bit Bit Name Initial value R/W Description 3 TGIED 0 R/W TGR Interrupt Enable D Enables or disables interrupt requests (TGID) by the TGFD bit when the TGFD bit in TSR is set to 1 in channels 0, 3, and 4. In channels 1 and 2, bit 3 is reserved. It is always read as 0, and should only be written with 0.
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Section 18 Multi-Function Timer Pulse Unit (MTU) 18.3.5 Timer Status Register (TSR) The TSR registers are 8-bit readable/writable registers that indicate the status of each channel. The MTU has five TSR registers, one for each channel. Bit Bit Name Initial value R/W Description 7 TCFD 1 R Count Direction Flag Status flag that shows the direction in which TCNT counts in channels 1, 2, 3, and 4. In channel 0, bit 7 is reserved. It is always read as 1, and should only be written with 1.
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Section 18 Multi-Function Timer Pulse Unit (MTU) Bit Bit Name Initial value R/W 4 TCFV 0 R/(W) Overflow Flag Description Status flag that indicates that TCNT overflow has occurred. Only 0 can be written, for flag clearing. [Setting conditions] • When the TCNT value overflows (changes from H'FFFF to H'0000 ) • In channel 4, when TCNT_4 is underflowed (H'0001 → H'0000) in complementary PWM mode.
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Section 18 Multi-Function Timer Pulse Unit (MTU) Bit Bit Name Initial value R/W 2 TGFC 0 R/(W) Input Capture/Output Compare Flag C Description Status flag that indicates the occurrence of TGRC input capture or compare match in channels 0, 3, and 4. Only 0 can be written, for flag clearing. In channels 1 and 2, bit 2 is reserved. It is always read as 0, and should only be written with 0.
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Section 18 Multi-Function Timer Pulse Unit (MTU) Bit Bit Name Initial value R/W 0 TGFA 0 R/(W) Input Capture/Output Compare Flag A Description Status flag that indicates the occurrence of TGRA input capture or compare match. Only 0 can be written, for flag clearing.
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Section 18 Multi-Function Timer Pulse Unit (MTU) 18.3.8 Timer Start Register (TSTR) TSTR is an 8-bit readable/writable register that selects operation/stoppage for channels 0 to 4. When setting the operating mode in TMDR or setting the count clock in TCR, first stop the TCNT counter. Bit Bit Name Initial value R/W Description 7 CST4 0 R/W Counter Start 4 and 3 6 CST3 0 R/W These bits select operation or stoppage for TCNT.
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Section 18 Multi-Function Timer Pulse Unit (MTU) Bit Bit Name Initial value R/W Description 7 SYNC4 0 R/W Timer Synchro 4 and 3 6 SYNC3 0 R/W These bits are used to select whether operation is independent of or synchronized with other channels. When synchronous operation is selected, the TCNT synchronous presetting of multiple channels, and synchronous clearing by counter clearing on another channel, are possible.
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Section 18 Multi-Function Timer Pulse Unit (MTU) 18.3.10 Timer Output Master Enable Register (TOER) TOER is an 8-bit readable/writable register that enables/disables output settings for output pins TIOC4D, TIOC4C, TIOC3D, TIOC4B, TIOC4A, and TIOC3B. These pins do not output correctly if the TOER bits have not been set. Set TOER of CH3 and CH4 prior to setting TIOR of CH3 and CH4. Bit Bit Name Initial value R/W Description 7, 6  All 1 R Reserved These bits are always read as 1.
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Section 18 Multi-Function Timer Pulse Unit (MTU) 18.3.11 Timer Output Control Register (TOCR) TOCR is an 8-bit readable/writable register that enables/disables PWM synchronized toggle output in complementary PWM mode/reset synchronized PWM mode, and controls output level inversion of PWM output. Bit Bit Name Initial value R/W 7  0 R Description Reserved This bit is always read as 0. The write value should always be 0.
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Section 18 Multi-Function Timer Pulse Unit (MTU) Table 18.27 Output Level Select Function Bit 1 Function Compare Match Output OLSP Initial Output Active Level 0 High level Low level Low level High level 1 Low level High level High level Low level Increment Count Decrement Count Figure 18.2 shows an example of complementary PWM mode output (one phase) when OLSN = 1, OLSP = 1.
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Section 18 Multi-Function Timer Pulse Unit (MTU) 18.3.12 Timer Gate Control Register (TGCR) TGCR is an 8-bit readable/writable register that controls the waveform output necessary for brushless DC motor control in reset-synchronized PWM mode/complementary PWM mode. These register settings are ineffective for anything other than complementary PWM mode/resetsynchronized PWM mode. Bit Bit Name Initial value R/W Description 7  1 R Reserved This bit is always read as 1.
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Section 18 Multi-Function Timer Pulse Unit (MTU) Bit Bit Name Initial value R/W Description 3 FB 0 R/W External Feedback Signal Enable This bit selects whether the switching of the output of the positive/reverse phase is carried out automatically with the MTU/channel 0 TGRA, TGRB, TGRC input capture signals or by writing 0 or 1 to bits 2 to 0 in TGCR.
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Section 18 Multi-Function Timer Pulse Unit (MTU) 18.3.13 Timer Subcounter (TCNTS) TCNTS is a 16-bit read-only counter that is used only in complementary PWM mode. Note: Accessing TCNTS in 8-bit units is prohibited. Always access in 16-bit units. 18.3.14 Timer Dead Time Data Register (TDDR) TDDR is a 16-bit register, used only in complementary PWM mode, that specifies the TCNT_3 and TCNT_4 counter offset values.
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Section 18 Multi-Function Timer Pulse Unit (MTU) 18.3.17 Bus Master Interface The timer counters (TCNT), general registers (TGR), timer subcounter (TCNTS), timer period buffer register (TCBR), and timer dead time data register (TDDR), and timer period data register (TCDR) are 16-bit registers. A 16-bit data bus to the bus master enables 16-bit read/writes. 8-bit read/write is not possible. Always access in 16-bit units. All registers other than the above registers are 8-bit registers.
PAGE 613
Section 18 Multi-Function Timer Pulse Unit (MTU) Example of Count Operation Setting Procedure: Figure 18.3 shows an example of the count operation setting procedure. Operation selection Select counter clock Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR. [2] For periodic counter operation, select the TGR to be used as the TCNT clearing source with bits CCLR2 to CCLR0 in TCR.
PAGE 614
Section 18 Multi-Function Timer Pulse Unit (MTU) TCNT value H'FFFF H'0000 Time CST bit TCFV Figure 18.4 Free-Running Counter Operation When compare match is selected as the TCNT clearing source, the TCNT counter for the relevant channel performs periodic count operation. The TGR register for setting the period is designated as an output compare register, and counter clearing by compare match is selected by means of bits CCLR0 to CCLR2 in TCR.
PAGE 615
Section 18 Multi-Function Timer Pulse Unit (MTU) Example of Setting Procedure for Waveform Output by Compare Match: Figure 18.6 shows an example of the setting procedure for waveform output by compare match Output selection Select waveform output mode [1] Set output timing [2] Start count operation [3] [1] Select initial value 0 output or 1 output, and compare match output value 0 output, 1 output, or toggle output, by means of TIOR.
PAGE 616
Section 18 Multi-Function Timer Pulse Unit (MTU) Figure 18.8 shows an example of toggle output. In this example, TCNT has been designated as a periodic counter (with counter clearing on compare match B), and settings have been made such that the output is toggled by both compare match A and compare match B. TCNT value Counter cleared by TGRB compare match H'FFFF TGRB TGRA Time H'0000 TIOCB Toggle output TIOCA Toggle output Figure 18.
PAGE 617
Section 18 Multi-Function Timer Pulse Unit (MTU) Example of Input Capture Operation Setting Procedure: Figure 18.9 shows an example of the input capture operation setting procedure. Input selection Select input capture input [1] Start count [2] [1] Designate TGR as an input capture register by means of TIOR, and select rising edge, falling edge, or both edges as the input capture source and input signal edge. [2] Set the CST bit in TSTR to 1 to start the count operation.
PAGE 618
Section 18 Multi-Function Timer Pulse Unit (MTU) Counter cleared by TIOCB input (falling edge) TCNT value H'0180 H'0160 H'0010 H'0005 Time H'0000 TIOCA TGRA H'0005 H'0160 H'0010 TIOCB TGRB H'0180 Figure 18.10 Example of Input Capture Operation 18.4.2 Synchronous Operation In synchronous operation, the values in a number of TCNT counters can be rewritten simultaneously (synchronous presetting).
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Section 18 Multi-Function Timer Pulse Unit (MTU) Example of Synchronous Operation Setting Procedure: Figure 18.11 shows an example of the synchronous operation setting procedure.
PAGE 620
Section 18 Multi-Function Timer Pulse Unit (MTU) Example of Synchronous Operation: Figure 18.12 shows an example of synchronous operation. In this example, synchronous operation and PWM mode 1 have been designated for channels 0 to 2, TGRB_0 compare match has been set as the channel 0 counter clearing source, and synchronous clearing has been set for the channel 1 and 2 counter clearing source. Three-phase PWM waveforms are output from pins TIOC0A, TIOC1A, and TIOC2A.
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Section 18 Multi-Function Timer Pulse Unit (MTU) 18.4.3 Buffer Operation Buffer operation, provided for channels 0, 3, and 4, enables TGRC and TGRD to be used as buffer registers. Buffer operation differs depending on whether TGR has been designated as an input capture register or as a compare match register. Table 18.29 shows the register combinations used in buffer operation. Table 18.
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Section 18 Multi-Function Timer Pulse Unit (MTU) • When TGR is an input capture register When input capture occurs, the value in TCNT is transferred to TGR and the value previously held in the timer general register is transferred to the buffer register. This operation is illustrated in figure 18.14. Input capture signal Buffer register Timer general register TCNT Figure 18.14 Input Capture Buffer Operation Example of Buffer Operation Setting Procedure: Figure 18.
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Section 18 Multi-Function Timer Pulse Unit (MTU) Examples of Buffer Operation: • When TGR is an output compare register Figure 18.16 shows an operation example in which PWM mode 1 has been designated for channel 0, and buffer operation has been designated for TGRA and TGRC. The settings used in this example are TCNT clearing by compare match B, 1 output at compare match A, and 0 output at compare match B.
PAGE 624
Section 18 Multi-Function Timer Pulse Unit (MTU) TCNT value H'0F07 H'09FB H'0532 H'0000 Time TIOCA H'0532 TGRA TGRC H'0F07 H'09FB H'0532 H'0F07 Figure 18.17 Example of Buffer Operation (2) 18.4.4 Cascaded Operation In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit counter. This function works by counting the channel 1 counter clock upon overflow/underflow of TCNT_2 as set in bits TPSC0 to TPSC2 in TCR.
PAGE 625
Section 18 Multi-Function Timer Pulse Unit (MTU) Example of Cascaded Operation Setting Procedure: Figure 18.18 shows an example of the setting procedure for cascaded operation. Cascaded operation Set cascading [1] Start count [2] [1] Set bits TPSC2 to TPSC0 in the channel 1 TCR to B'1111 to select TCNT_2 overflow/ underflow counting. [2] Set the CST bit in TSTR for the upper and lower channel to 1 to start the count operation. Figure 18.
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Section 18 Multi-Function Timer Pulse Unit (MTU) 18.4.5 PWM Modes In PWM mode, PWM waveforms are output from the output pins. The output level can be selected as 0, 1, or toggle output in response to a compare match of each TGR. TGR registers settings can be used to output a PWM waveform in the range of 0% to 100% duty. Designating TGR compare match as the counter clearing source enables the period to be set in that register. All channels can be designated for PWM mode independently.
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Section 18 Multi-Function Timer Pulse Unit (MTU) The correspondence between PWM output pins and registers is shown in table 18.31. Table 18.
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Section 18 Multi-Function Timer Pulse Unit (MTU) Example of PWM Mode Setting Procedure: Figure 18.20 shows an example of the PWM mode setting procedure. PWM mode Select counter clock [1] Select counter clearing source [2] Select waveform output level [3] Set TGR [4] Set PWM mode [5] Start count [6] [1] Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR.
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Section 18 Multi-Function Timer Pulse Unit (MTU) Figure 18.22 shows an example of PWM mode 2 operation. In this example, synchronous operation is designated for channels 0 and 1, TGRB_1 compare match is set as the TCNT clearing source, and 0 is set for the initial output value and 1 for the output value of the other TGR registers (TGRA_0 to TGRD_0, TGRA_1), outputting a 5-phase PWM waveform.
PAGE 630
Section 18 Multi-Function Timer Pulse Unit (MTU) Figure 18.23 shows examples of PWM waveform output with 0% duty cycle and 100% duty cycle in PWM mode.
PAGE 631
Section 18 Multi-Function Timer Pulse Unit (MTU) 18.4.6 Phase Counting Mode In phase counting mode, the phase difference between two external clock inputs is detected and TCNT counts up or down accordingly. This mode can be set for channels 1 and 2. When phase counting mode is set, an external clock is selected as the counter input clock and TCNT operates as an up/down-counter regardless of the setting of bits TPSC0 to TPSC2 and bits CKEG0 and CKEG1 in TCR.
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Section 18 Multi-Function Timer Pulse Unit (MTU) Example of Phase Counting Mode Setting Procedure: Figure 18.24 shows an example of the phase counting mode setting procedure. Phase counting mode Select phase counting mode [1] Start count [2] [1] Select phase counting mode with bits MD3 to MD0 in TMDR. [2] Set the CST bit in TSTR to 1 to start the count operation. Figure 18.
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Section 18 Multi-Function Timer Pulse Unit (MTU) Table 18.33 Up/Down-Count Conditions in Phase Counting Mode 1 TCLKA (Channel 1) TCLKC (Channel 2) TCLKB (Channel 1) TCLKD (Channel 2) Operation Up-count High level Low level Low level High level Down-count High level Low level High level Low level [Legend] : Rising edge : Falling edge • Phase counting mode 2 Figure 18.26 shows an example of phase counting mode 2 operation, and table 18.34 summarizes the TCNT up/down-count conditions.
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Section 18 Multi-Function Timer Pulse Unit (MTU) Table 18.34 Up/Down-Count Conditions in Phase Counting Mode 2 TCLKA (Channel 1) TCLKC (Channel 2) TCLKB (Channel 1) TCLKD (Channel 2) Operation High level Don't care Low level Don't care Low level Don't care High level Up-count High level Don't care Low level Don't care High level Don't care Low level Down-count [Legend] : Rising edge : Falling edge • Phase counting mode 3 Figure 18.
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Section 18 Multi-Function Timer Pulse Unit (MTU) Table 18.35 Up/Down-Count Conditions in Phase Counting Mode 3 TCLKA (Channel 1) TCLKC (Channel 2) TCLKB (Channel 1) TCLKD (Channel 2) Operation High level Don't care Low level Don't care Low level Don't care High level Up-count High level Down-count Low level Don't care High level Don't care Low level Don't care [Legend] : Rising edge : Falling edge • Phase counting mode 4 Figure 18.
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Section 18 Multi-Function Timer Pulse Unit (MTU) Table 18.36 Up/Down-Count Conditions in Phase Counting Mode 4 TCLKA (Channel 1) TCLKC (Channel 2) TCLKB (Channel 1) TCLKD (Channel 2) Operation Up-count High level Low level Low level Don't care High level Down-count High level Low level High level Don't care Low level [Legend] : Rising edge : Falling edge Phase Counting Mode Application Example: Figure 18.
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Section 18 Multi-Function Timer Pulse Unit (MTU) Channel 1 TCLKA TCLKB Edge detection circuit TCNT_1 TGRA_1 (speed period capture) TGRB_1 (position period capture) TCNT_0 TGRA_0 (speed control period) + - TGRC_0 (position control period) + - TGRB_0 (pulse width capture) TGRD_0 (buffer operation) Channel 0 Figure 18.29 Phase Counting Mode Application Example Rev. 4.00 Sep.
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Section 18 Multi-Function Timer Pulse Unit (MTU) 18.4.7 Reset-Synchronized PWM Mode In the reset-synchronized PWM mode, three-phase output of positive and negative PWM waveforms that share a common wave transition point can be obtained by combining channels 3 and 4. When set for reset-synchronized PWM mode, the TIOC3B, TIOC3D, TIOC4A, TIOC4C, TIOC4B, and TIOC4D pins function as PWM output pins and TCNT3 functions as an upcounter. Table 18.37 shows the PWM output pins used. Table 18.
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Section 18 Multi-Function Timer Pulse Unit (MTU) Procedure for Selecting the Reset-Synchronized PWM Mode: Figure 18.30 shows an example of procedure for selecting the reset synchronized PWM mode.
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Section 18 Multi-Function Timer Pulse Unit (MTU) Reset-Synchronized PWM Mode Operation: Figure 18.31 shows an example of operation in the reset-synchronized PWM mode. TCNT_3 and TCNT_4 operate as upcounters. The counter is cleared when a TCNT_3 and TGRA_3 compare-match occurs, and then begins counting up from H'0000. The PWM output pin output toggles with each occurrence of a TGRB_3, TGRA_4, TGRB_4 compare-match, and upon counter clears.
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Section 18 Multi-Function Timer Pulse Unit (MTU) 18.4.8 Complementary PWM Mode In the complementary PWM mode, three-phase output of non-overlapping positive and negative PWM waveforms can be obtained by combining channels 3 and 4. In complementary PWM mode, TIOC3B, TIOC3D, TIOC4A, TIOC4B, TIOC4C, and TIOC4D pins function as PWM output pins, the TIOC3A pin can be set for toggle output synchronized with the PWM period. TCNT_3 and TCNT_4 function as increment/decrement counters. Table 18.
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Section 18 Multi-Function Timer Pulse Unit (MTU) Table 18.
PAGE 643
TCBR TGRA_3 TCDR Comparator Match signal TCNT_3 TCNTS TCNT_4 TGRD_3 TGRC_4 TGRB_4 Temp 3 TGRA_4 Match signal Temp 2 TGRB_3 Temp 1 Comparator PWM cycle output PWM output 1 PWM output 2 PWM output 3 Output protection circuit TDDR TGRC_3 Output controller TCNT_4 underflow interrupt TGRA_3 comparematch interrupt Section 18 Multi-Function Timer Pulse Unit (MTU) PWM output 4 PWM output 5 PWM output 6 External cutoff input POE0 POE1 POE2 POE3 TGRD_4 External cutoff interrupt : Register
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Section 18 Multi-Function Timer Pulse Unit (MTU) Example of Complementary PWM Mode Setting Procedure An example of the complementary PWM mode setting procedure is shown in figure 18.33. Complementary PWM mode Stop count operation 1 Counter clock, counter clear source selection 2 Brushless DC motor control setting 3 1 Clear bits CST3 and CST4 in the timer start register (TSTR) to 0, and halt timer counter (TCNT) operation. Perform complementary PWM mode setting when TCNT_3 and TCNT_4 are stopped.
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Section 18 Multi-Function Timer Pulse Unit (MTU) Outline of Complementary PWM Mode Operation In complementary PWM mode, 6-phase PWM output is possible. Figure 18.34 illustrates counter operation in complementary PWM mode, and figure 18.35 shows an example of complementary PWM mode operation. Counter Operation: In complementary PWM mode, three counters−TCNT_3, TCNT_4, and TCNTS−perform up/down-count operations.
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Section 18 Multi-Function Timer Pulse Unit (MTU) Counter value TGRA_3 TCDR TCNT_3 TCNT_4 TCNTS TDDR Time H'0000 TCNT_3 TCNT_4 TCNTS Figure 18.34 Complementary PWM Mode Counter Operation Register Operation: In complementary PWM mode, nine registers are used, comprising compare registers, buffer registers, and temporary registers. Figure 18.35 shows an example of complementary PWM mode operation.
PAGE 647
Section 18 Multi-Function Timer Pulse Unit (MTU) with the counter. In this interval, therefore, there are two compare match registers for one-phase output, with the compare register containing the pre-change data, and the temporary register containing the new data. In this interval, the three counters−TCNT_3, TCNT_4, and TCNTS−and two registers−compare register and temporary register−are compared, and PWM output controlled accordingly.
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Section 18 Multi-Function Timer Pulse Unit (MTU) Initialization: In complementary PWM mode, there are six registers that must be initialized. Before setting complementary PWM mode with bits MD3 to MD0 in the timer mode register (TMDR), the following initial register values must be set. TGRC_3 operates as the buffer register for TGRA_3, and should be set with 1/2 the PWM carrier cycle + dead time Td.
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Section 18 Multi-Function Timer Pulse Unit (MTU) Dead Time Setting: In complementary PWM mode, PWM pulses are output with a nonoverlapping relationship between the positive and negative phases. This non-overlap time is called the dead time. The non-overlap time is set in the timer dead time data register (TDDR). The value set in TDDR is used as the TCNT_3 counter start value, and creates non-overlap between TCNT_3 and TCNT_4. Complementary PWM mode should be cleared before changing the contents of TDDR.
PAGE 650
Section 18 Multi-Function Timer Pulse Unit (MTU) Counter value TGRC_3 update TGRA_3 update TCNT_3 TGRA_3 TCNT_4 Time Figure 18.36 Example of PWM Cycle Updating Register Data Updating: In complementary PWM mode, the buffer register is used to update the data in a compare register. The update data can be written to the buffer register at any time. There are five PWM duty and carrier cycle registers that have buffer registers and can be updated during operation.
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data1 Temp_R GR data1 BR H'0000 TGRC_4 TGRA_4 TGRA_3 Counter value data1 Transfer from temporary register to compare register data2 data2 data2 Transfer from temporary register to compare register Data update timing: counter crest and trough data3 data3 Transfer from temporary register to compare register data3 data4 data4 Transfer from temporary register to compare register data4 data5 data5 Transfer from temporary register to compare register data6 data6 data6 Transfer from tem
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Section 18 Multi-Function Timer Pulse Unit (MTU) Initial Output in Complementary PWM Mode: In complementary PWM mode, the initial output is determined by the setting of bits OLSN and OLSP in the timer output control register (TOCR). This initial output is the PWM pulse non-active level, and is output from when complementary PWM mode is set with the timer mode register (TMDR) until TCNT_4 exceeds the value set in the dead time register (TDDR). Figure 18.
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Section 18 Multi-Function Timer Pulse Unit (MTU) Timer output control register settings OLSN bit: 0 (initial output: high; active level: low) OLSP bit: 0 (initial output: high; active level: low) TCNT_3, 4 value TCNT_3 TCNT_4 TDDR TGR_4 Time Initial output Positive phase output Negative phase output Active level Complementary PWM mode (TMDR setting) TCNT_3, 4 count start (TSTR setting) Figure 18.39 Example of Initial Output in Complementary PWM Mode (2) Rev. 4.00 Sep.
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Section 18 Multi-Function Timer Pulse Unit (MTU) Complementary PWM Mode PWM Output Generation Method: In complementary PWM mode, 3-phase output is performed of PWM waveforms with a non-overlap time between the positive and negative phases. This non-overlap time is called the dead time. A PWM waveform is generated by output of the output level selected in the timer output control register in the event of a compare-match between a counter and data register.
PAGE 655
Section 18 Multi-Function Timer Pulse Unit (MTU) T2 period T1 period T1 period TGR3A_3 c d TCDR a b a' b' TDDR H'0000 Positive phase Negative phase Figure 18.40 Example of Complementary PWM Mode Waveform Output (1) Rev. 4.00 Sep.
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Section 18 Multi-Function Timer Pulse Unit (MTU) T2 period T1 period T1 period TGRA_3 c d TCDR a b a TDDR H'0000 Positive phase Negative phase Figure 18.41 Example of Complementary PWM Mode Waveform Output (2) Rev. 4.00 Sep.
PAGE 657
Section 18 Multi-Function Timer Pulse Unit (MTU) T1 period T2 period T1 period TGRA_3 TCDR a b TDDR c a' d b' H'0000 Positive phase Negative phase Figure 18.42 Example of Complementary PWM Mode Waveform Output (3) Rev. 4.00 Sep.
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Section 18 Multi-Function Timer Pulse Unit (MTU) Complementary PWM Mode 0% and 100% Duty Output: In complementary PWM mode, 0% and 100% duty cycles can be output as required. Figures 18.43 to 18.47 show output examples. 100% duty output is performed when the data register value is set to H'0000. The waveform in this case has a positive phase with a 100% on-state. 0% duty output is performed when the data register value is set to the same value as TGRA_3.
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Section 18 Multi-Function Timer Pulse Unit (MTU) T1 period T2 period T1 period TGRA_3 TCDR a b a b TDDR H'0000 c d Positive phase Negative phase Figure 18.44 Example of Complementary PWM Mode 0% and 100% Waveform Output (2) T1 period T2 period c TGRA_3 T1 period d TCDR a b TDDR H'0000 Positive phase Negative phase Figure 18.45 Example of Complementary PWM Mode 0% and 100% Waveform Output (3) Rev. 4.00 Sep.
PAGE 660
Section 18 Multi-Function Timer Pulse Unit (MTU) T1 period T2 period T1 period TGRA_3 TCDR a b TDDR H'0000 c b' d a' Positive phase Negative phase Figure 18.46 Example of Complementary PWM Mode 0% and 100% Waveform Output (4) T1 period TGRA_3 T2 period c a d T1 period b TCDR TDDR H'0000 Positive phase Negative phase Figure 18.47 Example of Complementary PWM Mode 0% and 100% Waveform Output (5) Rev. 4.00 Sep.
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Section 18 Multi-Function Timer Pulse Unit (MTU) Toggle Output Synchronized with PWM Cycle: In complementary PWM mode, toggle output can be performed in synchronization with the PWM carrier cycle by setting the PSYE bit to 1 in the timer output control register (TOCR). An example of a toggle output waveform is shown in figure 18.48. This output is toggled by a compare-match between TCNT_3 and TGRA_3 and a compare-match between TCNT4 and H'0000. The output pin for this toggle output is the TIOC3A pin.
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Section 18 Multi-Function Timer Pulse Unit (MTU) Counter Clearing by another Channel: In complementary PWM mode, by setting a mode for synchronization with another channel by means of the timer synchro register (TSYR), and selecting synchronous clearing with bits CCLR2 to CCLR0 in the timer control register (TCR), it is possible to have TCNT_3, TCNT_4, and TCNTS cleared by another channel. Figure 18.49 illustrates the operation.
PAGE 663
Section 18 Multi-Function Timer Pulse Unit (MTU) Example of AC Synchronous Motor (Brushless DC Motor) Drive Waveform Output: In complementary PWM mode, a brushless DC motor can easily be controlled using the timer gate control register (TGCR). Figures 18.50 to 18.53 show examples of brushless DC motor drive waveforms created using TGCR. When output phase switching for a 3-phase brushless DC motor is performed by means of external signals detected with a Hall element, etc., clear the FB bit in TGCR to 0.
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Section 18 Multi-Function Timer Pulse Unit (MTU) External input TIOC0A pin TIOC0B pin TIOC0C pin 6-phase output TIOC3B pin TIOC3D pin TIOC4A pin TIOC4C pin TIOC4B pin TIOC4D pin When BCD = 1, N = 1, P = 1, FB = 0, output active level = high Figure 18.51 Example of Output Phase Switching by External Input (2) TGCR UF bit VF bit WF bit 6-phase output TIOC3B pin TIOC3D pin TIOC4A pin TIOC4C pin TIOC4B pin TIOC4D pin When BCD = 1, N = 0, P = 0, FB = 1, output active level = high Figure 18.
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Section 18 Multi-Function Timer Pulse Unit (MTU) TGCR UF bit VF bit WF bit 6-phase output TIOC3B pin TIOC3D pin TIOC4A pin TIOC4C pin TIOC4B pin TIOC4D pin When BCD = 1, N = 1, P = 1, FB = 1, output active level = high Figure 18.53 Example of Output Phase Switching by Means of UF, VF, WF Bit Settings (2) A/D Conversion Start Request Setting: In complementary PWM mode, an A/D conversion start request can be set using a TGRA_3 compare-match or a compare-match on a channel other than channels 3 and 4.
PAGE 666
Section 18 Multi-Function Timer Pulse Unit (MTU) Some registers in channels 3 and 4 concerned are listed below: total 21 registers of TCR_3 and TCR_4; TMDR_3 and TMDR_4; TIORH_3 and TIORH_4; TIORL_3 and TIORL_4; TIER_3 and TIER_4; TCNT_3 and TCNT_4; TGRA_3 and TGRA_4; TGRB_3 and TGRB_4; TOER; TOCR; TGCR; TCDR; and TDDR. This function enables the CPU to prevent miswriting due to the CPU runaway by disabling CPU access to the mode registers, control register, and counters.
PAGE 667
Section 18 Multi-Function Timer Pulse Unit (MTU) Table 18.
PAGE 668
Section 18 Multi-Function Timer Pulse Unit (MTU) Overflow Interrupt: An interrupt is requested if the TCIEV bit in TIER is set to 1 when the TCFV flag in TSR is set to 1 by the occurrence of TCNT overflow on a channel. The interrupt request is cleared by clearing the TCFV flag to 0. The MTU has five overflow interrupts, one for each channel.
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Section 18 Multi-Function Timer Pulse Unit (MTU) 18.6 Operation Timing 18.6.1 Input/Output Timing TCNT Count Timing: Figure 18.54 shows TCNT count timing in internal clock operation, and figure 18.55 shows TCNT count timing in external clock operation (normal mode), and figure 18.56 shows TCNT count timing in external clock operation (phase counting mode). Pφ Internal clock Falling edge Rising edge TCNT input clock N-1 TCNT N N+1 N+2 Figure 18.
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Section 18 Multi-Function Timer Pulse Unit (MTU) Pφ External clock Falling edge Rising edge Falling edge TCNT input clock TCNT N-1 N N+1 Figure 18.56 Count Timing in External Clock Operation (Phase Counting Mode) Output Compare Output Timing: A compare match signal is generated in the final state in which TCNT and TGR match (the point at which the count value matched by TCNT is updated).
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Section 18 Multi-Function Timer Pulse Unit (MTU) Pφ TCNT input clock TCNT N TGR N N+1 Compare match signal TIOC pin Figure 18.58 Output Compare Output Timing (Complementary PWM Mode/Reset Synchronous PWM Mode) Input Capture Signal Timing: Figure 18.59 shows input capture signal timing. Pφ Input capture input Input capture signal TCNT TGR N N+1 N+2 N N+2 Figure 18.59 Input Capture Input Signal Timing Rev. 4.00 Sep.
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Section 18 Multi-Function Timer Pulse Unit (MTU) Timing for Counter Clearing by Compare Match/Input Capture: Figure 18.60 shows the timing when counter clearing on compare match is specified, and figure 18.61 shows the timing when counter clearing on input capture is specified. Pφ Compare match signal Counter clear signal TCNT N TGR N H'0000 Figure 18.60 Counter Clear Timing (Compare Match) Pφ Input capture signal Counter clear signal TCNT N H'0000 N TGR Figure 18.
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Section 18 Multi-Function Timer Pulse Unit (MTU) Buffer Operation Timing: Figures 18.62 and 18.63 show the timing in buffer operation. Pφ TCNT n n+1 Compare match signal TGRA, TGRB n TGRC, TGRD N N Figure 18.62 Buffer Operation Timing (Compare Match) Pφ Input capture signal TCNT N TGRA, TGRB n TGRC, TGRD N+1 N N+1 n N Figure 18.63 Buffer Operation Timing (Input Capture) Rev. 4.00 Sep.
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Section 18 Multi-Function Timer Pulse Unit (MTU) 18.6.2 Interrupt Signal Timing TGF Flag Setting Timing in Case of Compare Match: Figure 18.64 shows the timing for setting of the TGF flag in TSR on compare match, and TGI interrupt request signal timing. Pφ TCNT input clock TCNT N TGR N N+1 Compare match signal TGF flag TGI interrupt Figure 18.64 TGI Interrupt Timing (Compare Match) TGF Flag Setting Timing in Case of Input Capture: Figure 18.
PAGE 675
Section 18 Multi-Function Timer Pulse Unit (MTU) TCFV Flag/TCFU Flag Setting Timing: Figure 18.66 shows the timing for setting of the TCFV flag in TSR on overflow, and TCIV interrupt request signal timing. Figure 18.67 shows the timing for setting of the TCFU flag in TSR on underflow, and TCIU interrupt request signal timing. Pφ TCNT input clock TCNT (overflow) H'FFFF H'0000 Overflow signal TCFV flag TCIV interrupt Figure 18.
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Section 18 Multi-Function Timer Pulse Unit (MTU) Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. When the DMA is activated, the flag is cleared automatically. Figure 18.68 shows the timing for status flag clearing by the CPU, and figure 18.69 shows the timing for status flag clearing by the DMA. TSR write cycle T1 T2 Pφ TSR address Address Write signal Status flag Interrupt request signal Figure 18.
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Section 18 Multi-Function Timer Pulse Unit (MTU) 18.7 Usage Notes 18.7.1 Module Standby Mode Setting MTU operation can be disabled or enabled using the module standby register. 18.7.2 Input Clock Restrictions The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at least 2.5 states in the case of both-edge detection. The TPU will not operate properly at narrower pulse widths.
PAGE 678
Section 18 Multi-Function Timer Pulse Unit (MTU) 18.7.3 Caution on Period Setting When counter clearing on compare match is set, TCNT is cleared in the final state in which it matches the TGR value (the point at which the count value matched by TCNT is updated). Consequently, the actual counter frequency is given by the following formula: Pφ f= (N + 1) Where 18.7.
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Section 18 Multi-Function Timer Pulse Unit (MTU) 18.7.5 Conflict between TCNT Write and Increment Operations If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence and TCNT is not incremented. Figure 18.72 shows the timing in this case. TCNT write cycle T2 T1 Pφ TCNT address Address Write signal TCNT input clock TCNT N M TCNT write data Figure 18.72 Conflict between TCNT Write and Increment Operations Rev. 4.00 Sep.
PAGE 680
Section 18 Multi-Function Timer Pulse Unit (MTU) 18.7.6 Conflict between TGR Write and Compare Match When a compare match occurs in the T2 state of a TGR write cycle, the TGR write is executed and the compare match signal is generated. Figure 18.73 shows the timing in this case. TGR write cycle T1 T2 Pφ TGR address Address Write signal Compare match signal TCNT TGR N N+1 N M TGR write data Figure 18.73 Conflict between TGR Write and Compare Match 18.7.
PAGE 681
Section 18 Multi-Function Timer Pulse Unit (MTU) TGR write cycle T1 T2 Pφ Buffer register address Address Write signal Compare match signal Compare match buffer signal Buffer register Buffer register write data M N M TGR Figure 18.74 Conflict between Buffer Register Write and Compare Match (Channel 0) TGR write cycle T1 T2 Pφ Buffer register address Address Write signal Compare match signal Compare match buffer signal Buffer register write data Buffer register TGR N M N Figure 18.
PAGE 682
Section 18 Multi-Function Timer Pulse Unit (MTU) 18.7.8 Conflict between TGR Read and Input Capture If an input capture signal is generated in the T2 state of a TGR read cycle, the data that is read will be that in the buffer after input capture transfer. Figure 18.76 shows the timing in this case. Buffer register read cycle T2 T1 Pφ Buffer register address Address Read signal Input capture signal TCNT N M TGR Buffer register N M Figure 18.76 Conflict between TGR Read and Input Capture Rev. 4.
PAGE 683
Section 18 Multi-Function Timer Pulse Unit (MTU) 18.7.9 Conflict between TGR Write and Input Capture If an input capture signal is generated in the T2 state of a TGR write cycle, the input capture operation takes precedence and the write to TGR is not performed. Figure 18.77 shows the timing in this case. TGR write cycle T1 T2 Pφ TGR address Address Write signal Input capture signal TCNT TGR M M Figure 18.77 Conflict between TGR Write and Input Capture Rev. 4.00 Sep.
PAGE 684
Section 18 Multi-Function Timer Pulse Unit (MTU) 18.7.10 Conflict between Buffer Register Write and Input Capture If an input capture signal is generated in the T2 state of a buffer register write cycle, the buffer operation takes precedence and the write to the buffer register is not performed. Figure 18.78 shows the timing in this case. Buffer register write cycle T2 T1 Pφ Buffer register address Address Write signal Input capture signal TCNT TGR Buffer register N M N M Figure 18.
PAGE 685
Section 18 Multi-Function Timer Pulse Unit (MTU) TCNT write cycle T1 T2 Pφ Address TCNT_2 address Write signal TCNT_2 H'FFFE H'FFFF N N+1 TCNT_2 write data TGR2A_2 to TGR2B_2 H'FFFF Ch2 comparematch signal A/B Disabled TCNT_1 input clock TCNT_1 M TGRA_1 M Ch1 comparematch signal A TGRB_1 N M Ch1 input capture signal B TCNT_0 P TGRA_0 to TGRD_0 Q P Ch0 input capture signal A to D Figure 18.79 TCNT_2 Write and Overflow/Underflow Conflict with Cascade Connection Rev. 4.00 Sep.
PAGE 686
Section 18 Multi-Function Timer Pulse Unit (MTU) 18.7.12 Counter Value during Complementary PWM Mode Stop When counting operation is stopped with TCNT_3 and TCNT_4 in complementary PWM mode, TCNT_3 has the timer dead time register (TDDR) value, and TCNT_4 is set to H'0000. When restarting complementary PWM mode, counting begins automatically from the initialized state. This explanatory diagram is shown in figure 18.80.
PAGE 687
Section 18 Multi-Function Timer Pulse Unit (MTU) buffer register for TGRA_3. At the same time, TGRC_4 functions as the buffer register for TRGA_4, while the TCBR functions as the TCDR's buffer register. 18.7.14 Reset Sync PWM Mode Buffer Operation and Compare Match Flag When setting buffer operation for reset sync PWM mode, set the BFA and BFB bits of TMDR_4 to 0. The TIOC4C pin will be unable to produce its waveform output if the BFA bit of TMDR_4 is set to 1.
PAGE 688
Section 18 Multi-Function Timer Pulse Unit (MTU) 18.7.15 Overflow Flags in Reset Sync PWM Mode When set to reset sync PWM mode, TCNT_3 and TCNT_4 start counting when the CST3 bit of TSTR is set to 1. At this point, TCNT_4's count clock source and count edge obey the TCR_3 setting.
PAGE 689
Section 18 Multi-Function Timer Pulse Unit (MTU) Pφ TCNT input clock TCNT H'FFFF H'0000 Counter clear signal TGF Disabled TCFV Figure 18.83 Conflict between Overflow and Counter Clearing 18.7.17 Conflict between TCNT Write and Overflow/Underflow If there is an up-count or down-count in the T2 state of a TCNT write cycle, and overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is not set. Figure 18.
PAGE 690
Section 18 Multi-Function Timer Pulse Unit (MTU) 18.7.18 Cautions on Transition from Normal Operation or PWM Mode 1 to Reset-Synchronous PWM Mode When making a transition from channel 3 or 4 normal operation or PWM mode 1 to resetsynchronous PWM mode, if the counter is halted with the output pins (TIOC3B, TIOC3D, TIOC4A, TIOC4C, TIOC4B, TIOC4D) in the high-impedance state, followed by the transition to reset-synchronous PWM mode and operation in that mode, the initial pin output will not be correct.
PAGE 691
Section 18 Multi-Function Timer Pulse Unit (MTU) 18.8 MTU Output Pin Initialization 18.8.1 Operating Modes The MTU has the following six operating modes. Waveform output is possible in all of these modes.
PAGE 692
Section 18 Multi-Function Timer Pulse Unit (MTU) 18.8.3 Operation in Case of Re-Setting Due to Error During Operation, etc. If an error occurs during MTU operation, MTU output should be cut by the system. Cutoff is performed by switching the pin output to port output with the PFC and outputting the inverse of the active level. For large-current pins, output can also be cut by hardware, using port output enable (POE). The pin initialization procedures for re-setting due to an error during operation, etc.
PAGE 693
Section 18 Multi-Function Timer Pulse Unit (MTU) 18.8.4 Overview of Initialization Procedures and Mode Transitions in Case of Error during Operation, Etc. • When making a transition to a mode (Normal, PWM1, PWM2, PCM) in which the pin output level is selected by the timer I/O control register (TIOR) setting, initialize the pins by means of a TIOR setting. • In PWM mode 1, since a waveform is not output to the TIOC*B (TIOC *D) pin, setting TIOR will not initialize the pins.
PAGE 694
Section 18 Multi-Function Timer Pulse Unit (MTU) (1) Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in Normal Mode Figure 18.85 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in normal mode after re-setting.
PAGE 695
Section 18 Multi-Function Timer Pulse Unit (MTU) (2) Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in PWM Mode 1 Figure 18.86 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in PWM mode 1 after re-setting.
PAGE 696
Section 18 Multi-Function Timer Pulse Unit (MTU) (3) Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in PWM Mode 2 Figure 18.87 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in PWM mode 2 after re-setting.
PAGE 697
Section 18 Multi-Function Timer Pulse Unit (MTU) (4) Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in Phase Counting Mode Figure 18.88 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in phase counting mode after re-setting.
PAGE 698
Section 18 Multi-Function Timer Pulse Unit (MTU) (5) Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in Complementary PWM Mode Figure 18.89 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in complementary PWM mode after re-setting.
PAGE 699
Section 18 Multi-Function Timer Pulse Unit (MTU) (6) Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in Reset-Synchronous PWM Mode Figure 18.90 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in reset-synchronous PWM mode after re-setting.
PAGE 700
Section 18 Multi-Function Timer Pulse Unit (MTU) (7) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in Normal Mode Figure 18.91 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in normal mode after re-setting.
PAGE 701
Section 18 Multi-Function Timer Pulse Unit (MTU) (8) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in PWM Mode 1 Figure 18.92 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in PWM mode 1 after re-setting.
PAGE 702
Section 18 Multi-Function Timer Pulse Unit (MTU) (9) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in PWM Mode 2 Figure 18.93 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in PWM mode 2 after re-setting.
PAGE 703
Section 18 Multi-Function Timer Pulse Unit (MTU) (10) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in Phase Counting Mode Figure 18.94 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in phase counting mode after re-setting.
PAGE 704
Section 18 Multi-Function Timer Pulse Unit (MTU) (11) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in Complementary PWM Mode Figure 18.95 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in complementary PWM mode after re-setting.
PAGE 705
Section 18 Multi-Function Timer Pulse Unit (MTU) (12) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in Reset-Synchronous PWM Mode Figure 18.96 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in reset-synchronous PWM mode after re-setting.
PAGE 706
Section 18 Multi-Function Timer Pulse Unit (MTU) (13) Operation when Error Occurs during PWM Mode 2 Operation, and Operation is Restarted in Normal Mode Figure 18.97 shows an explanatory diagram of the case where an error occurs in PWM mode 2 and operation is restarted in normal mode after re-setting.
PAGE 707
Section 18 Multi-Function Timer Pulse Unit (MTU) (14) Operation when Error Occurs during PWM Mode 2 Operation, and Operation is Restarted in PWM Mode 1 Figure 18.98 shows an explanatory diagram of the case where an error occurs in PWM mode 2 and operation is restarted in PWM mode 1 after re-setting.
PAGE 708
Section 18 Multi-Function Timer Pulse Unit (MTU) (15) Operation when Error Occurs during PWM Mode 2 Operation, and Operation is Restarted in PWM Mode 2 Figure 18.99 shows an explanatory diagram of the case where an error occurs in PWM mode 2 and operation is restarted in PWM mode 2 after re-setting.
PAGE 709
Section 18 Multi-Function Timer Pulse Unit (MTU) (16) Operation when Error Occurs during PWM Mode 2 Operation, and Operation is Restarted in Phase Counting Mode Figure 18.100 shows an explanatory diagram of the case where an error occurs in PWM mode 2 and operation is restarted in phase counting mode after re-setting.
PAGE 710
Section 18 Multi-Function Timer Pulse Unit (MTU) (17) Operation when Error Occurs during Phase Counting Mode Operation, and Operation is Restarted in Normal Mode Figure 18.101 shows an explanatory diagram of the case where an error occurs in phase counting mode and operation is restarted in normal mode after re-setting.
PAGE 711
Section 18 Multi-Function Timer Pulse Unit (MTU) (18) Operation when Error Occurs during Phase Counting Mode Operation, and Operation is Restarted in PWM Mode 1 Figure 18.102 shows an explanatory diagram of the case where an error occurs in phase counting mode and operation is restarted in PWM mode 1 after re-setting.
PAGE 712
Section 18 Multi-Function Timer Pulse Unit (MTU) (19) Operation when Error Occurs during Phase Counting Mode Operation, and Operation is Restarted in PWM Mode 2 Figure 18.103 shows an explanatory diagram of the case where an error occurs in phase counting mode and operation is restarted in PWM mode 2 after re-setting.
PAGE 713
Section 18 Multi-Function Timer Pulse Unit (MTU) (20) Operation when Error Occurs during Phase Counting Mode Operation, and Operation is Restarted in Phase Counting Mode Figure 18.104 shows an explanatory diagram of the case where an error occurs in phase counting mode and operation is restarted in phase counting mode after re-setting.
PAGE 714
Section 18 Multi-Function Timer Pulse Unit (MTU) (21) Operation when Error Occurs during Complementary PWM Mode Operation, and Operation is Restarted in Normal Mode Figure 18.105 shows an explanatory diagram of the case where an error occurs in complementary PWM mode and operation is restarted in normal mode after re-setting.
PAGE 715
Section 18 Multi-Function Timer Pulse Unit (MTU) (22) Operation when Error Occurs during Complementary PWM Mode Operation, and Operation is Restarted in PWM Mode 1 Figure 18.106 shows an explanatory diagram of the case where an error occurs in complementary PWM mode and operation is restarted in PWM mode 1 after re-setting.
PAGE 716
Section 18 Multi-Function Timer Pulse Unit (MTU) (23) Operation when Error Occurs during Complementary PWM Mode Operation, and Operation is Restarted in Complementary PWM Mode Figure 18.107 shows an explanatory diagram of the case where an error occurs in complementary PWM mode and operation is restarted in complementary PWM mode after re-setting (when operation is restarted using the cycle and duty settings at the time the counter was stopped).
PAGE 717
Section 18 Multi-Function Timer Pulse Unit (MTU) (24) Operation when Error Occurs during Complementary PWM Mode Operation, and Operation is Restarted in Complementary PWM Mode Figure 18.108 shows an explanatory diagram of the case where an error occurs in complementary PWM mode and operation is restarted in complementary PWM mode after re-setting (when operation is restarted using completely new cycle and duty settings).
PAGE 718
Section 18 Multi-Function Timer Pulse Unit (MTU) (25) Operation when Error Occurs during Complementary PWM Mode Operation, and Operation is Restarted in Reset-Synchronous PWM Mode Figure 18.109 shows an explanatory diagram of the case where an error occurs in complementary PWM mode and operation is restarted in reset-synchronous PWM mode.
PAGE 719
Section 18 Multi-Function Timer Pulse Unit (MTU) (26) Operation when Error Occurs during Reset-Synchronous PWM Mode Operation, and Operation is Restarted in Normal Mode Figure 18.110 shows an explanatory diagram of the case where an error occurs in resetsynchronous PWM mode and operation is restarted in normal mode after re-setting.
PAGE 720
Section 18 Multi-Function Timer Pulse Unit (MTU) (27) Operation when Error Occurs during Reset-Synchronous PWM Mode Operation, and Operation is Restarted in PWM Mode 1 Figure 18.111 shows an explanatory diagram of the case where an error occurs in resetsynchronous PWM mode and operation is restarted in PWM mode 1 after re-setting.
PAGE 721
Section 18 Multi-Function Timer Pulse Unit (MTU) (28) Operation when Error Occurs during Reset-Synchronous PWM Mode Operation, and Operation is Restarted in Complementary PWM Mode Figure 18.112 shows an explanatory diagram of the case where an error occurs in resetsynchronous PWM mode and operation is restarted in complementary PWM mode after re-setting.
PAGE 722
Section 18 Multi-Function Timer Pulse Unit (MTU) (29) Operation when Error Occurs during Reset-Synchronous PWM Mode Operation, and Operation is Restarted in Reset-Synchronous PWM Mode Figure 18.113 shows an explanatory diagram of the case where an error occurs in resetsynchronous PWM mode and operation is restarted in reset-synchronous PWM mode after resetting.
PAGE 723
Section 18 Multi-Function Timer Pulse Unit (MTU) 18.9 Port Output Enable (POE) The port output enable (POE) can be used to establish a high-impedance state for high-current pins, by changing the POE0 to POE3 pin input, depending on the output status of the high-current pins (TIOC3B/PTE[6], TIOC3D/PTE[4], TIOC4A/PTE[3], TIOC4B/PTE[2], TIOC4C/PTE[1], TIOC4D/PTE[0]). It can also simultaneously generate interrupt requests. 18.9.
PAGE 724
Section 18 Multi-Function Timer Pulse Unit (MTU) The POE has input-level detection circuitry and output-level detection circuitry, as shown in the block diagram of figure 18.114.
PAGE 725
Section 18 Multi-Function Timer Pulse Unit (MTU) 18.9.2 Pin Configuration Table 18.44 Pin Configuration Name Abbreviation I/O Description Port output enable input pins POE0 to POE3 Input Input request signals to make highcurrent pins high-impedance state Table 18.45 shows output-level comparisons with pin combinations. Table 18.
PAGE 726
Section 18 Multi-Function Timer Pulse Unit (MTU) Bit Bit Name Initial value R/W 15 POE3F 0 R/(W)* POE3 Flag Description This flag indicates that a high impedance request has been input to the POE3 pin [Clear condition] • By writing 0 to POE3F after reading a POE3F = 1 [Set condition] • 14 POE2F 0 When the input set by ICSR1 bits 7 and 6 occurs at the POE3 pin R/(W)* POE2 Flag This flag indicates that a high impedance request has been input to the POE2 pin [Clear condition] • By writing 0 to
PAGE 727
Section 18 Multi-Function Timer Pulse Unit (MTU) Bit Bit Name Initial value R/W Description 11 to 9  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 8 PIE 0 R/W Port Interrupt Enable This bit enables/disables interrupt requests when any of the POE0F to POE3F bits of the ICSR1 are set to 1 0: Interrupt requests disabled 1: Interrupt requests enabled 7 POE3M1 0 R/W POE3 mode 1, 0 6 POE3M0 0 R/W These bits select the input mode of the POE3 pin.
PAGE 728
Section 18 Multi-Function Timer Pulse Unit (MTU) Bit Bit Name Initial value R/W 3 2 POE1M1 POE1M0 0 0 R/W R/W 1 0 Note: Description POE1 mode 1, 0 These bits select the input mode of the POE1 pin. 00: Accept request on falling edge of POE1 input 01: Accept request when POE1 input has been sampled for 16 Pφ/8 clock pulses, and all are low level. 10: Accept request when POE1 input has been sampled for 16 Pφ/16 clock pulses, and all are low level.
PAGE 729
Section 18 Multi-Function Timer Pulse Unit (MTU) Output Level Control/Status Register (OCSR): OCSR is a 16-bit readable/writable register that controls the enable/disable of both output level comparison and interrupts, and indicates status. If the OSF bit is set to 1, the high current pins become high impedance.
PAGE 730
Section 18 Multi-Function Timer Pulse Unit (MTU) Bit Bit Name Initial value R/W Description 9 OCE 0 R/W Output Level Compare Enable This bit enables the start of output level comparisons. When setting this bit to 1, pay attention to the output pin combinations shown in table 18.43, Mode Transition Combinations. When 0 is output on both pins, the OSF bit is set to 1 at the same time when this bit is set, and output goes to high impedance.
PAGE 731
Section 18 Multi-Function Timer Pulse Unit (MTU) 18.9.4 Operation Input Level Detection Operation: If the input conditions set by the ICSR1 occur on any of the POE0 to POE3 pins, all high-current pins become high-impedance state. However, only when the general input/output function or MTU function is selected, the large-current pin is in the highimpedance state. 1.
PAGE 732
Section 18 Multi-Function Timer Pulse Unit (MTU) 2. Low-Level Detection Figure 18.116 shows the low-level detection operation. Sixteen continuous low levels are sampled with the sampling clock established by the ICSR1. If even one high level is detected during this interval, the low level is not accepted. Furthermore, the timing when the large-current pins enter the high-impedance state from the sampling clock is the same in both falling-edge detection and in low-level detection.
PAGE 733
Section 18 Multi-Function Timer Pulse Unit (MTU) Release from High-Impedance State: High-current pins that have entered high-impedance state due to input-level detection can be released either by returning them to their initial state with a power-on reset, or by clearing all of the bit 12 to 15 (POE0F to POE3F) flags of the ICSR1.
PAGE 734
Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep.
PAGE 735
Section 19 Serial Communication Interface with FIFO (SCIF) Section 19 Serial Communication Interface with FIFO (SCIF) 19.1 Overview This LSI has a three-channel serial communication interface with FIFO (SCIF) that supports both asynchronous and clock synchronous serial communication. It also has 16-stage FIFO registers for both transmission and reception independently for each channel that enable this LSI to perform efficient high-speed continuous communication. 19.1.
PAGE 736
Section 19 Serial Communication Interface with FIFO (SCIF) • Internal or external transmit/receive clock source: From either baud rate generator (internal) or SCK pin (external) • Four types of interrupts: Transmit-FIFO-data-empty, break, receive-FIFO-data-full, and receive-error interrupts are requested independently. The direct memory access controller (DMAC) can be activated to execute a data transfer by a transmit-FIFO-data-empty or receiveFIFO-data-full interrupt.
PAGE 737
Section 19 Serial Communication Interface with FIFO (SCIF) Bus interface Module data bus SCBRRn SCSMR SCFRDR (16 stage) SCFTDR (16 stage) SCLSR SCTSR SCFSR SCSCR Internal data bus SCFDR SCFCR RxD SCRSR Baud rate generator SCSPTR Pφ Pφ/4 Pφ/16 Transmission/ reception control Pφ/64 TxD Parity generation Clock Parity check External clock SCK TXI RXI ERI BRI CTS RTS SCIF [Legend] SCRSR: Receive shift register SCFRDR: Receive FIFO data register SCTSR: Transmit shift register SCFTDR: Transm
PAGE 738
Section 19 Serial Communication Interface with FIFO (SCIF) 19.2 Pin Configuration The SCIF has the serial pins summarized in table 19.1. Table 19.
PAGE 739
Section 19 Serial Communication Interface with FIFO (SCIF) 19.3 Register Description The SCIF has the following registers. These registers specify the data format and bit rate, and control the transmitter and receiver sections.
PAGE 740
Section 19 Serial Communication Interface with FIFO (SCIF) 19.3.1 Receive Shift Register (SCRSR) The receive shift register (SCRSR) receives serial data. Data input at the RxD pin is loaded into SCRSR in the order received, LSB (bit 0) first, converting the data to parallel form. When one byte has been received, it is automatically transferred to SCFRDR, the receive FIFO data register. The CPU cannot read or write to SCRSR directly. 19.3.
PAGE 741
Section 19 Serial Communication Interface with FIFO (SCIF) 19.3.4 Transmit FIFO Data Register (SCFTDR) The transmit FIFO data register (SCFTDR) is a 16-byte FIFO register that stores data for serial transmission. When the SCIF detects that the transmit shift register (SCTSR) is empty, it moves transmit data written in the SCFTDR into SCTSR and starts serial transmission. Continuous serial transmission is performed until there is no transmit data left in SCFTDR.
PAGE 742
Section 19 Serial Communication Interface with FIFO (SCIF) Bit Bit Name Initial value R/W Description 6 CHR 0 R/W Character Length Selects 7-bit or 8-bit data in asynchronous mode. In the synchronous mode, the data length is always eight bits, regardless of the CHR setting. 0: 8-bit data 1: 7-bit data* Note: * When 7-bit data is selected, the MSB (bit 7) of the transmit FIFO data register is not transmitted.
PAGE 743
Section 19 Serial Communication Interface with FIFO (SCIF) Bit Bit Name Initial value R/W Description 4 O/E 0 R/W Parity mode Selects even or odd parity when parity bits are added and checked. The O/E setting is used only in asynchronous mode and only when the parity enable bit (PE) is set to 1 to enable parity addition and checking. The O/E setting is ignored in synchronous mode, or in asynchronous mode when parity addition and checking is disabled.
PAGE 744
Section 19 Serial Communication Interface with FIFO (SCIF) Bit Bit Name Initial value R/W Description 2  0 R Reserved This bit is always read as 0. The write value should always be 0. 1 CKS1 0 R/W Clock Select 1, 0 0 CKS0 0 R/W Select the internal clock source of the on-chip baud rate generator. Four clock sources are available. Pφ, Pφ/4, Pφ/16 and Pφ/64. For further information on the clock source, bit rate register settings, and baud rate, see section 19.3.
PAGE 745
Section 19 Serial Communication Interface with FIFO (SCIF) 19.3.6 Serial Control Register (SCSCR) The serial control register (SCSCR) operates the SCIF transmitter/receiver, enables/disables interrupt requests, and selects the transmit/receive clock source. The CPU can always read and write to SCSCR. SCSCR is initialized to H'0000 by a power-on reset. Bit Bit Name Initial value R/W Description 15 to 8  All 0 R Reserved These bits are always read as 0. The write value should always be 0.
PAGE 746
Section 19 Serial Communication Interface with FIFO (SCIF) Bit Bit Name Initial value R/W Description 6 RIE 0 R/W Receive Interrupt Enable Enables or disables the receive-data-full (RXI) interrupts requested when the RDF flag or DR flag in serial status register (SCFSR) is set to1, receive-error (ERI) interrupts requested when the ER flag in SCFSR is set to1, and break (BRI) interrupts requested when the BRK flag in SCFSR or the ORER flag in line status register (SCLSR) is set to1.
PAGE 747
Section 19 Serial Communication Interface with FIFO (SCIF) Bit Bit Name Initial value R/W Description 4 RE 0 R/W Receive Enable Enables or disables the SCIF serial receiver. 0: Receiver disabled* 1 2 1: Receiver enabled* Notes: 1. Clearing RE to 0 does not affect the receive flags (DR, ER, BRK, RDF, FER, PER, and ORER). These flags retain their previous values. 2.
PAGE 748
Section 19 Serial Communication Interface with FIFO (SCIF) Bit Bit Name Initial value R/W Description 2  0 R Reserved This bit is always read as 0. The write value should always be 0. 1 CKE1 0 R/W Clock Enable 1, 0 0 CKE0 0 R/W Select the SCIF clock source and enable or disable clock output from the SCK pin. Depending on the combination of CKE1 and CKE0, the SCK pin can be used for serial clock output or serial clock input.
PAGE 749
Section 19 Serial Communication Interface with FIFO (SCIF) 19.3.7 Serial Status Register (SCFSR) The serial status register (SCFSR) is a 16-bit register. The upper 8 bits indicate the number of receives errors in the SCFRDR data, and the lower 8 bits indicate the status flag indicating SCIF operating state. The CPU can always read and write to SCFSR, but cannot write 1 to the status flags (ER, TEND, TDFE, BRK, RDF, and DR).
PAGE 750
Section 19 Serial Communication Interface with FIFO (SCIF) Bit Bit Name Initial value R/W 7 ER 0 R/(W)* Receive Error Description Indicates the occurrence of a framing error, or of a 1 parity error when receiving data that includes parity. * 0: Receiving is in progress or has ended normally [Clearing conditions] • ER is cleared to 0 a power-on reset • ER is cleared to 0 when the chip is when 0 is written after 1 is read from ER 1: A framing error or parity error has occurred.
PAGE 751
Section 19 Serial Communication Interface with FIFO (SCIF) Bit Bit Name Initial value R/W 6 TEND 0 R/(W)* Transmit End Description Indicates that when the last bit of a serial character was transmitted, SCFTDR did not contain valid data, so transmission has ended.
PAGE 752
Section 19 Serial Communication Interface with FIFO (SCIF) Bit Bit Name Initial value R/W 5 TDFE 0 R/(W)* Transmit FIFO Data Empty Description Indicates that data has been transferred from the transmit FIFO data register (SCFTDR) to the transmit shift register (SCTSR), the quantity of data in SCFTDR has become less than the transmission trigger number specified by the TTRG1 and TTRG0 bits in the FIFO control register (SCFCR), and writing of transmit data to SCFTDR is enabled.
PAGE 753
Section 19 Serial Communication Interface with FIFO (SCIF) Bit Bit Name Initial value R/W 4 BRK 0 R/(W)* Break Detection Description Indicates that a break signal has been detected in receive data.
PAGE 754
Section 19 Serial Communication Interface with FIFO (SCIF) Bit Bit Name Initial value R/W Description 2 PER 0 R Parity Error Indicates a parity error in the data read from the next receive FIFO data register (SCFRDR) in asynchronous mode.
PAGE 755
Section 19 Serial Communication Interface with FIFO (SCIF) Bit Bit Name Initial value R/W 1 RDF 0 R/(W)* Receive FIFO Data Full Description Indicates that receive data has been transferred to the receive FIFO data register (SCFRDR), and the quantity of data in SCFRDR has become more than the receive trigger number specified by the RTRG1 and RTRG0 bits in the FIFO control register (SCFCR).
PAGE 756
Section 19 Serial Communication Interface with FIFO (SCIF) Bit Bit Name Initial value R/W 0 DR 0 R/(W)* Receive Data Ready Description Indicates that the quantity of data in the receive FIFO data register (SCFRDR) is less than the specified receive trigger number, and that the next data has not yet been received after the elapse of 15 ETU from the last stop bit in asynchronous mode. In clock synchronous mode, this bit is not set to 1.
PAGE 757
Section 19 Serial Communication Interface with FIFO (SCIF) 19.3.8 Bit Rate Register (SCBRR) The bit rate register (SCBRR) is an 8-bit register that, together with the baud rate generator clock source selected by the CKS1 and CKS0 bits in the serial mode register (SCSMR), determines the serial transmit/receive bit rate. The CPU can always read and write to SCBRR. SCBRR is initialized to H'FF by a power-on reset.
PAGE 758
Section 19 Serial Communication Interface with FIFO (SCIF) Table 19.3 lists examples of SCBRR settings in asynchronous mode, and table 19.4 lists examples of SCBRR settings in synchronous mode. Table 19.3 Bit Rates and SCBRR Settings in Asynchronous Mode Pφ (MHz) 5 6 6.144 Bit Rate (bits/s) n N Error (%) n N Error (%) n N Error (%) 110 2 88 −0.25 2 106 −0.44 2 108 0.08 150 2 64 0.16 2 77 0.16 2 79 0.00 300 1 129 0.16 1 155 0.16 1 159 0.00 600 1 64 0.16 1 77 0.
PAGE 759
Section 19 Serial Communication Interface with FIFO (SCIF) Pφ (MHz) 10 12 12.288 14.7456 Bit Rate (bits/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 2 177 –0.25 2 212 0.03 2 217 0.08 3 64 0.70 150 2 129 0.16 2 155 0.16 2 159 0.00 2 191 0.00 300 2 64 0.16 2 77 0.16 2 79 0.00 2 95 0.00 600 1 129 0.16 1 155 0.16 1 159 0.00 1 191 0.00 1200 1 64 0.16 1 77 0.16 1 79 0.00 1 95 0.00 2400 0 129 0.16 0 155 0.
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Section 19 Serial Communication Interface with FIFO (SCIF) Pφ (MHz) 24.576 28.7 30 33 Bit Rate (bits/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 3 108 0.08 3 126 0.31 3 132 0.13 3 145 0.33 150 3 79 0.00 3 92 0.46 3 97 –0.35 3 106 0.39 300 2 159 0.00 2 186 –0.08 2 194 0.16 2 214 -0.07 600 2 79 0.00 2 92 0.46 2 97 –0.35 2 106 0.39 1200 1 159 0.00 1 186 –0.08 1 194 0.16 1 214 -0.07 2400 1 79 0.00 1 92 0.
PAGE 761
Section 19 Serial Communication Interface with FIFO (SCIF) Table 19.4 Bit Rates and SCBRR Settings in Synchronous Mode Pφ (MHz) Bit Rate (bits/s) 5 n N 8 16 28.7 30 33 n N n N n N n N n N 110 — — — — — — — — — — — — 250 3 77 3 124 3 249 — — — — — — 500 3 38 2 249 3 124 3 223 3 233 3 255 1k 2 77 2 124 2 249 3 111 3 116 3 125 2.
PAGE 762
Section 19 Serial Communication Interface with FIFO (SCIF) Table 19.5 indicates the maximum bit rates in asynchronous mode when the baud rate generator is used. Tables 19.6 and 19.7 list the maximum rates for external clock input. Table 19.5 Maximum Bit Rates for Various Frequencies with Baud Rate Generator (Asynchronous Mode) Settings Pφ (MHz) Maximum Bit Rate (bits/s) n N 5 156250 0 0 4.9152 153600 0 0 8 250000 0 0 9.8304 307200 0 0 12 375000 0 0 14.
PAGE 763
Section 19 Serial Communication Interface with FIFO (SCIF) Table 19.6 Maximum Bit Rates with External Clock Input (Asynchronous Mode) Pφ (MHz) External Input Clock (MHz) Maximum Bit Rate (bits/s) 5 1.2500 78125 4.9152 1.2288 76800 8 2.0000 125000 9.8304 2.4576 153600 12 3.0000 187500 14.7456 3.6864 230400 16 4.0000 250000 19.6608 4.9152 307200 20 5.0000 312500 24 6.0000 375000 24.576 6.1440 384000 28.7 7.1750 448436 30 7.5000 468750 33 8.25 515625 Table 19.
PAGE 764
Section 19 Serial Communication Interface with FIFO (SCIF) 19.3.9 FIFO Control Register (SCFCR) The FIFO control register (SCFCR) resets the quantity of data in the transmit and receive FIFO registers, sets the trigger data quantity, and contains an enable bit for loop-back testing. SCFCR can always be read and written to by the CPU. It is initialized to H'0000 by a power-on reset. Bit Bit Name Initial value R/W Description 15 to 11 — All 0 R Reserved These bits are always read as 0.
PAGE 765
Section 19 Serial Communication Interface with FIFO (SCIF) Bit Bit Name Initial value R/W Description 7 RTRG1 0 R/W Receive FIFO Data Trigger 6 RTRG0 0 R/W Set the quantity of receive data which sets the receive data full (RDF) flag in the serial status register (SCFSR). The RDF flag is set when the quantity of receive data stored in the receive FIFO register (SCFRDR) is increased more than the set trigger number shown below.
PAGE 766
Section 19 Serial Communication Interface with FIFO (SCIF) Bit Bit Name Initial value R/W Description 2 TFRST 0 R/W Transmit FIFO Data Register Reset Disables the transmit data in the transmit FIFO data register and resets the data to the empty state. 0: Reset operation disabled* 1: Reset operation enabled Note: * Reset operation is executed by a power-on reset.
PAGE 767
Section 19 Serial Communication Interface with FIFO (SCIF) 19.3.10 FIFO Data Count Register (SCFDR) SCFDR is a 16-bit register which indicates the quantity of data stored in the transmit FIFO data register (SCFTDR) and the receive FIFO data register (SCFRDR). It indicates the quantity of transmit data in SCFTDR with the upper 8 bits, and the quantity of receive data in SCFRDR with the lower 8 bits. SCFDR can always be read by the CPU. SCFDR is initialized to H'0000 by a power on reset.
PAGE 768
Section 19 Serial Communication Interface with FIFO (SCIF) Bit Bit Name Initial value R/W Description 15 to 8 — All 0 R Reserved These bits are always read as 0. The write value should always be 0. 7 RTSIO 0 R/W RTS Port Input/Output Indicates the input or output of RTS pin. When RTS pin is used as port outputting the RTSDT bit, the MCE bit of FIFO control register (SCFCR) should be set to 0.
PAGE 769
Section 19 Serial Communication Interface with FIFO (SCIF) Bit Bit Name Initial value R/W 3 SCKIO 0 R/W Description SCK Port Input/Output Indicates the input or output of SCK pin. When SCK pin is used as port outputting the SCKDT bit, the CKE1, CKE0 bit of serial control register (SCSCR) should be set to 0. 0: Not output the SCKDT bit to SCK pin 1: Output the SCKDT bit to SCK pin 2 SCKDT 0 R/W SCK Port Data Indicates the data of SCK pin used as port. Input/output is specified by SCKIO bit.
PAGE 770
Section 19 Serial Communication Interface with FIFO (SCIF) 19.3.12 Line Status Register (SCLSR) The CPU can always read or write to SCLSR, but cannot write 1 to the ORER flag. This flag can be cleared to 0 only if it has first been read (after being set to 1). SCLSR is initialized to H'0000 by a power-on reset. Bit Bit Name Initial value R/W Description 15 to 1 — All 0 R Reserved These bits are always read as 0. The write value should always be 0.
PAGE 771
Section 19 Serial Communication Interface with FIFO (SCIF) 19.4 Operation 19.4.1 Overview For serial communication, the SCIF has an asynchronous mode in which characters are synchronized individually, and a synchronous mode in which communication is synchronized with clock pulses. The SCIF has a 16-byte FIFO buffer for both transmit and receive operations, reducing the overhead of the CPU, and enabling continuous high-speed communication. Moreover, it has RTS and CTS signals as modem control signals.
PAGE 772
Section 19 Serial Communication Interface with FIFO (SCIF) Table 19.8 SCSMR Settings and SCIF Communication Formats SCSMR Settings SCIF Communication Format Bit 7 Bit 6 Bit 5 Bit 3 C/A CHR PE STOP Mode Data Length Parity Bit Stop Bit Length 0 8 bits Not set 1 bit 0 0 0 Asynchronous 1 1 2 bits 0 Set 1 1 0 2 bits 0 7 bits Not set 1 1 * 0 * * 1 bit 2 bits Set 1 1 1 bit 1 bit 2 bits Synchronous 8 bits Not set None Note: *: Don't care Table 19.
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Section 19 Serial Communication Interface with FIFO (SCIF) 19.4.2 Operation in Asynchronous Mode In asynchronous mode, each transmitted or received character begins with a start bit and ends with a stop bit. Serial communication is synchronized one character at a time. The transmitting and receiving sections of the SCIF are independent, so full duplex communication is possible.
PAGE 774
Section 19 Serial Communication Interface with FIFO (SCIF) Transmit/Receive Formats: Table 19.10 lists the 8 communication formats that can be selected in asynchronous mode. The format is selected by settings in the serial mode register (SCSMR). Table 19.
PAGE 775
Section 19 Serial Communication Interface with FIFO (SCIF) Transmitting and Receiving Data: • SCIF Initialization (Asynchronous Mode) Before transmitting or receiving, clear the TE and RE bits to 0 in the serial control register (SCSCR), then initialize the SCIF as follows. When changing the operation mode or the communication format, always clear the TE and RE bits to 0 before following the procedure given below. Clearing TE to 0 initializes the transmit shift register (SCTSR).
PAGE 776
Section 19 Serial Communication Interface with FIFO (SCIF) Figure 19.3 shows a sample flowchart for initializing the SCIF. Start of initialization [1] Set the clock selection in SCSCR. Be sure to clear bits TIE, RIE, TE, and RE to 0. Clear TE and RE bits in SCSCR to 0 [2] Set the data transfer format in SCSMR. Set TFRST and RFRST bits in SCFCR to 1 [3] Write a value corresponding to the bit rate into SCBRR. (Not necessary if an external clock is used.
PAGE 777
Section 19 Serial Communication Interface with FIFO (SCIF) • Transmitting Serial Data (Asynchronous Mode) Figure 19.4 shows a sample flowchart for serial transmission. Use the following procedure for serial data transmission after enabling the SCIF for transmission.
PAGE 778
Section 19 Serial Communication Interface with FIFO (SCIF) In serial transmission, the SCIF operates as described below. 1. When data is written into the transmit FIFO data register (SCFTDR), the SCIF transfers the data from SCFTDR to the transmit shift register (SCTSR) and starts transmitting. Confirm that the TDFE flag in the serial status register (SCFSR) is set to 1 before writing transmit data to SCFTDR. The number of data bytes that can be written is (16 – transmit trigger setting). 2.
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Section 19 Serial Communication Interface with FIFO (SCIF) Figure 19.5 shows an example of the operation for transmission. Start bit 1 Serial data Data 0 D0 D1 Parity Stop Start bit bit bit D7 0/1 1 0 Data D0 D1 Parity Stop bit bit D7 0/1 1 1 Idle state (mark state) TDFE TEND TXI interrupt request Data written to SCFTDR and TDFE flag read as 1 then cleared to 0 by TXI interrupt handler TXI interrupt request One frame Figure 19.
PAGE 780
Section 19 Serial Communication Interface with FIFO (SCIF) • Receiving Serial Data (Asynchronous Mode) Figures 19.7 and 19.8 show a sample flowchart for serial reception. Use the following procedure for serial data reception after enabling the SCIF for reception.
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Section 19 Serial Communication Interface with FIFO (SCIF) Error handling No ORER = 1? Yes Overrun error handling No ER = 1? Yes [1] Whether a framing error or parity error has occurred in the receive data that is to be read from SCFRDR can be ascertained from the FER and PER bits in SCFSR. [2] When a break signal is received, receive data is not transferred to SCFRDR while the BRK flag is set.
PAGE 782
Section 19 Serial Communication Interface with FIFO (SCIF) In serial reception, the SCIF operates as described below. 1. The SCIF monitors the transmission line, and if a 0 start bit is detected, performs internal synchronization and starts reception. 2. The received data is stored in SCRSR in LSB-to-MSB order. 3. The parity bit and stop bit are received. After receiving these bits, the SCIF carries out the following checks. A. Stop bit check: The SCIF checks whether the stop bit is 1.
PAGE 783
Section 19 Serial Communication Interface with FIFO (SCIF) 1 Start bit Serial data 0 Data D0 D1 Parity Stop Start bit bit bit D7 0/1 1 0 Data D0 D1 Parity Stop bit bit D7 0/1 0 0/1 RDF FER RXI interrupt request One frame Data read and RDF flag read as 1 then cleared to 0 by RXI interrupt handler ERI interrupt request generated by receive error Figure 19.9 Example of SCIF Receive Operation (8-Bit Data, Parity, One Stop Bit) 5.
PAGE 784
Section 19 Serial Communication Interface with FIFO (SCIF) Figure 19.11 shows the general format in synchronous serial communication. One unit of transfer data (character or frame) * * Synchronization clock LSB Bit 0 Serial data MSB Bit 1 Don’t care Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Don't care Note: * High except in continuous transfer Figure 19.
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Section 19 Serial Communication Interface with FIFO (SCIF) Figure 19.12 shows a sample flowchart for initializing the SCIF. Start of initialization Clear TE and RE bits in SCSCR to 0 [1] [2] Set the data transfer format in SCSMR. Set TFRST and RFRST bits in SCFCR to 1 to clear the FIFO buffer [3] Set the CKE1 and CKE0 bits. [4] Write a value corresponding to the bit rate into SCBRR. This is not necessary if an external clock is used.
PAGE 786
Section 19 Serial Communication Interface with FIFO (SCIF) • Transmitting Serial Data (Synchronous Mode) Figure 19.13 shows a sample flowchart for transmitting serial data. Use the following procedure for serial data transmission after enabling the SCIF for transmission. Start of transmission [1] Read TDFE flag in SCFSR TDFE = 1? Read SCFSR and check that the TDFE flag is set to 1, then write transmit data to SCFTDR, and clear the TDFE flag to 0.
PAGE 787
Section 19 Serial Communication Interface with FIFO (SCIF) In serial transmission, the SCIF operates as described below. 1. When data is written into the transmit FIFO data register (SCFTDR), the SCIF transfers the data from SCFTDR to the transmit shift register (SCTSR) and starts transmitting. Confirm that the TDFE flag in the serial status register (SCFSR) is set to 1 before writing transmit data to SCFTDR. The number of data bytes that can be written is (16 – transmit trigger setting). 2.
PAGE 788
Section 19 Serial Communication Interface with FIFO (SCIF) • Receiving Serial Data (Synchronous Mode) Figure 19.15 shows a sample flowchart for receiving serial data. When switching from asynchronous mode to synchronous mode without SCIF initialization, make sure that ORER, PER, and FER are cleared to 0. [1] Receive error handling: Start of reception Read the ORER flag in SCLSR to identify any error, perform the appropriate error handling, then clear the ORER flag to 0.
PAGE 789
Section 19 Serial Communication Interface with FIFO (SCIF) Error handling No ORER = 1? Yes Overrun error handling Clear ORER flag in SCLSR to 0 End Figure 19.16 Sample Flowchart for Receiving Serial Data (2) Rev. 4.00 Sep.
PAGE 790
Section 19 Serial Communication Interface with FIFO (SCIF) In serial reception, the SCIF operates as described below. 1. The SCIF synchronizes with serial clock input or output and starts the reception. 2. Receive data is shifted into SCRSR in order from the LSB to the MSB. After receiving the data, the SCIF checks the receive data can be loaded from SCRSR into SCFRDR or not. If this check is passed, the SCIF stores the received data in SCFRDR.
PAGE 791
Section 19 Serial Communication Interface with FIFO (SCIF) • Transmitting and Receiving Serial Data Simultaneously (Synchronous Mode) Figure 19.18 shows a sample flowchart for transmitting and receiving serial data simultaneously. Use the following procedure for the simultaneous transmission/reception of serial data, after enabling the SCIF for transmission/reception.
PAGE 792
Section 19 Serial Communication Interface with FIFO (SCIF) 19.5 SCIF Interrupts and DMAC The SCIF has four interrupt sources: transmit-FIFO-data-empty (TXI), receive-error (ERI), receive-data-full (RXI), and break (BRI). Table 19.11 shows the interrupt sources and their order of priority. The interrupt sources are enabled or disabled by means of the TIE, RIE, and REIE bits in SCSCR. A separate interrupt request is sent to the interrupt controller for each of these interrupt sources.
PAGE 793
Section 19 Serial Communication Interface with FIFO (SCIF) Table 19.11 SCIF Interrupt Sources Interrupt Source Description DMAC Activation Priority on Reset Release ERI Interrupt initiated by receive error (ER) Not possible High RXI Interrupt initiated by receive data FIFO full (RDF) or Possible data ready (DR)* BRI Interrupt initiated by break (BRK) or overrun error (ORER) Not possible TXI Interrupt initiated by transmit FIFO data empty (TDFE) Possible Note: 19.
PAGE 794
Section 19 Serial Communication Interface with FIFO (SCIF) The number of receive data bytes in SCFRDR can be found from the lower 8 bits of the FIFO data count register (SCFDR). 3. Break Detection and Processing Break signals can be detected by reading the RxD pin directly when a framing error (FER) is detected. In the break state the input from the RxD pin consists of all 0s, so the FER flag is set and the parity error flag (PER) may also be set.
PAGE 795
Section 19 Serial Communication Interface with FIFO (SCIF) 16 clocks 8 clocks 0 1 2 3 4 5 6 7 8 9 10 1112 1314 15 0 1 2 3 4 5 6 7 8 9 10 1112 1314 15 0 1 2 3 4 5 Base clock –7.5 clocks Receive data (RxD) +7.5 clocks Start bit D0 D1 Synchronization sampling timing Data sampling timing Figure 19.19 Receive Data Sampling Timing in Asynchronous Mode The receive margin in asynchronous mode can therefore be expressed as shown in equation 1. Equation 1: M = (0.5 - D - 0.5 1 ) = (L - 0.
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Section 19 Serial Communication Interface with FIFO (SCIF) 6. When Using the DMAC  Using an External Clock in Chock Synchronous Mode: When using an external clock as the synchronization clock, after SCFTDR is updated by the DMAC, an external clock should be input after at least five peripheral clock cycles. A malfunction may occur when the transfer clock is input within four cycles after updating SCFTDR (figure 19.20).
PAGE 797
Section 20 USB Function Module Section 20 USB Function Module 20.
PAGE 798
Section 20 USB Function Module • Power mode: Self-powered, bus-powered 20.1.1 Block Diagram Internal peripheral bus USB function module Status and control registers Interrupt requests DMA transfer requests UDC To transceiver FIFO (288 bytes) Clock (48 MHz) UDC: USB device controller Figure 20.1 Block Diagram of USB 20.2 Pin Configuration Table 20.
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Section 20 USB Function Module In on-chip transceiver bypass mode (the XVEROFF bit of the USBXVERCR register is 1), a Philips PDIUSBP11 Series transceiver or compatible product can be connected (when using a compatible product, carry out evaluation and investigation with the manufacturer supplying the transceiver beforehand). 20.3 Register Descriptions The USB has the following registers.
PAGE 800
Section 20 USB Function Module 20.3.1 USB Interrupt Flag Register 0 (USBIFR0) Together with USB interrupt flag registers 1 (USBIFR1) and 2 (USBIFR2), USBIFR0 indicates interrupt status information required by the application. When an interrupt occurs, the corresponding bit is set to 1 and an interrupt request is sent to the CPU according to the combination with USB interrupt enable register 0 (USBIER0). Clearing is performed by writing 0 to the bit to be cleared, and 1 to the other bits.
PAGE 801
Section 20 USB Function Module Bit Bit Name Initial Value R/W Description 2 EP0oTS 0 R/W EP0o Receive Complete This bit is set to 1 when endpoint 0 receives data from the host normally, stores the data in the FIFO buffer, and returns an ACK handshake to the host. 1 EP0iTR 0 R/W EP0i Transfer Request This bit is set if there is no valid transmit data in the FIFO buffer when an IN token for endpoint 0 is received from the host.
PAGE 802
Section 20 USB Function Module Bit Bit Name Initial Value R/W Description 2 EP3TR 0 R/W EP3 Transfer Request This bit is set if there is no valid transmit data in the FIFO buffer when an IN token for endpoint 3 is received from the host. A NACK handshake is returned to the host until data is written to the FIFO buffer and packet transmission is enabled. 1 EP3TS 0 R/W EP3 Transmit Complete This bit is set when data is transmitted to the host from endpoint 3 and an ACK handshake is returned.
PAGE 803
Section 20 USB Function Module Bit Bit Name Initial Value R/W Description 1 CFGV 0 R Configuration Value Status bit for monitoring the configuration value. This is a status bit and cannot be cleared. 0 SETC 0 R/W SET_CONFIGURATION Request Detection This bit is set to 1 when the SET_CONFIGURATION request is received. 20.3.4 USB Interrupt Select Register 0 (USBISR0) USBISR0 selects the vector numbers of the interrupt requests indicated in USB interrupt flag register 0 (USBIFR0).
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Section 20 USB Function Module 20.3.5 USB Interrupt Select Register 1 (USBISR1) USBISR1 selects the vector numbers of the interrupt requests indicated in USB interrupt flag register 1 (USBIFR1). If the USB issues an interrupt request to the INTC when the corresponding bit in USBISR1 is cleared to 0, the interrupt will be USI0 (USB interrupt 0). If the USB issues an interrupt request to the INTC when the corresponding bit in USBISR1 is set to 1, the interrupt will be USI1 (USB interrupt 1).
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Section 20 USB Function Module 20.3.7 USB Interrupt Enable Register 1 (USBIER1) USBIER1 enables the interrupt requests indicated in USB interrupt flag register 1 (USBIFR1). When an interrupt flag is set while the corresponding bit in USBIER1 is set to 1, an interrupt request is sent to the CPU. The interrupt vector number is decided by the contents of USB interrupt select register 1 (USBISR1). USBIER1 is initialized to H'00 by a power-on reset.
PAGE 806
Section 20 USB Function Module 20.3.9 USBEP0i Data Register (USBEPDR0i) USBEPDR0i is an 8-byte transmit FIFO buffer for endpoint 0, holding one packet of transmit data for control IN. Transmit data is fixed by writing one packet of data and setting the EP0iPKTE bit in the trigger register. When an ACK handshake is returned from the host after the data has been transmitted, bit 0 (EP0iTS) in USB interrupt flag register 0 is set. USBEP0I can be initialized by means of the EP0iCLR bit in USBFCLR.
PAGE 807
Section 20 USB Function Module 20.3.11 USBEP0s Data Register (USBEPDR0s) USBEPDR0s is an 8-byte FIFO buffer specifically for endpoint 0 setup command reception and stores an 8-byte command data that is sent in the setup stage. USBEPDR0s receives only commands requiring processing on the microcomputer (firmware) side. Commands that this module automatically processes are not stored. When command data is received normally, the SETUPTS bit in USB interrupt flag register 0 is set.
PAGE 808
Section 20 USB Function Module 20.3.13 USBEP2 Data Register (USBEPDR2) USBEPDR2 is a 128-byte transmit FIFO buffer for endpoint 2. USBEPDR2 has a dual-buffer configuration, and has a capacity of twice the maximum packet size. When transmit data is written to this FIFO buffer and the EP2PKTE bit in the USB trigger register is set, one packet of transmit data is fixed, and the dual buffer is switched over. Transmit data for this FIFO buffer can be transferred by DMA (dual address transfer byte by byte).
PAGE 809
Section 20 USB Function Module 20.3.16 USBEP1 Receive Data Size Register (USBEPSZ1) USBEPSZ1 indicates, in bytes, the amount of data received from the host by endpoint 1. The endpoint 1 FIFO buffer has a dual-FIFO configuration. The receive data size indicated by this register refers to the currently selected FIFO (that can be read by CPU). USBEPSZ1 can be initialized to H'00 by a power-on reset.
PAGE 810
Section 20 USB Function Module Bit Bit Name Initial Value R/W Description 2 EP0sRDFN 0 W EP0s Read Complete Write 1 to this bit after EP0s command FIFO data has been read. Writing 1 to this bit enables transmission/reception of data in the following data stage. A NACK handshake is returned in response to transmit/receive requests from the host in the data stage until 1 is written to this bit.
PAGE 811
Section 20 USB Function Module Bit Bit Name Initial Value R/W Description 4 EP2DE 0 R EP2 Data Present This bit is set when the endpoint 2 FIFO buffer contains valid data 3 to 1  All 0 R Reserved The write value should always be 0. 0 EP0iDE 0 R EP0i Data Present This bit is set when the endpoint 0 transmit FIFO buffer contains valid data. 20.3.19 USBFIFO Clear Register (USBFCLR) USBFCLR is provided to initialize the FIFO buffers for each endpoint.
PAGE 812
Section 20 USB Function Module Bit Bit Name Initial Value R/W Description 0 EP0iCLR 0 W EP0i Clear When 1 is written to this bit, the endpoint 0 transmit FIFO buffer is initialized. 20.3.20 USBDMA Transfer Setting Register (USBDMAR) USBDMAR enables DMA transfer between the endpoint 1 and endpoint 2 data registers and memory by means of the on-chip DMA controller (DMAC). Dual address transfer is performed with the transfer size of only on a per-byte basis.
PAGE 813
Section 20 USB Function Module Bit Bit Name Initial Value R/W Description 0 EP1DMAE 0 R/W Endpoint 1 DMA Transfer Enable When this bit is set, DMA transfer is enabled from the endpoint 1 receive FIFO buffer to memory. If there is at least one byte of receive data in the FIFO buffer, a transfer request is asserted for the DMA controller. In DMA transfer, when all the received data is read, EP1 is read automatically and the completion trigger operates.
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Section 20 USB Function Module Bit Bit Name Initial Value R/W Description 2 EP2STL 0 R/W EP2 Stall When this bit is set to 1, endpoint 2 is placed in the stall state. 1 EP1STL 0 R/W EP1 Stall When this bit is set to 1, endpoint 1 is placed in the stall state. 0 EP0STL 0 R/W EP0 Stall When this bit is set to 1, endpoint 0 is placed in the stall state. 20.3.
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Section 20 USB Function Module 20.3.23 USB Bus Power Control Register (USBCTRL) This LSI can operate using a bus power control method. For details of the bus power control method, see section 20.9, USB Bus Power Control Method. USBCTRL can be initialized to H'00 by a power-on reset. Bit Bit Name Initial Value R/W 7 to 2  All 0 R Description Reserved The write value should always be 0. 1 SUSPEND 0 R/W USB Suspend Enable Allows an interrupt by the USB suspend signal or awake signal detection.
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Section 20 USB Function Module 20.4 Operation 20.4.
PAGE 817
Section 20 USB Function Module Also, in applications that require connection detection regardless of D+ pull-up control, detection should be carried out using IRQx or a general input port. For details, see section 20.8, Example of USB External Circuitry. 20.4.2 Cable Disconnection USB function Application Cable connected VBUS pin = 1 USB cable disconnection VBUS pin = 0 UDC core reset End Figure 20.3 Cable Disconnection Operation The flowchart in figure 20.
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Section 20 USB Function Module 20.4.3 Control Transfer Control transfer consists of three stages: setup, data (not always included), and status (figure 20.4). The data stage comprises a number of bus transactions. Operation flowcharts for each stage are shown below. Setup stage Control IN Control OUT No data Data stage SETUP(0) IN(1) IN(0) DATA0 DATA1 DATA0 SETUP(0) OUT(1) OUT(0) DATA0 DATA1 DATA0 Status stage ... ...
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Section 20 USB Function Module Setup Stage: USB function Application SETUP token reception Receive 8-byte command data in EP0s Command to be processed by application? No Automatic processing by this module Yes Set setup command reception complete flag (USBIFR0/SETUP TS = 1) To data stage Interrupt request Clear SETUP TS flag (USBIFR0/SETUP TS = 0) Clear EP0i FIFO (UFCLR/EP0iCLR = 1) Clear EP0o FIFO (UFCLR/EP0oCLR = 1) Read 8-byte data from EP0s Decode command data Determine data stage directio
PAGE 820
Section 20 USB Function Module Data Stage (Control-IN): The application first analyzes command data from the host in the setup stage, and determines the subsequent data stage direction. If the result of command data analysis is that the data stage is in-transfer, one packet of data to be sent to the host is written to the FIFO. If there is more data to be sent, this data is written to the FIFO after the data written first has been sent to the host (USBIFR0/EP0iTS = 1).
PAGE 821
Section 20 USB Function Module Data Stage (Control-OUT): The application first analyzes command data from the host in the setup stage, and determines the subsequent data stage direction. If the result of command data analysis is that the data stage is OUT-transfer, the application waits for data from the host, and after data is received (USBIFR0/EP0oTS = 1), reads data from the FIFO.
PAGE 822
Section 20 USB Function Module Status Stage (Control-IN): The control-IN status stage starts with an OUT token from the host. The application receives 0-byte data from the host, and ends control transfer.
PAGE 823
Section 20 USB Function Module Status Stage (Control-OUT): The control-OUT status stage starts with an IN token from the host. When an IN token is received at the start of the status stage, there is not yet any data in the EP0iFIFO, and so an EP0i transfer request interrupt is generated. The application recognizes from this interrupt that the status stage has started. Next, in order to transmit 0-byte data to the host, 1 is written to the EP0i packet enable bit but no data is written to the EP0i FIFO.
PAGE 824
Section 20 USB Function Module 20.4.4 EP1 Bulk-OUT Transfer (Dual FIFOs) EP1 has two 64-byte FIFOs, but the user can perform data reception and receive data reads without being aware of this dual-FIFO configuration. When one FIFO is full after reception is completed, the USBIFR0/EP1 FULL bit is set. After the first receive operation into one of the FIFOs when both FIFOs are empty, the other FIFO is empty, and so the next packet can be received immediately.
PAGE 825
Section 20 USB Function Module USB function Application OUT token reception Space in EP1 FIFO? No NACK Yes Data reception from host ACK Interrupt request Set EP1 FIFO full status (USBIFR0/EP1 FULL = 1) Read USBEP1 receive data size register (USBEPSZ1) Read data from USBEP1 data register (USBEPDR1) Write 1 to EP1 read complete bit (USBTRG/EP1 RDFN = 1) Both EP1 FIFOs empty? No Interrupt request Yes Clear EP1 FIFO full status (USBIFR0/EP1 FULL = 0) Figure 20.
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Section 20 USB Function Module 20.4.5 EP2 Bulk-IN Transfer (Dual FIFOs) EP2 has two 64-byte FIFOs, but the user can perform data transmission and transmit data writes without being aware of this dual-FIFO configuration. However, one data write is performed for one FIFO. For example, even if both FIFOs are empty, it is not possible to perform EP2/PKTE at one time after consecutively writing 128 bytes of data. EP2/PKTE must be performed for each 64byte write.
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Section 20 USB Function Module USB function Application IN token reception Valid data in EP2 FIFO? Clear EP2 transfer request flag (USBIFR0/EP2 TR = 0) Interrupt request No NACK Yes Enable EP2 FIFO empty interrupt (USBIER0/EP2 EMPTY = 1) Data transmission to host ACK Space in EP2 FIFO? Yes Set EP2 empty status (USBIFR0/EP2 EMPTY = 1) Interrupt request USBIER0/EP2 EMPTY interrupt No Clear EP2 empty status (USBIFR0/EP2 EMPTY = 0) Write one packet of data to USBEP2 data register (USBEPDR2) W
PAGE 828
Section 20 USB Function Module 20.4.
PAGE 829
Section 20 USB Function Module 20.5 Processing of USB Standard Commands and Class/Vendor Commands 20.5.1 Processing of Commands Transmitted by Control Transfer A command transmitted from the host by control transfer may require decoding and execution of command processing on the application side. Whether command decoding is required on the application side is indicated in table 20.2 below. Table 20.
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Section 20 USB Function Module 20.6 Stall Operations This section describes stall operations in the USB function module. There are two cases in which the USB function module stall function is used: • When the application forcibly stalls an endpoint for some reason • When a stall is performed automatically within the USB function module due to a USB specification violation The USB function module has internal status bits that hold the status (stall or non-stall) of each endpoint.
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Section 20 USB Function Module (1) Transition from normal operation to stall (1-1) USB Internal status bit 0 USBEPSTL 0→1 1. 1 written to USBEPSTL by application USBEPSTL 1 1. IN/OUT token received from host 2. USBEPSTL referenced USBEPSTL 1 1. 1 set in USBEPSTL 2. Internal status bit set to 1 3.
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Section 20 USB Function Module 20.6.2 Automatic Stall by USB Function Module When a stall setting is made with the Set Feature command, or in the event of a USB specification violation, the USB function module automatically sets the internal status bit for the relevant endpoint without regard to USBEPSTL register, and returns a stall handshake (1-1 in figure 20.14).
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Section 20 USB Function Module (1) Transition from normal operation to stall (1-1) STALL handshake Internal status bit 0→1 USBEPSTL 0 To (2-1) or (3-1) 1. In case of USB specification violation, etc., USB function module stalls endpoint automatically (2) When transaction is performed when internal status bit is set, and Clear Feature is sent (2-1) Transaction request Internal status bit 1 USBEPSTL 0 Internal status bit 1 USBEPSTL 0 1. USBEPSTL cleared to 0 by application 2.
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Section 20 USB Function Module 20.7 DMA Transfer This module allows DMAC transfer for endpoints 1 and 2, excluding transfer of word and longword. If endpoint 1 contains at least one byte of valid receive data, a DMA transfer request is issued to endpoint 1. If there is no valid data in endpoint 2, a DMA transfer request is issued to endpoint 2. When EP1 DMAE in the USBDMA setting register is set to 1 to allow DMA transfer, 0-length data received for endpoint 1 is ignored.
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Section 20 USB Function Module 20.7.2 DMA Transfer for Endpoint 2 When the transmitted data for EP2 is transferred by DMA when the data on one side of FIFO (64 bytes) becomes full an equivalent processing of writing 1 to the USBTRG/PKTE bit is automatically performed in the module. Therefore, when data to be transferred is a multiple of 64 bytes, writing 1 to the USBTRG/PKTE bit is not necessary.
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Section 20 USB Function Module 20.8 Example of USB External Circuitry USB Transceiver: When an on-chip transceiver is not used, a USB transceiver IC (such as a PDIUSBP11) must be connected externally. The USB transceiver manufacturer should be consulted concerning the recommended circuit from the USB transceiver to the USB connector, etc.
PAGE 837
Section 20 USB Function Module This LSI IC that allows voltage application when the system (LSI) power is off. General output port, etc. USB module VBUS 3.3 V USB connector IC that allows voltage application when the system (LSI) power is off. VBUS 5V D+ D+ D- D- GND Note: Operation cannot be guaranteed by this example. When the system requires countermeasures against external surge or ESD noise, use the protection diode or noise canceller. USB cable Figure 20.
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Section 20 USB Function Module This LSI IC that allows voltage application when the system (LSI) power is off. General output port, etc. USB module VBUS 3.3 V IC that allows voltage application when the system (LSI) power is off. TXENL TXDMNS TXDPLS XVDATA SPEED OE VMO VPO VBUS 5V D+ D- GND RCV DPLS VP DMNS VM SUSPND USB connector + - USB cable SUSPND PDIUSBP11 etc Note: Operation cannot be guaranteed by this example.
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Section 20 USB Function Module 20.9 USB Bus Power Control Method 20.9.1 USB Bus Power Control Operation This LSI can operate using a USB bus power control method. The following describes notes on the LSI using the USB bus power control method. Changing to High-Power Function: According to the USB standard, the startup operation (from connecting cables to completing enumeration) is handled as a low-power function.
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Section 20 USB Function Module This LSI IRQ1 0 IRQ1_SUSPEND IRQ1 interrupt 1 USB suspend signal (internal signal) S Q USBCTRL/ SUSPEND IRQ0_AWAKE USBIFR2/ SUSPS IRQ0 IRQ0 interrupt 0 Interrupt controller (INTC) 1 AWAKE signal (internal signal) S Q USBIFR2/ AWAKE Figure 20.
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Section 20 USB Function Module Normal routine USIHP interrupt routine Power On Reset Set STBCR4/MSTP46 to 1 (exit USB module stop mode) Set USBCTRL/PWMD to 1 (set to bus power control method) Set IPRC/IRQ0 of INTC to 15 (set the priority of IRQ0 to 15) Set IPRC/IRQ1 of INTC to 14 (set the priority of IRQ1 to 14) Clear ICR1/IRQ00S and IRQ01S of INTC to 0 (set the IRQ0 falling edge detection) Clear ICR1/IRQ10S and IRQ11S of INTC to 0 (set the IRQ1 falling edge detection) Clear ICR1/IRQE of INTC to 0 (IRQ i
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Section 20 USB Function Module IRQ1 interrupt routine Normal routine Normal state No Yes IRQ1 interrupt? Clear IRR0/IRQ1R of INTC Save SSR and SPC to memory Set SR/I[3:0] to the IRQ1 priority IRR0/IRQ0R of INTC? 0 1 Clear IRR0/IRQ0R of INTC Set STBCR/STBY Clear USBIFR2/SUSPS and AWAKE (clear detection of USB suspend and AWAKE signals) SLEEP instruction RTE instruction Normal operation Standby mode Figure 20.22 Sample Flowchart for Changing the State from USB Suspend to Standby Rev. 4.
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Section 20 USB Function Module Normal routine IRQ1interrupt routine IRQ0 interrupt routine Normal state or standby mode Yes No IRQ0 interrupt? Clear IRR0/IRQ0R of INTC Set SR/I[3:0] to the IRQ0 priority 1 IRR0/IRQ1R of INTC? 0 Clear USBIFR2/SUSPS and AWAKE Clear IRR0/IRQ1R of INTC RTE instruction Clear USBIFR2/SUSPS and AWAKE Restore SSR and SPC from memory RTE instruction RTE instruction Normal operation Figure 20.23 Sample Flowchart for AWAKE Rev. 4.00 Sep.
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Section 20 USB Function Module 20.10 Notes on Usage 20.10.1 Receiving Setup Data Note that the following when 8-byte setup data is received by USBEPDR0s. 1. 2. The USB must always receive the setup command. Therefore, writing from the USB bus has priority over reading from the CPU. When the USB starts receiving the next setup command while the CPU is reading data after data reception, the USB forcibly invalidates reading from the CPU to start writing.
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Section 20 USB Function Module 20.10.4 Assigning Interrupt Source for EP0 Interrupt sources (bits 0 to 3) for EP0 that are assigned to USBIFR0 of this module must be assigned to the same interrupt pin using USBISR0. 20.10.5 Clearing FIFO when Setting DMA Transfer Clearing the endpoint 1 data register (USBEPDR1) is impossible when DMA transfer is enabled (USBDMAR/EP1DMAE = 1) for endpoint 1. To clear this register, cancel DMA transfer. 20.10.
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Section 20 USB Function Module TR interrupt routine Clear TR flag, Write transmit data, and TRG/PKTE CPU Host USB TR interrupt routine IN token IN token IN token Check NAK Check NAK NAK NAK Set TR flag Data transmission Set TR flag (flag is set again) Figure 20.24 Timing for Setting the TR Interrupt Flag Rev. 4.00 Sep.
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Section 21 A/D Converter Section 21 A/D Converter This LSI includes a 10-bit successive-approximation A/D converter allowing selection of up to eight analog input channels. The A/D converter is composed of two independent modules, A/D0 and A/D1. 21.1 Features A/D converter features are listed below. • 10-bit resolution • Eight input channels (4 channels × 2) • High-speed conversion  Conversion time: maximum 4.4 µs per channel (in single mode, 146-state conversion (Typ.
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Section 21 A/D Converter 21.1.1 Block Diagram Figure 21.1 shows a block diagram of the A/D converter. A/D converter 0 ADCSR0 ADDRD0 AVSS ADDRC0 10 bit A/D ADDRA0 AVCC ADDRB0 Successive approxi- mation register Peripheral data bus Bus interface bus AVcc and AVss for both A/D modules are common pins in the chip.
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Section 21 A/D Converter 21.1.2 Input Pins Table 21.1 summarizes the A/D converter's input pins. The eight analog input pins are divided into two groups: A/D0 (AN0 to AN3), and A/D1 (AN4 to AN7). AVCC and AVSS are the power supply inputs for the analog circuits in the A/D converter. AVCC also functions as the A/D converter reference voltage pin. AVSS also functions as the A/D converter reference ground pin. Table 21.
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Section 21 A/D Converter 21.1.3 Register Configuration The A/D converter's registers are summarized below. • • • • • • • • • • • A/D0 data register A (ADDRA0) A/D0 data register B (ADDRB0) A/D0 data register C (ADDRC0) A/D0 data register D (ADDRD0) A/D0 control/status register (ADCSR0) A/D1 data register A (ADDRA1) A/D1 data register B (ADDRB1) A/D1 data register C (ADDRC1) A/D1 data register D (ADDRD1) A/D1 control/status register (ADCSR1) A/D0 A/D1 control register (ADCR) 21.
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Section 21 A/D Converter Table 21.2 Analog Input Channels and A/D Data Registers Analog Input Channel A/D Data Register Module AN0 ADDRA0 A/D0 AN1 ADDRB0 AN2 ADDRC0 AN3 ADDRD0 AN4 ADDRA1 AN5 ADDRB1 AN6 ADDRC1 AN7 ADDRD1 21.2.2 A/D1 A/D Control/Status Registers (ADCSR0, ADCSR1) ADCSR is a 16-bit readable/writable register that selects the mode, controls the A/D converter, and enable or disable starting of A/D conversion by external trigger input.
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Section 21 A/D Converter Bit Bit Name Initial Value R/W Description 14 ADIE 0 R/W A/D Interrupt Enable Enables or disables the interrupt (ADI) requested at the end of A/D conversion. Set the ADIE bit while A/D conversion is not being made. 0: A/D end interrupt request (ADI) is disabled 1: A/D end interrupt request (ADI) is enabled 13 ADST 0 R/W A/D Start Starts or stops A/D conversion. The ADST bit remains set to 1 during A/D conversion.
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Section 21 A/D Converter Bit Bit Name Initial Value R/W Description 10 to 8  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 7 CKS1 0 R/W Clock Select 6 CKS0 1 R/W Selects the A/D conversion time. Clear the ADST bit to 0 before changing the conversion time.
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Section 21 A/D Converter Bit Bit Name Initial Value R/W Description 1 0 CH1 CH0 0 0 R/W R/W Channel Select These bits and the MULTI bit select the analog input channels. Clear the ADST bit to 0 before changing the channel selection. • In the case of ADCSR0 (A/D0) Single mode 00: AN0 01: AN1 10: AN2 11: AN3 • In the case of ADSCR1 (A/D1) Single mode 00: AN4 01: AN5 10: AN6 11: AN7 Note: 21.2.
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Section 21 A/D Converter 21.3 Operation The A/D converter operates by successive approximations with 10-bit resolution. It has three operating modes: single mode, multi mode, and scan mode. 21.3.1 Single Mode Single mode should be selected when only one A/D conversion on one channel is required. A/D conversion starts when the ADST bit is set to 1 by software. The ADST bit remains set to 1 during A/D conversion and is automatically cleared to 0 when conversion ends.
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Section 21 A/D Converter Set* ADIE Set* Set* ADST A/D conversion starts Clear* ADF Channel 0 (AN0) operating Channel 1 (AN1) operating Clear* Waiting Waiting A/D conversion 1 Channel 2 (AN2) operating Waiting Channel 3 (AN3) operating Waiting Waiting A/D conversion result 2 Waiting ADDRA ADDRB Read result A/D conversion result 1 Read result A/D conversion result 2 ADDRC ADDRD Note: * Vertical arrows ( ) indicate instruction execution by software. Figure 21.
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Section 21 A/D Converter Typical operations when three channels in A/D0 (AN0 to AN2) are selected in multi mode are described next. Figure 21.3 shows a timing diagram for this example. 1. Multi mode is selected (MULTI = 1), channel group A/D0 is selected, analog input channels AN0 to AN2 are selected (CH1 = 1, CH0 = 0), and A/D conversion is started (ADST = 1). 2. When A/D conversion of the first channel (AN0) is completed, the result is transferred into ADDRA0. 3.
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Section 21 A/D Converter 21.3.3 Scan Mode Scan mode is useful for monitoring analog inputs in a group of one or more channels. When the ADST bit in the A/D control/status register (ADCSR0 or ADCSR1) is set to 1 by software, A/D conversion starts on the first channel in the group (A/D0 when AN0, A/D1 when AN4). When two or more channels are selected, after conversion of the first channel ends, conversion of the second channel (AN1 or AN5) starts immediately.
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Section 21 A/D Converter Continuous A/D conversion Clear*1 Set*1 ADST Clear*1 ADF Channel 0 (AN0) operating Waiting Waiting A/D conversion 1 Channel 1 (AN1) operating Waiting Channel 2 (AN2) operating Waiting Channel 3 (AN3) operating Waiting Waiting A/D conversion 4 *2 Waiting Waiting A/D conversion 2 A/D conversion 5 Waiting A/D conversion 3 Transfer ADDRA0 A/D conversion result 1 A/D conversion result 4 ADDRB0 A/D conversion result 2 ADDRC0 A/D conversion result 3 ADDRD0 Notes:
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Section 21 A/D Converter 21.3.5 A/D Converter Activation by MTU The A/D converter can be independently activated by an A/D conversion request from the MTU or CSL. To activate the A/D converter by the MTU, set the A/D trigger enable bit (TRGE). After this bit setting has been made, the ADST bit in ADCSR is automatically set to 1 and A/D conversion is started when an A/D conversion request from the MTU occurs.
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Section 21 A/D Converter ADCSR write cycle Pφ Address ADCSR address Write signal Input sampling timing ADF tD tSPL tCONV [Legend] A/D conversion start delay tD : tSPL : Input sampling time tCONV : A/D conversion time Figure 21.5 A/D Conversion Timing Table 21.3 A/D Conversion Time (Single Mode) CKS1 = 1, CKS0 = 1 CKS1 = 1, CKS0 = 1 CKS1 = 1, CKS0 = 1 Symbol Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.
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Section 21 A/D Converter 21.4 Interrupt and DMAC Transfer Request The A/D converter generates an interrupt (ADI0 and ADI1) or DMAC activation signal at the end of A/D conversion. These requests are enabled or disabled by the ADIE bit or the DMASL bit in ADCSR. When the DMAC is activated by an ADI interrupt, the ADF bit in the A/D control/status register (ADCSR0 and ADCSR1) is automatically cleared to 0 when an A/D register is accessed. Table 21.
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Section 21 A/D Converter 21.5 Definitions of A/D Conversion Accuracy The A/D converter compares an analog value input from an analog input channel with its analog reference value and converts it to 10-bit digital data. The absolute accuracy of this A/D conversion is the deviation between the input analog value and the output digital value.
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Section 21 A/D Converter Digital output Ideal A/D conversion characteristic 111 110 (2) Full-scale error Digital output Ideal A/D conversion characteristic 101 100 (4) Nonlinearity error 011 (3) Quantization error 010 001 000 0 10221023 FS 1024 1024 Analog input voltage 1 2 1024 1024 Actual A/D convertion characteristic (1) Offset error FS: Full-scale voltage Figure 21.6 Definitions of A/D Conversion Accuracy Rev. 4.00 Sep.
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Section 21 A/D Converter 21.6 Usage Notes When using the A/D converter, note the following points. 21.6.1 Setting Analog Input Voltage Permanent damage to the LSI may result if the following voltage ranges are exceeded. 1. Analog input range: During A/D conversion, voltages on the analog input pins ANn should not go beyond the following range: AVss ≤ ANn ≤ AVcc (n = 0 to 7). 2. AVcc and AVss input voltages: Input voltages AVcc and AVss should be VccQ − 0.2 V ≤ AVcc ≤ VccQ and AVss = Vss.
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Section 21 A/D Converter 21.6.4 Influences on Absolute Precision Adding capacitance results in coupling with GND, and therefore noise in GND may adversely affect absolute precision. Be sure to make the connection to an electrically stable GND such as AVss. Care is also required to insure that filter circuits do not communicate with digital signals on the mounting board (i.e., acting as antennas). 21.6.
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Section 21 A/D Converter AVCC 100 Ω *2 Rin *1 AN0 to AN7 This LSI 0.1 µF AVSS Note: Value are referene value. 1. 10 µF 0.01 µF 2. Rin : input impedance Figure 21.7 Example of Analog Input Protection Circuit 3 kΩ to A/D converter AN0 to AN7 20 pF Note: Value are referene value. Figure 21.8 Analog Input Pin Equivalent Circuit This LSI Sensor output impeddance Up to 3 kΩ A/D converter equivalent circuit 3 kΩ Sensor input Low-pass filter Cin = 15pF 20pF C to 0.
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Section 21 A/D Converter Rev. 4.00 Sep.
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Section 22 Pin Function Controller (PFC) Section 22 Pin Function Controller (PFC) The pin function controller (PFC) is composed of registers for selecting the function of multiplexed pins and the input/output direction. The pin function and input/output direction can be selected for each pin individually without regard to the operating mode of the chip. Table 22.1 lists the multiplexed pins. Table 22.
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Section 22 Pin Function Controller (PFC) Port Port Function (Related Module) Other Function (Related Module) C PTC15 input/output (port) STATUS1 output (CPG) PTC14 input/output (port) STATUS0 output (CPG) PTC13 input/output (port) ASEBRKAK output (CPU) PTC12 input/output (port) DACK1 output (DMAC) PTC11 input/output (port) DACK0 output (DMAC) PTC10 input/output (port) DREQ1 input (DMAC) PTC9 input/output (port) DREQ0 input (DMAC) PTC8 input/output (port) TEND output (DMAC) PTC7 input/ou
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Section 22 Pin Function Controller (PFC) Port Port Function (Related Module) Other Function (Related Module) E PTE15 input/output (port) TIOC0A input/output (MTU) PTE14 input/output (port) TIOC0B input/output (MTU) PTE13 input/output (port) TIOC0C input/output (MTU) PTE12 input/output (port) TIOC0D input/output (MTU) PTE11 input/output (port) TIOC1A input/output (MTU) PTE10 input/output (port) TIOC1B input/output (MTU) PTE9 input/output (port) TIOC2A input/output (MTU) PTE8 input/output (
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Section 22 Pin Function Controller (PFC) Port Port Function (Related Module) Other Function (Related Module) G PTG13 input/output (port)  PTG12 input/output (port)  PTG11 input/output (port)  PTG10 input/output (port) SDA input/output (IIC2) PTG9 input/output (port) SDL input/output (IIC2) PTG8 input/output (port)  PTG7 input (port) AN7 input (ADC) PTG6 input (port) AN6 input (ADC) PTG5 input (port) AN5 input (ADC) PTG4 input (port) AN4 input (ADC) PTG3 input (port) AN3 input (
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Section 22 Pin Function Controller (PFC) Port Port Function (Related Module) Other Function (Related Module) J PTJ12 input/output (port) AUDSYNC output (AUD) PTJ11 input/output (port) AUDATA3 output (AUD) PTJ10 input/output (port) AUDATA2 output (AUD) PTJ9 input/output (port) AUDATA1 output (AUD) PTJ8 input/output (port) AUDATA0 output (AUD) PTJ7 input/output (port) IRQ7 input (INTC) PTJ6 input/output (port) IRQ6 input (INTC) PTJ5 input/output (port) IRQ5 input (INTC) PTJ4 input/output
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Section 22 Pin Function Controller (PFC) 22.1.1 Port A Control Register (PACR) PACR is a 32-bit readable/writable register that selects the pin functions. PACR is initialized to H'00000000 by a power-on reset, and it is not initialized by a manual reset, in standby mode, or in sleep mode. Bit Bit Name Initial Value R/W Description 31, 30  All 0 R Reserved These bits are always read as 0. The write value should always be 0.
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Section 22 Pin Function Controller (PFC) Bit Bit Name Initial Value R/W Description 7 PA3MD2 0 R/W PAn Mode 2 and 1 6 PA3MD1 0 R/W 5 PA2MD2 0 R/W 4 PA2MD1 0 R/W 3 PA1MD2 0 R/W 2 PA1MD1 0 R/W 1 PA0MD2 0 R/W The combination of bits PAnMD2 and PAnMD1 (n = 0 to 14) controls the pin functions. 00: Port input 01: Port output 10: Reserved (When set, correct operation cannot be guaranteed.) 11: Other functions (see table 22.1.
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Section 22 Pin Function Controller (PFC) 22.1.2 Port B Control Register (PBCR) PBCR is a 32-bit readable/writable register that selects the pin functions. PBCR is initialized to H'00000000 by a power-on reset, and it is not initialized by a manual reset, in standby mode, or in sleep mode. Bit Bit Name Initial Value R/W Description 31 to 18  All 0 R Reserved These bits are always read as 0. The write value should always be 0.
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Section 22 Pin Function Controller (PFC) 22.1.3 Port C Control Register (PCCR) PCCR is a 32-bit readable/writable register that selects the pin functions. PCCR is initialized to H'0C000000 by a power-on reset, and it is not initialized by a manual reset, in standby mode, or in sleep mode. Bit Bit Name Initial Value R/W Description 31 PC15MD2 0 R/W PCn Mode 2 and 1 30 PC15MD1 0 R/W 29 PC14MD2 0 R/W The combination of bits PCnMD2 and PCnMD1 (n = 0 to 15) controls the pin functions.
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Section 22 Pin Function Controller (PFC) Bit Bit Name Initial Value R/W Description 7 PC3MD2 0 R/W PCn Mode 2 and 1 6 PC3MD1 0 R/W 5 PC2MD2 0 R/W The combination of bits PCnMD2 and PCnMD1 (n = 0 to 15) controls the pin functions. 4 PC2MD1 0 R/W 00: Port input 3 PC1MD2 0 R/W 2 PC1MD1 0 R/W 1 PC0MD2 0 R/W 0 PC0MD1 0 R/W 22.1.4 01: Port output 10: Reserved (When set, correct operation cannot be guaranteed.) 11: Other functions (see table22.1.
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Section 22 Pin Function Controller (PFC) Bit Bit Name Initial Value R/W Description 17 PD8MD2 0/1 R/W PDn Mode 2 and 1 16 PD8MD1 0/1 R/W 15 PD7MD2 0/1 R/W 14 PD7MD1 0/1 R/W 13 PD6MD2 0/1 R/W 12 PD6MD1 0/1 R/W 11 PD5MD2 0/1 R/W The combination of bits PDnMD2 and PDnMD1 (n = 0 to 15) controls the pin functions. 00: Port input 01: Port output 10: Reserved (When set, correct operation cannot be guaranteed.) 11: Other functions (see table22.1.
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Section 22 Pin Function Controller (PFC) 22.1.5 Port E Control Register (PECR) PECR is a 32-bit readable/writable register that selects the pin functions. PECR is initialized to H'00000000 by a power-on reset, and it is not initialized by a manual reset, in standby mode, or in sleep mode.
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Section 22 Pin Function Controller (PFC) Bit Bit Name Initial Value R/W Description 7 PE3MD2 0 R/W PEn Mode 2 and 1 6 PE3MD1 0 R/W 5 PE2MD2 0 R/W 4 PE2MD1 0 R/W 3 PE1MD2 0 R/W 2 PE1MD1 0 R/W 1 PE0MD2 0 R/W 0 PE0MD1 0 R/W The combination of bits PEnMD2 and PEnMD1 (n = 0 to 15) controls the pin functions. 00: Port input 01: Port output 10: Reserved (When set, correct operation cannot be guaranteed.) 11: Other functions (see table 22.1.
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Section 22 Pin Function Controller (PFC) 22.1.6 Port E I/O Register (PEIOR) PEIOR is a 16-bit readable/writable register that selects the input/output direction of the port E pins. The PE15IOR to PE0IOR bits correspond to the PE15/TIOC0A to PE0/TIOC4D pins. PEIOR is valid only when the port E pins function as the TIOC pins of the MTU (other functions). Otherwise, PEIOR is invalid.
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Section 22 Pin Function Controller (PFC) 22.1.7 Port E MTU R/W Enable Register (PEMTURWER) PEMTURWER is a 16-bit readable/writable register that allows access of the MTU registers. PEMTURWER is initialized to H'0001 by a power-on reset, and it is not initialized by a manual reset, in standby mode, or in sleep mode. Bit Bit Name Initial Value R/W Description 15 to 1  All 0 R Reserved These bits are always read as 0. The write value should always be 0.
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Section 22 Pin Function Controller (PFC) 22.1.8 Port F Control Register (PFCR) PFCR is a 32-bit readable/writable register that selects the pin functions. PFCR is initialized to H'00000000 by a power-on reset, and it is not initialized by a manual reset, in standby mode, or in sleep mode.
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Section 22 Pin Function Controller (PFC) Bit Bit Name Initial Value R/W Description 15 PF7MD2 0 R/W PFn Mode 2,1 14 PF7MD2 0 R/W 13 PF6MD2 0 R/W 12 PF6MD2 0 R/W 11 PF5MD2 0 R/W 10 PF5MD2 0 R/W The combination of bits PFnMD2 and PFnMD1 controls the pin functions. (n = 0 to 7) 00: Port input 01: Port output 10, 11: Reserved (When set, correct operation cannot be guaranteed.
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Section 22 Pin Function Controller (PFC) 22.1.9 Port G Control Register (PGCR) PGCR is a 32-bit readable/writable register that selects the pin functions. PGCR is initialized to H'00000000 by a power-on reset, and it is not initialized by a manual reset, in the standby mode, or in the sleep mode. Bit Bit Name Initial Value R/W Description 31 to 28  All 0 R Reserved These bits are always read as 0. The write value should always be 0.
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Section 22 Pin Function Controller (PFC) Bit Bit Name Initial Value R/W Description 15 PG7MD2 0 R/W PGn Mode 2 and 1 14 PG7MD2 0 R/W 13 PG6MD2 0 R/W The combination of bits PGnMD2 and PGnMD1 controls the pin functions.
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Section 22 Pin Function Controller (PFC) 22.1.10 Port H Control Register (PHCR) PHCR is a 32-bit readable/writable register that selects the pin functions. PHCR is initialized to H'00000000 by a power-on reset, and it is not initialized by a manual reset, in standby mode, or in sleep mode. Bit Bit Name Initial Value R/W Description 31, 30  All 0 R Reserved These bits are always read as 0. The write value should always be 0.
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Section 22 Pin Function Controller (PFC) Bit Bit Name Initial Value R/W Description 7 PH3MD2 0 R/W PHn Mode 2 and 1 6 PH3MD2 0 5 PH2MD2 0 R/W The combination of bits PHnMD2 and PHnMD1controls the pin functions. (n = 0 to 14) 4 PH2MD2 0 3 PH1MD2 0 2 PH1MD2 0 1 PH0MD2 0 0 PH0MD2 0 00: Port input R/W 01: Port output 10: Reserved (When set, correct operation cannot be guaranteed.) R/W 11: Other functions (see table22.1.) 22.1.
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Section 22 Pin Function Controller (PFC) Bit Bit Name Initial Value R/W Description 13 PJ6MD2 0 R/W PJn Mode 2 and 1 12 PJ6MD2 0 11 PJ5MD2 0 10 PJ5MD2 0 9 PJ4MD2 0 8 PJ4MD2 0 7 PJ3MD2 0 6 PJ3MD2 0 5 PJ2MD2 0 4 PJ2MD2 0 3 PJ1MD2 0 2 PJ1MD2 0 1 PJ0MD2 0 0 PJ0MD2 0 R/W R/W R/W R/W R/W R/W Rev. 4.00 Sep. 14, 2005 Page 840 of 982 REJ09B0023-0400 The combination of bits PJnMD2 and PJnMD1controls the pin functions.
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Section 22 Pin Function Controller (PFC) 22.2 I/O Buffer Internal Block Diagram 22.2.1 I/O Buffer with Weak Keeper All the I/O buffers except PTG10, PTG9, and PTG 7 to PTG 0 (IIC2 and analog pins) listed in table 22.1 have weak keepers that consist of two inverters to keep the status of the pin. Figure 22.1 shows the internal block diagram of the I/O buffer. I/O buffer Output enalbe Output data Input data Weak keeper Figure 22.1 Internal Block Diagram of I/O Buffer with Weak Keeper 22.2.
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Section 22 Pin Function Controller (PFC) SDA input data SCL input data SDA output data SCL output data PTG[10] output enable PTG[9] output enable PTG[10] /SDA PTG[9] /SCL PTG[10] output data PTG[9] output data PTG[10] input data PTG[9] input data Figure 22.2 Internal Block Diagram of I/O Buffer with Open Drain 22.3 Notes on Usage • Pins function as outputs when other function is selected by the port control register When the pin function (shown in table 22.
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Section 23 I/O Ports Section 23 I/O Ports This LSI has nine 16-bit ports (ports A to J). All port pins are multiplexed with other pin functions (the pin function controller (PFC) handles the selection of pin functions). Each port has a data register which stores data for the pins. 23.1 Port A Port A is a 15-bit input/output port with the pin configuration shown in figure 23.1. Each pin is controlled by the port A control register (PACR) in the PFC.
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Section 23 I/O Ports 23.1.2 Port A Data Register (PADR) PADR is a 15-bit readable/writable register with one reserved bit that stores data for pins PTA14 to PTA0. PADR is initialized to H'0000 by a power-on reset, but it retains its previous value by a manual reset, in standby mode or in sleep mode. Bit Bit Name Initial Value R/W Description 15  0 R Reserved This bit is always read as 0. The write value should always be 0.
PAGE 895
Section 23 I/O Ports Table 23.1 Port A Data Register (PADR) Read/Write Operations PAnMD2 PAnMD1 Pin Function Read Write 0 1 0 Input Pin state Data is written to PADR, but does not affect pin state. 1 Output PADR value Data is written to PADR and the value is output from the pin. 0 Reserved   1 Other functions Pin state Data is written to PADR, but does not affect pin state. (n = 0 to 14) 23.2 Port B Port B is a 9-bit input/output port with the pin configuration shown in figure 23.
PAGE 896
Section 23 I/O Ports 23.2.2 Port B Data Register (PBDR) PBDR is a 9-bit readable/writable register with seven reserved bits that stores data for pins PTB8 to PTB0. PBDR is initialized to H'0000 by a power-on reset, but it retains its previous value by a manual reset, in standby mode, or in sleep mode. Bit Bit Name Initial Value R/W Description 15 to 9  All 0 R Reserved These bits are always read as 0. The write value should always be 0.
PAGE 897
Section 23 I/O Ports 23.3 Port C Port C is a 16-bit input/output port with the pin configuration shown in figure 23.3. Each pin is controlled by the port C control register (PCCR) in the PFC.
PAGE 898
Section 23 I/O Ports 23.3.2 Port C Data Register (PCDR) PCDR is a 16-bit readable/writable register that stores data for pins PTC15 to PTC0. PCDR is initialized to H'0000 by a power-on reset, but it retains its previous value by a manual reset, in standby mode, or in sleep mode. Bit Bit Name Initial Value R/W Description 15 PC15DT 0 R/W 14 PC14DT 0 R/W 13 PC13DT 0 R/W 12 PC12DT 0 R/W 11 PC11DT 0 R/W Bits PC15DT to PC0DT correspond to pins PTC15 to PTC0.
PAGE 899
Section 23 I/O Ports Table 23.3 Port C Data Register (PCDR) Read/Write Operations PCnMD2 PCnMD1 Pin State Read Write 0 1 0 Input Pin state Data is written to PCDR, but does not affect pin state. 1 Output PCDR value Data is written to PCDR and the value is output from the pin. 0 Reserved   1 Other functions Pin state Data is written to PCDR, but does not affect pin state. (n = 0 to 15) 23.
PAGE 900
Section 23 I/O Ports 23.4.1 Register Description Port D has the following register. • Port D data register (PDDR) 23.4.2 Port D Data Register (PDDR) PDDR is a 16-bit readable/writable register that stores data for pins PTD15 to PTD0. PDDR is initialized to H'0000 by a power-on reset, after which the general input port function is set as the initial pin function, and the corresponding pin levels are read when MD3 = 0 (16-bit bus width in CS0 space) is set.
PAGE 901
Section 23 I/O Ports Table 23.4 Port D Data Register (PDDR) Read/Write Operations PDnMD2 PDnMD1 Pin State Read Write 0 1 0 Input Pin state Data is written to PDDR, but does not affect pin state. 1 Output PDDR value Data is written to PDDR and the value is output from the pin. 0 Reserved   1 Other function Pin state Data is written to PDDR, but does not affect pin state. (n = 0 to 15) 23.5 Port E Port E is a 16-bit input/output port with the pin configuration shown in figure 23.5.
PAGE 902
Section 23 I/O Ports 23.5.1 Register Description Port E has the following register. • Port E data register (PEDR) 23.5.2 Port E Data Register (PEDR) PEDR is a 16-bit readable/writable register that stores data for pins PTE15 to PTE0. The PEDR is initialized to H'0000 by a power-on reset, but it retains its previous value by a manual reset, in standby mode, or in sleep mode.
PAGE 903
Section 23 I/O Ports Table 23.5 Port E Data Register (PEDR) Read/Write Operations PEnMD2 PEnMD1 Pin State Read Write 0 1 0 Input Pin state Data is written to PEDR, but does not affect pin state. 1 Output PEDR value Data is written to PEDR and the value is output from the pin. 0 Reserved   1 Other function Pin state Data is written to PEDR, but does not affect pin state. (n = 0 to 15) 23.6 Port F Port F is a 16-bit input port with the pin configuration shown in figure 23.6.
PAGE 904
Section 23 I/O Ports 23.6.1 Register Description Port F has the following register. • Port F data register (PFDR) 23.6.2 Port F Data Register (PFDR) PFDR is a 16-bit readable/writable register that stores data for pins PTF15 to PTF0. PFDR is initialized to H'0000 by a power-on reset, but it retains its previous value by a manual reset, in standby mode, or in sleep mode.
PAGE 905
Section 23 I/O Ports Table 23.6 Port F Data Register (PFDR) Read/Write Operations (PF15DT to PF8DT) PFnMD2 PFnMD1 Pin State Read Write 0 1 0 Input Pin state Data is written to PFDR, but does not affect pin state. 1 Output PFDR value Data is written to PFDR and the value is output from the pin. 0 Reserved   1 Other function Pin state Data is written to PFDR, but does not affect pin state. (n = 8 to 15) Table 23.
PAGE 906
Section 23 I/O Ports 23.7 Port G Port G comprises a 6-bit input/output port and an 8-bit input port with the pin configuration shown in figure 23.7. Each pin is controlled by the port G control register (PGCR) in the PFC.
PAGE 907
Section 23 I/O Ports 23.7.2 Port G Data Register (PGDR) PGDR a register that includes six readable/writable and eight readable bits with two reserved bits that store data for pins PTG13 to PTG0. PGDR13 to PGDR8 are initialized to H'00 by a power-on reset, but they retain their previous values by a manual reset, in standby mode, or in sleep mode. PGDR7 to PGDR0 are not initialized by a power-on or manual reset, in standby mode, or in sleep mode. (The bit always indicates the status of the pin.
PAGE 908
Section 23 I/O Ports Table 23.8 Port G Data Register (PGDR) Read/Write Operations (PG13DT to PG11DT, PG8DT) PGnMD2 PGnMD1 Pin State Read Write 0 0 Input Pin state Data is written to PGDR, but does not affect pin state. 1 Output PGDR value Data is written to PGDR and the value is output from the pin. Reserved   Other than above (n = 8, 11 to 13) Table 23.
PAGE 909
Section 23 I/O Ports 23.7.3 Port G Internal Block Diagram Pins PTG7 to PTG0 are multiplexed with the A/D converter. (See section 22, Pin Function Controller (PFC).) The statuses of these pins are read only when the PGDR is read, but are always input to the A/D converter. Figure 23.8 shows the internal block diagram of PG7DT to PG0DT. Enabled only when the port is read. Port Port data register A/D Figure 23.8 Internal Block Diagram of PG7DT to PG0DT Rev. 4.00 Sep.
PAGE 910
Section 23 I/O Ports 23.8 Port H Port H comprises a 15-bit input/output port with the pin configuration shown in figure 23.9. Each pin is controlled by the port H control register (PHCR) in the PFC.
PAGE 911
Section 23 I/O Ports 23.8.2 Port H Data Register (PHDR) PHDR is a 15-bit readable/writable register with one reserved bit that stores data for pins PTH14 to PTH0. PHDR is initialized to H'0000 by a power-on reset, but it retains its previous value by a manual reset, in standby mode, or in sleep mode. Bit Bit Name Initial Value R/W Description 15  0 R Reserved This bit is always read as 0. The write value should always be 0.
PAGE 912
Section 23 I/O Ports Table 23.11 Port H Data Register (PHDR) Read/Write Operations PHnMD2 PHnMD1 Pin State Read Write 0 Data is written to PHDR, but does not affect pin state. 1 0 Input Pin state 1 Output PHDR value Data is written to PHDR and the value is output from the pin. 0 Reserved  1 Other functions Pin state  Data is written to PHDR, but does not affect pin state. (n = 0 to 14) 23.9 Port J Port J is a 13-bit input/output port with the pin configuration shown in figure 23.10.
PAGE 913
Section 23 I/O Ports 23.9.2 Port J Data Register (PJDR) PJDR is a 13-bit readable/writable register with three reserved bits that stores data for pins PTJ12 to PTJ0. The PJDR is initialized to H'0000 by a power-on reset, but it retains its previous value by a manual reset, in standby mode, or in sleep mode. Bit Bit Name Initial Value R/W Description 15 to 13  All 0 R Reserved These bits are always read as 0. The write value should always be 0.
PAGE 914
Section 23 I/O Ports Rev. 4.00 Sep.
PAGE 915
Section 24 List of Registers Section 24 List of Registers This section gives information on the on-chip I/O registers and is configured as described below. 1. Register Addresses (by functional module, in order of the corresponding section numbers) • Descriptions by functional module, in order of the corresponding section numbers Entries that consist of - lines are for separation of the functional modules. • Access to reserved addresses which are not described in this list is prohibited.
PAGE 916
Section 24 List of Registers 24.1 Register Addresses (by functional module, in order of the corresponding section numbers) Entries under Access size indicates numbers of bits. Note: Access to undefined or reserved addresses is prohibited. Since operation or continued operation is not guaranteed when these registers are accessed, do not attempt such access. Register Name Abbreviation Bit No.
PAGE 917
Section 24 List of Registers Register Name Abbreviation Bit No.
PAGE 918
Section 24 List of Registers Register Name Abbreviation Bit No.
PAGE 919
Section 24 List of Registers Register Name Abbreviation Bit No.
PAGE 920
Section 24 List of Registers Register Name Abbreviation Bit No.
PAGE 921
Section 24 List of Registers Register Name Abbreviation Bit No.
PAGE 922
Section 24 List of Registers Register Name Abbreviation Bit No.
PAGE 923
Section 24 List of Registers Register Name Abbreviation Bit No.
PAGE 924
Section 24 List of Registers Register Name Abbreviation Bit No.
PAGE 925
Section 24 List of Registers Register Name Abbreviation Bit No.
PAGE 926
Section 24 List of Registers 24.2 Register Bits Register addresses and bit names of the on-chip peripheral modules are described below. Each line covers eight bits, and 16-bit and 32-bit registers are shown as 2 or 4 lines, respectively.
PAGE 927
Section 24 List of Registers Register Bit Bit Bit Bit Bit Bit Bit Bit Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 Module EXPEVT IPRF — — — — — — — — Exception — — — — — — — — handling — — — — INTC IPR15 IPR14 IPR13 IPR12 IPR11 IPR10 IPR9 IPR8 IPR7 IPR6 IPR5 IPR4 IPR3 IPR2 IPR1 IPR0 IPR15 IPR14 IPR13 IPR12 IPR11 IPR10 IPR9 IPR8 IPR7 IPR6 IPR5 IPR4 IPR3 IPR2 IPR1 IPR0 IPR15 IPR14 IPR1
PAGE 928
Section 24 List of Registers Register Bit Bit Bit Bit Bit Bit Bit Bit Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 Module IMCR9 IMC7 IMC6 IMC5 IMC4 IMC3 IMC2 IMC1 IMC0 INTC IMCR10 IMC7 IMC6 IMC5 IMC4 IMC3 IMC2 IMC1 IMC0 IRR0 IRQ7R IRQ6R IRQ5R IRQ4R IRQ3R IRQ2R IRQ1R IRQ0R ICR1 — IRQE — — IRQ51S IRQ50S IRQ41S IRQ40S IRQ31S IRQ30S IRQ21S IRQ20S IRQ11S IRQ10S IRQ01S IRQ00S — — — — — — — — —
PAGE 929
Section 24 List of Registers Register Bit Bit Bit Bit Bit Bit Bit Bit Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 Module BETR UBC BARB BAMRB BBRB BRSR BARA BAMRA BBRA BRDR — — — — BET11 BET10 BET9 BET8 BET7 BET6 BET5 BET4 BET3 BET2 BET1 BET0 BAB31 BAB30 BAB29 BAB28 BAB27 BAB26 BAB25 BAB24 BAB23 BAB22 BAB21 BAB20 BAB19 BAB18 BAB17 BAB16 BAB15 BAB14 BAB13 BAB12 BAB11 BAB10 BAB9 BAB8 BAB7 BAB6
PAGE 930
Section 24 List of Registers Register Bit Bit Bit Bit Bit Bit Bit Bit Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 Module CMNCR BSC CS0BCR CS2BCR CS3BCR CS4BCR CS5ABCR CS5BBCR — — — — — — — — — — — — — — — — WAITSEL — — MAP BLOCK DPRTY1 DPRTY0 DMAIW2 DMAIW1 DMAIW0 DMAIWA — — CK2DRV HIZMEM HIZCNT — IWW2 IWW1 IWW0 IWRWD2 IWRWD1 IWRWD0 IWRWS2 IWRWS1 IWRWS0 IWRRD2 IWRRD1 IWRRD0 IWRRS2 IWRRS1
PAGE 931
Section 24 List of Registers Register Bit Bit Bit Bit Bit Bit Bit Bit Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 Module CS6ABCR BSC CS6BBCR 1 CS0WCR* 2 CS0WCR* 3 CS0WCR* 1 CS2WCR* 4 CS2WCR* — IWW2 IWW1 IWW0 IWRWD2 IWRWD1 IWRWD0 IWRWS2 IWRWS1 IWRWS0 IWRRD2 IWRRD1 IWRRD0 IWRRS2 IWRRS1 IWRRS0 — TYPE2 TYPE1 TYPE0 — BSZ1 BSZ0 — — — — — — — — — — IWW2 IWW1 IWW0 IWRWD2 IWRWD1 IWRWD0 IWRWS2 IWRW
PAGE 932
Section 24 List of Registers Register Bit Bit Bit Bit Bit Bit Bit Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 1 CS3WCR* 4 CS3WCR* 1 CS4WCR* 2 CS4WCR* 1 CS5AWCR* 1 CS5BWCR* 1 CS6AWCR* Bit 24/16/8/0 Module BSC — — — — — — — — — — — BAS — — — — — — — — — WR3 WR2 WR1 WR0 WM — — — — — — — — — — — — — — — — — — — — — — — WTRP1 WTRP0 — WTRCD1 WTRCD0 — A3CL1 A3CL0 — — TRWL1 TRWL0 — WTR
PAGE 933
Section 24 List of Registers Register Bit Bit Bit Bit Bit Bit Bit Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 1 CS6BWCR* 5 CS6BWCR* SDCR RTCSR Bit 24/16/8/0 Module BSC — — — — — — — — — — — BAS — — — — — — — SW1 SW0 WR3 WR2 WR1 WR0 WM — — — — HW1 HW0 — — — — — — — — — — MPXAW1 MPXAW0 MPXMD — BW1 BW0 — — — — — W3 W2 W1 W0 WM — — — — — — — — — — — — — — — — — A2ROW1 A2ROW0
PAGE 934
Section 24 List of Registers Register Bit Bit Bit Bit Bit Bit Bit Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 Bit 24/16/8/0 DMATCR_0 CHCR_0 DMAC TC — — — — — — — DO TL — — — — AM AL DM1 DM0 SM1 SM0 RS3 RS2 RS1 RS0 DL DS TB TS1 TS0 IE TE DE SAR_1 DAR_1 DMATCR_1 CHCR_1 Module TC — — — — — — — DO — — — — — AM AL DM1 DM0 SM1 SM0 RS3 RS2 RS1 RS0 DL DS TB TS1 TS0 IE TE DE SAR_2 Rev. 4.
PAGE 935
Section 24 List of Registers Register Bit Bit Bit Bit Bit Bit Bit Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 Bit 24/16/8/0 DAR_2 Module DMAC DMATCR_2 CHCR_2 TC — — — — — — — — — — — — — — — DM1 DM0 SM1 SM0 RS3 RS2 RS1 RS0 — — TB TS1 TS0 IE TE DE TC — — — — — — — — — — — — — — — DM1 DM0 SM1 SM0 RS3 RS2 RS1 RS0 — — TB TS1 TS0 IE TE DE SAR_3 DAR_3 DMATCR_3 CHCR_3 Rev. 4.00 Sep.
PAGE 936
Section 24 List of Registers Register Bit Bit Bit Bit Bit Bit Bit Bit Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 Module DMAOR DMAC — — CMS1 CMS0 — — PR1 PR0 — — — — — AE NMIF DME — — — — — — — — — — RC0 RC1 RC2 RC3 — — C1MID5 C1MID4 C1MID3 C1MID2 C1MID1 C1MID0 C1RID1 C1RID0 C0MID5 C0MID4 C0MID3 C0MID2 C0MID1 C0MID0 C0RID1 C0RID0 C3MID5 C3MID4 C3MID3 C3MID2 C3MID1 C3MID0 C3RID1 C3RID0
PAGE 937
Section 24 List of Registers Register Bit Bit Bit Bit Bit Bit Bit Bit Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 Module CMSTR_1 CMT — — — — — — — — — — — — — — — STR — — — — — — — — CMF — CMR1 CMR0 — — CKS1 CKS0 TCR_3 CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TCR_4 CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TMDR_3 — — BFB BFA MD3 MD2 MD1 MD0 TMDR_4 — — BFB BFA MD3
PAGE 938
Section 24 List of Registers Register Bit Bit Bit Bit Bit Bit Bit Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 Bit 24/16/8/0 TGRB_3 Module MTU TGRA_4 TGRB_4 TCNTS TCBR TGRC_3 TGRD_3 TGRC_4 TGRD_4 TSR_3 TCFD — — TCFV TGFD TGFC TGFB TGFA TSR_4 TCFD — — TCFV TGFD TGFC TGFB TGFA TSTR CST4 CST3 — — — CST2 CST1 CST0 TSYR SYNC4 SYNC3 — — — SYNC2 SYNC1 SYNC0 TCR_0 CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TP
PAGE 939
Section 24 List of Registers Register Bit Bit Bit Bit Bit Bit Bit Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 Bit 24/16/8/0 TGRA_0 Module MTU TGRB_0 TGRC_0 TGRD_0 TCR_1 CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TMDR_1 — — — — MD3 MD2 MD1 MD0 TIOR_1 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 TIER_1 TTGE TGFASEL TCIEU TCIEV — — TGIEB TGIEA TSR_1 TCFD — TCFU TCFV — — TGFB TGFA TCR_2 CCLR2 CCLR1 CCLR0
PAGE 940
Section 24 List of Registers Register Bit Bit Bit Bit Bit Bit Bit Bit Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 Module ICSR1 MTU OCSR SCSMR_0 POE3F POE2F POE1F POE0F — — — PIE POE3M1 POE3M0 POE2M1 POE2M0 POE1M1 POE1M0 POE0M1 POE0M0 OSF — — — — — OCE OIE — — — — — — — — — — — — — — — — C/A CHR PE O/E STOP — CKS1 CKS0 — — — — — — — — TIE RIE TE RE REIE — CKE1 CKE0 PER3 PER
PAGE 941
Section 24 List of Registers Register Bit Bit Bit Bit Bit Bit Bit Bit Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 Module SCFCR_1 SCIF SCFDR_1 SCSPTR_1 — — — — — RSTRG2 RSTRG1 RSTRG0 RTRG1 RTRG0 TTRG1 TTRG0 MCE TFRST RFRST LOOP — — — T4 T3 T2 T1 T0 — — — R4 R3 R2 R1 R0 — — — — — — — — RTSIO RTSDT CTSIO CTSDT SCKIO SCKDT SPB2IO SPB2DT — — — — — — — — — — — — — — — ORER — —
PAGE 942
Section 24 List of Registers Register Bit Bit Bit Bit Bit Bit Bit Bit Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 Module USBEPSZ0o USB — — — — — — — — USBEPDR0s D7 D6 D5 D4 D3 D2 D1 D0 USBDASTS — — EP3DE EP2DE — — — EP0iDE USBISR0 BRST EP1FULL EP2TR EP2EMPTY SETUPTS EP0oTS EP0iTR EP0iTS USBEPSTL — — — ASCE EP2STL EP1STL EP0STL USBIER0 BRST EP1FULL EP2TR EP2EMPTY SETUPTS EP0oTS EP3STL EP0iTR E
PAGE 943
Section 24 List of Registers Register Bit Bit Bit Bit Bit Bit Bit Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 Bit 24/16/8/0 ADDRD1 ADCSR0 ADCSR1 ADCR PACR PBCR PCCR PDCR PECR Module ADC — — — — — — ADF ADIE ADST DMASL TRGE — — — CKS1 CKS0 MULTI1 MULTI0 — — CH1 CH0 ADF ADIE ADST DMASL TRGE — — — CKS1 CKS0 MULTI1 MULTI0 — — CH1 CH0 DSMP — — — — — — — — — — — — — — — — — PA14MD2 PA14MD1 PA
PAGE 944
Section 24 List of Registers Register Bit Bit Bit Bit Bit Bit Bit Bit Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 Module PFCR PFC PGCR PHCR PJCR PEIOR PEMTURWER PADR PBDR PCDR PDDR PEDR PF15MD2 PF15MD1 PF14MD2 PF14MD1 PF13MD2 PF13MD1 PF12MD2 PF12MD1 PF11MD2 PF11MD1 PF10MD2 PF10MD1 PF9MD2 PF9MD1 PF8MD2 PF8MD1 PF7MD2 PF7MD1 PF6MD2 PF6MD1 PF5MD2 PF5MD1 PF4MD2 PF4MD1 PF3MD2 PF3MD1 PF2MD2 PF2MD1 PF1MD2 PF
PAGE 945
Section 24 List of Registers Register Bit Bit Bit Bit Bit Bit Bit Bit Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 Module PFDR PORT PGDR PHDR PJDR Notes: 1. 2. 3. 4. 5.
PAGE 946
Section 24 List of Registers 24.
PAGE 947
Section 24 List of Registers Register Software Abbreviation Power-On Reset Manual Reset Standby Module Standby Sleep Module IMCR0 Initialized Initialized Retained  Retained INTC IMCR1 Initialized Initialized Retained  Retained IMCR2 Initialized Initialized Retained  Retained IMCR4 Initialized Initialized Retained  Retained IMCR5 Initialized Initialized Retained  Retained IMCR6 Initialized Initialized Retained  Retained IMCR7 Initialized Initialized Retain
PAGE 948
Section 24 List of Registers Register Software Abbreviation Power-On Reset Manual Reset Standby Module Standby Sleep Module BBRA Initialized Retained Retained Retained Retained UBC BRDR Undefined*2 Retained Retained Retained Retained CMNCR Initialized Retained Retained  Retained CS0BCR Initialized Retained Retained  Retained CS2BCR Initialized Retained Retained  Retained CS3BCR Initialized Retained Retained  Retained CS4BCR Initialized Retained Retained 
PAGE 949
Section 24 List of Registers Register Software Abbreviation Power-On Reset Manual Reset Standby Module Standby Sleep Module DAR_1 Undefined Undefined Retained Retained Retained DMAC DMATCR_1 Undefined Undefined Retained Retained Retained CHCR_1 Initialized Initialized Retained Retained Retained SAR_2 Undefined Undefined Retained Retained Retained DAR_2 Undefined Undefined Retained Retained Retained DMATCR_2 Undefined Undefined Retained Retained Retained CHCR_2 In
PAGE 950
Section 24 List of Registers Register Software Abbreviation Power-On Reset Manual Reset Standby Module Standby Sleep Module CMCOR_0 Initialized Retained Retained Retained Retained CMT CMSTR_1 Initialized Retained Retained Retained Retained CMCSR_1 Initialized Retained Retained Retained Retained CMCNT_1 Initialized Retained Retained Retained Retained CMCOR_1 Initialized Retained Retained Retained Retained TCR_3 Initialized Retained Initialized Initialized Retained
PAGE 951
Section 24 List of Registers Register Software Abbreviation Power-On Reset Manual Reset Standby Module Standby Sleep Module TGRD_3 Initialized Retained Initialized Initialized Retained MTU TGRC_4 Initialized Retained Initialized Initialized Retained TGRD_4 Initialized Retained Initialized Initialized Retained TSR_3 Initialized Retained Initialized Initialized Retained TSR_4 Initialized Retained Initialized Initialized Retained TSTR Initialized Retained Initialized I
PAGE 952
Section 24 List of Registers Register Software Abbreviation Power-On Reset Manual Reset Standby Module Standby Sleep Module TIER_2 Initialized Retained Initialized Initialized Retained MTU TSR_2 Initialized Retained Initialized Initialized Retained TCNT_2 Initialized Retained Initialized Initialized Retained TGRA_2 Initialized Retained Initialized Initialized Retained TGRB_2 Initialized Retained Initialized Initialized Retained ICSR1 Initialized Retained Retained Re
PAGE 953
Section 24 List of Registers Register Software Abbreviation Power-On Reset Manual Reset Standby Module Standby Sleep Module SCSCR_2 Initialized Retained Retained Retained Retained SCIF SCFTDR_2 Undefined Retained Retained Retained Retained SCFSR_2 Initialized Retained Retained Retained Retained SCFRDR_2 Undefined Retained Retained Retained Retained SCFCR_2 Initialized Retained Retained Retained Retained SCFDR_2 Initialized Retained Retained Retained Retained SCSPT
PAGE 954
Section 24 List of Registers Register Software Abbreviation Power-On Reset Manual Reset Standby Module Standby Sleep Module USBIER2 Initialized Retained Retained Retained Retained USB USBCTRL Initialized Retained Retained Retained Retained ADDRA0 Initialized Retained Initialized Initialized Retained ADDRB0 Initialized Retained Initialized Initialized Retained ADDRC0 Initialized Retained Initialized Initialized Retained ADDRD0 Initialized Retained Initialized Initial
PAGE 955
Section 24 List of Registers Register Software Abbreviation Power-On Reset Manual Reset Standby Module Standby Sleep Module PFDR Initialized Retained Retained — Retained PORT PGDR Initialized*3 Retained Retained — Retained PHDR Initialized Retained Retained — Retained Initialized Retained Retained — Retained PJDR Notes: 1. 2. 3. 4. Not initialized by a power-on reset. Some bits are initialized. Some bits are not initialized.
PAGE 956
Section 24 List of Registers Rev. 4.00 Sep.
PAGE 957
Section 25 Electrical Characteristics Section 25 Electrical Characteristics The specifications shown in this section are preliminary. After the characteristics have been evaluated, the specifications may be changed without notice. 25.1 Absolute Maximum Ratings Table 25.1 lists the absolute maximum ratings. Table 25.1 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage (I/O) VCCQ −0.3 to 3.8 V Power supply voltage (Internal) VCC −0.3 to 2.
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Section 25 Electrical Characteristics 25.1.1 Power-On Sequence Supply the power so that VccQ (3.3-V system) and Vcc (1.8-V system) are supplied simultaneously or Vcc is supplied after VccQ is supplied. Recommended values for the power-on procedure are shown below. VCCQ: 3.3 V-system power supply VCCQ (min.) voltage VCC: 1.8 V-system power supply tpwu VCC (min.
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Section 25 Electrical Characteristics Table 25.2 Recommended Values for Power-On/Off Sequence Item Symbol Max. Permissible Value Unit Time lag between VccQ and Vcc when turning on tpwu 1 ms Time lag between VccQ and Vcc when turning off tpwd 1 ms Unsettling operation time 100 ms tunc Notes: 1. The figures shown above are recommended values, so they represent guidelines rather than strict requirements. 2.
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Section 25 Electrical Characteristics 25.2 DC Characteristics Tables 25.3 and 25.4 list DC characteristics. Table 25.3 DC Characteristics (1) [Common Items] Conditions: Ta = −40°C to +85°C Item Symbol Current Normal operation 1 consumption* 2 ICC* Min. Typ. Max. Unit Test Conditions — 300 400 mA VCC = 1.8 V Iφ = 100 MHz Pφ = 33 MHz 3 ICCQ* — 10 20 mA VCCQ = 3.
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Section 25 Electrical Characteristics Table 25.3 DC Characteristics (2) [Except for I2C- and USB-Related Pins] Conditions: VCC = VCC (PLL1, PLL2) = 1.8 V ±5%, VCCQ = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, VSS = VSS (PLL1, PLL2) = AVSS = 0 V, Ta = −40°C to +85°C Item Symbol Min. Typ. Max. Unit Power supply VCCQ 3.0 3.3 3.6 V VCC 1.71 1.8 1.89 Test Conditions VCC (PLL1) VCC (PLL2) Input high RESETP, RESETM, VIH voltage NMI, MD3, MD2 VCCQ × 0.9 — VCCQ + 0.3 V EXTAL, CKIO VCCQ − 0.
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Section 25 Electrical Characteristics Item Symbol Schmitt trigger TIOC0A to TIOC0D, VT + input − TIOC1A, TIOC1B, characteristics TIOC2A, TIOC2B, TIOC3A to TIOC3D, VT + VT − VT − Min. Typ. Max. Unit VCCQ × 0.9 — — V — — VCCQ × 0.2 V VCCQ × 0.05 — — V 2.4 — — V 2.0 — — — — 1.5 — — 0.4 1.
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Section 25 Electrical Characteristics Table 25.3 DC Characteristics (3) [I2C-Related Pins*] Conditions: VCCQ = 3.0 V to 3.6 V, VCC = 1.8 V ±5%, VSSQ = VSS = 0 V, Ta = −40°C to +85°C Item Symbol Min. Typ. Max. Unit Power supply VCCQ 3.0 3.3 3.6 V Input high voltage VIH VCCQ × 0.7 — VCCQ + 0.3 V Input low voltage VIL −0.3 — VCCQ × 0.3 V Schmitt trigger input characteristics VIH − VIL VCCQ × — — V — 0.4 V Test Conditions 0.05 Output low voltage Note: * VOL 0 IOL = 3.
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Section 25 Electrical Characteristics Table 25.3 DC Characteristics (5) [USB Transceiver-Related Pins*] Conditions: Ta = −40°C to +85°C Item Symbol Min. Typ. Max. Unit Test Conditions Differential input sensitivity VDI 0.2 — — V (DP) – (DM) Differential common mode range VCM 0.8 — 2.5 V Single ended receiver threshold voltage VSE 0.8 — 2.0 V Output high voltage VOH 2.8 — VCCQ V Output low voltage VOL — — 0.
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Section 25 Electrical Characteristics 25.3 AC Characteristics Signals input to this LSI are basically handled as signals in synchronization with a clock. The setup and hold times for input pins must be followed. Table 25.5 Maximum Operating Frequency Conditions: VCCQ = 3.0 V to 3.6 V, VCC = 1.8 V ± 5%, AVCC = 3.0 V to 3.6 V, Ta = −40°C to +85°C Item Operating frequency Symbol Min. Typ. Max.
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Section 25 Electrical Characteristics 25.3.1 Clock Timing Table 25.6 Clock Timing Conditions: VCCQ = 3.0 V to 3.6 V, VCC = 1.8 V ± 5%, AVCC = 3.0 V to 3.6 V, VSSQ = VSS = AVSS = 0 V, Ta = −40°C to +85°C Item Symbol Min. Max. Unit Figure(s) EXTAL clock input frequency fEX 10 25 MHz 25.
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Section 25 Electrical Characteristics tEXcyc tEXH EXTAL* (input) 1/2 VCC VIH tEXL VIH 1/2 VCC VIH VIL VIL tEXF tEXR Note: * When the clock is input on the EXTAL pin. Figure 25.2 EXTAL Clock Input Timing tCKIcyc tCKIH CKIO (input) 1/2 VCCQ tCKIL VIH VIH 1/2 VCCQ VIH VIL VIL tCKIF tCKIR Figure 25.3 CKIO Clock Input Timing tcyc tCKOH CKIO, CKIO2 (output) 1/2VCC VIH tCKOL VOH VOH VOL VOL tCKOF 1/2VCC tCKOR Figure 25.4 CKIO and CKIO2 Clock Input Timing Rev. 4.00 Sep.
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Section 25 Electrical Characteristics Oscillation settling time CKIO, Internal clock VCC VCC min tRESP/MW tOSC1 tRESP/MS RESETP RESETM Note: Oscillation settling time when the internal oscillator is used. Figure 25.5 Oscillation Settling Timing (Power-On) CKIO CKIO2 tphckio2 Figure 25.6 Phase Difference between CKIO and CKIO2 Oscillation settling time Standby period CKIO, Internal clock tOSC2 tRESP/MW RESETP RESETM Note: Oscillation settling time when the internal oscillator is used.
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Section 25 Electrical Characteristics Standby period Oscillation settling time CKIO, Internal clock tOSC3 NMI, IRQ Note: Oscillation settling time when the internal oscillator is used. Figure 25.8 Oscillation Settling Timing (Standby Mode Canceled by NMI or IRQ) Rev. 4.00 Sep.
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Section 25 Electrical Characteristics 25.3.2 Control Signal Timing Table 25.7 Control Signal Timing Conditions: VCCQ = 3.0 V to 3.6 V, VCC = 1.8 V ±5%, AVCC = 2.7 V to 3.6 V, VSSQ = VSS = AVSS = 0 V, Ta = −40°C to +85°C 2 Bφ = 50 MHz* Item Symbol RESETP pulse width Min. 2 Max.
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Section 25 Electrical Characteristics CKIO tRESPS/MS tRESPS/MS tRESPW/MW RESETP RESETM Figure 25.9 Reset Input Timing CKIO tRESPH/MH VIH RESETP RESETM VIL tNMIH tNMIS VIH NMI VIL tIRQH IRQ7 to IRQ0 tRESPS/MS tIRQS VIH VIL Figure 25.10 Interrupt Input Timing Rev. 4.00 Sep.
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Section 25 Electrical Characteristics tBOFF2 tBON2 CKIO (HIZCNT = 0) CKIO (HIZCNT = 1) tBREQH tBREQS tBREQH tBREQS BREQ tBACKD tBACKD BACK tBON1 tBOFF1 A25 to A0, D31 to D0 tBOFF2 tBON2 RD, RD/WR, RASU/L, CASU/L, CSn, WEn, BS, CKE When HZCNT = 1 When HZCNT = 0 Figure 25.11 Bus Release Timing Normal mode Standby mode Normal mode CKIO input tSTD tSTD tBOFF2 tBON2 tBOFF1 tBON1 STATUS 0 STATUS 1 RD, RD/WR, RASU/L, CASU/L, CSn, WEn, BS, CKE A25 to A0, D31 to D0 Figure 25.
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Section 25 Electrical Characteristics 25.3.3 AC Bus Timing Table 25.8 Bus Timing Conditions: Clock mode 2/6/7, VCCQ = 3.0 V to 3.6 V, VSSQ = 0 V, Ta = −40°C to +85°C Bφ = 50 MHz* Item Symbol Min. Max. Unit Figure(s) Address delay time 1 tAD1 1 12 ns 25.13 to 25.39 Address delay time 2 tAD2 1/2tcyc 1/2tcyc + 12 ns 25.22 Address delay time 3 tAD3 1/2tcyc 1/2tcyc + 12 ns 25.40, 25.41 Address setup time tAS 0 — ns 25.13 to 25.18 Address hold time tAH 0 — ns 25.13 to 25.
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Section 25 Electrical Characteristics Bφ = 50 MHz* Item Symbol Min. Max. Unit Figure(s) Write data delay time 1 tWDD1 — 14 ns 25.13 to 25.21 Write data delay time 2 tWDD2 — 14 ns 25.27 to 25.30, 25.34 to 25.36 Write data delay time 3 tWDD3 — 1/2tcyc + 14 ns 25.40 Write enable hold time 1 tWDH1 1 — ns 25.13 to 25.21 Write enable hold time 2 tWDH2 1 — ns 25.27 to 25.30, 25.34 to 25.36 Write enable hold time 3 tWDH3 1/2tcyc — ns 25.
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Section 25 Electrical Characteristics 25.3.4 Basic Timing T1 T2 CKIO tAD1 tAD1 A25 to A0 tAS tCSD1 tCSD1 tRWD1 tRWD1 CSn RD/WR tRSD tRSD RD tAH tRDH1 Read tRDS1 D31 to D0 tWED1 tWED1 tAH WEn Write tWDD1 tWDH1 D31 to D0 tBSD tBSD BS tDACD tDACD DACKn* Note: * Waveform for DACKn when active low is selected. Figure 25.13 Basic Bus Timing for Normal Space (No Wait) Rev. 4.00 Sep.
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Section 25 Electrical Characteristics T1 Tw T2 CKIO tAD1 tAD1 A25 to A0 tAS tCSD1 tCSD1 tRWD1 tRWD1 CSn RD/WR tRSD tRSD RD tAH tRDH1 tRDS1 Read D31 to D0 tWED1 tWED1 tAH WEn tWDD1 Write tWDH1 D31 to D0 tBSD tBSD BS tDACD tDACD DACKn* tWTH1 tWTS1 WAIT Note: * Waveform for DACKn when active low is selected. Figure 25.14 Basic Bus Timing for Normal Space (Software 1 Wait) Rev. 4.00 Sep.
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Section 25 Electrical Characteristics T1 TwX T2 CKIO tAD1 tAD1 A25 to A0 tAS tCSD1 tCSD1 CSn tRWD1 tRWD1 RD/WR tRSD tRSD RD tAH tRDH1 Read tRDS1 D31 to D0 tWED1 tWED1 tAH WEn tWDD1 Write tWDH1 D31 to D0 tBSD tBSD BS tDACD tDACD DACKn* tWTH1 tWTS1 tWTH1 tWTS1 WAIT Note: * Waveform for DACKn when active low is selected. Figure 25.15 Basic Bus Timing for Normal Space (One Cycle of Externally Input/WAITSEL = 0) Rev. 4.00 Sep.
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Section 25 Electrical Characteristics T1 TwX T2 CKIO tAD1 tAD1 A25 to A0 tAS tCSD1 tCSD1 CSn tRWD1 tRWD1 RD/WR tRSD tRSD RD tAH tRDH1 tRDS1 Read D31 to D0 tWED1 tWED1 tAH WEn tWDD1 Write tWDH1 D31 to D0 tBSD tBSD BS tDACD tDACD DACKn* tWTS2 tWTH2 tWTS2 tWTH2 WAIT Note: * Waveform for DACKn when active low is selected. Figure 25.16 Basic Bus Timing for Normal Space (One Cycle of Externally Input/WAITSEL = 1) Rev. 4.00 Sep.
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Section 25 Electrical Characteristics T1 Tw T2 Taw T1 Tw T2 Taw CKIO tAD1 tAD1 tAD1 tAD1 A25 to A0 tCSD1 tAS tAS tCSD1 tCSD1 tCSD1 tRWD1 tRWD1 tRWD1 CSn tRWD1 RD/WR tRSD tRSD RD tAH tRSD tRSD tRDH1 Read tAH tRDH1 tRDS1 tRDS1 D15 to D0 tWED1 tWED1 tWED1 tAH tWED1 tAH WEn Write tWDD1 tWDH1 tWDD1 tWDH1 D15 to D0 tBSD tBSD tBSD tBSD BS tDACD tDACD tDACD tDACD DACKn* tWTH1 tWTS1 tWTH1 tWTS1 WAIT Note: * Waveform for DACKn when active low is selected.
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Section 25 Electrical Characteristics Ta1 Ta2 Ta3 T1 Tw Tw T2 CKIO tAD1 tAD1 tCSD1 tCSD1 tRWD1 tRWD1 A25 to A0 CS5B RD/WR tAHD tAHD tAHD AH tRSD tRSD RD Read tRDH1 tMAH tMAD D15 to D0 tRDS1 Data Address tWED1 WE1 to WE0 tWED1 Write tWDD1 D15 to D0 tWDH1 tMAH tMAD Data Address tBSD tBSD BS tWTH1 tWTS1 tWTH1 tWTS1 WAIT tDACD tDACD DACKn* Note: * Waveform for DACKn when active low is selected. Figure 25.
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Section 25 Electrical Characteristics Tm1 Tmd1w Tmd1 CKIO tAD1 tAD1 A25 to A0 tCSD1 tCSD1 tRWD1 tRWD1 CS6B RD/WR tFMD tFMD tFMD FRAME tWDD1 tWDH1 tWDD1 tWDH1 tBSD tBSD tRDS2 Read D31 to D0 tWDD1 tRDH2 tWDH1 Write D31 to D0 BS tDACD tDACD DACKn, TENDn* tWTH1 WAIT tWTS1 RD WEn Note: * Waveform for DACKn and TENDn when active low is selected. Figure 25.19 Burst MPX-IO Interface Bus Cycle Single Read Write (One Address Cycle, One Software Wait) Rev. 4.00 Sep.
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Section 25 Electrical Characteristics 25.3.5 Bus Cycle of Byte-Selection SRAM Th T1 Twx T2 Tf CKIO tAD1 tAD1 tCSD1 tCSD1 A25 to A0 CSn tWED1 tWED1 WEn tRWD1 tRWD1 RD/WR tRSD tRSD RD Read tRDH1 tRDS1 D31 to D0 tRWD1 tRWD1 tWDD1 tWDH1 RD/WR Write D31 to D0 tBSD tBSD BS tDACD tDACD DACKn, TENDn* tWTH1 tWTH1 WAIT tWTS1 tWTS1 Note: * Waveform for DACKn and TENDn when active low is selected. Figure 25.
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Section 25 Electrical Characteristics Th T1 Twx T2 Tf CKIO tAD1 tAD1 tCSD1 tCSD1 tWED2 tWED2 A25 to A0 CSn WEn tRWD1 RD/WR tRSD Read tRSD RD tRDH1 tRDS1 D31 to D0 tRWD1 tRWD1 tRWD1 RD/WR tWDD1 Write tWDH1 D31 to D0 tBSD tBSD BS tDACD tDACD DACKn, TENDn* tWTH1 tWTH1 WAIT tWTS1 tWTS1 Note: * Waveform for DACKn and TENDn when active low is selected. Figure 25.
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Section 25 Electrical Characteristics 25.3.6 Burst ROM Read Cycle T1 Tw Twx T2B Twb T2B CKIO tAD1 tAD2 tAD2 tAD1 A25 to A0 tCSD1 tAS tCSD1 tRWD1 tRWD1 CSn RD/WR tRSD tRSD RD tRDS3 tRDH3 tRDS3 tRDH3 D31 to D0 WEn tBSD tBSD BS tDACD tDACD DACKn, TENDn* tWTH1 tWTH1 WAIT tWTS1 tWTS1 Note: * Waveform for DACKn and TENDn when active low is selected. Figure 25.22 Burst ROM Read Cycle (One Software Wait Cycle, One Asynchronous External Burst Wait Cycle, Two Burst) Rev. 4.
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Section 25 Electrical Characteristics 25.3.7 Synchronous DRAM Timing Tr Tc1 Tcw Td1 Tde CKIO tAD1 tAD1 Row address A25 to A0 tAD1 tAD1 Column address tAD1 tAD1 ReadA command A12/A11*1 tCSD1 tCSD1 CSn tRWD1 tRWD1 RD/WR tRASD1 tRASD1 RASU/L tCASD1 tCASD1 CASU/L tDQMD1 tDQMD1 DQMxx tRDS2 tRDH2 D31 to D0 tBSD tBSD BS (High) CKE tDACD tDACD DACKn*2 Note: 1. An address pin to be connected to pin A10 of SDRAM. 2. Waveform for DACKn when active low is selected. Figure 25.
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Section 25 Electrical Characteristics Tr Trw Tc1 Tcw Td1 Tde Tap CKIO tAD1 tAD1 Row address A25 to A0 tAD1 tAD1 Column address tAD1 tAD1 ReadA command A12/A11*1 tCSD1 tCSD1 CSn tRWD1 tRWD1 RD/WR tRASD1 tRASD1 RASU/L tCASD1 tCASD1 CASU/L tDQMD1 tDQMD1 DQMxx tRDS2 tRDH2 D31 to D0 tBSD tBSD BS (High) CKE tDACD tDACD DACKn*2 Note: 1. An address pin to be connected to pin A10 of SDRAM. 2. Waveform for DACKn when active low is selected. Figure 25.
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Section 25 Electrical Characteristics Tr TC1 TC2 Td1 Tc3 Td2 Tc4 Td3 Td4 Tde CKIO tAD1 tAD1 tAD1 Row address A25 to A0 tAD1 tAD1 Column address tAD1 tAD1 (1 to 4) tAD1 Read command A12/A11*1 tAD1 tAD1 ReadA command tCSD1 tCSD1 CSn tRWD1 tRWD1 RD/WR tRASD1 tRASD1 RASU/L tCASD1 tCASD1 CASU/L tDQMD1 tDQMD1 DQMxx tRDS2 tRDH2 tRDS2 tRDH2 D31 to D0 tBSD tBSD BS (High) CKE tDACD tDACD DACKn*2 Note: 1. An address pin to be connected to pin A10 of SDRAM. 2.
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Section 25 Electrical Characteristics Tr Trw Tc1 Tc2 Td1 Tc3 Td2 Tc4 Td3 Td4 Tde CKIO tAD1 tAD1 tAD1 tAD1 Column address Row address A25 to A0 tAD1 tAD1 (1 to 4) tAD1 tAD1 Read command A12/A11*1 tAD1 tAD1 ReadA command tCSD1 tCSD1 CSn tRWD1 tRWD1 RD/WR tRASD1 tRASD1 RASU/L tCASD1 tCASD1 CASU/L tDQMD1 tDQMD1 DQMxx tRDS2 tRDH2 tRDS2 tRDH2 D31 to D0 tBSD tBSD BS (High) CKE tDACD tDACD DACKn*2 Note: 1. An address pin to be connected to pin A10 of SDRAM. 2.
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Section 25 Electrical Characteristics Tr Tc1 Trwl CKIO tAD1 tAD1 Row address A25 to A0 tAD1 tAD1 Column address tAD1 tAD1 WriteA command A12/A11*1 tCSD1 tCSD1 CSn tRWD1 tRWD1 tRASD1 tRASD1 tRWD1 RD/WR RASU/L tCASD1 tCASD1 CASU/L tDQMD1 tDQMD1 DQMxx tWDD2 tWDH2 tBSD tBSD D31 to D0 BS (High) CKE tDACD tDACD DACKn*2 Note: 1. An address pin to be connected to pin A10 of SDRAM. 2. Waveform for DACKn when active low is selected. Figure 25.
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Section 25 Electrical Characteristics Tr Trw Trw Tc1 Trwl CKIO tAD1 Column address Row address A25 to A0 tAD1 tAD1 tAD1 tAD1 tAD1 WriteA command A12/A11*1 tCSD1 tCSD1 CSn tRWD1 tRWD1 tRWD1 tCASD1 tCASD1 RD/WR tRASD1 tRASD1 RASU/L CASU/L tDQMD1 tDQMD1 DQMxx tWDD2 tWDH2 tBSD tBSD D31 to D0 BS (High) CKE tDACD tDACD DACKn*2 Note: 1. An address pin to be connected to pin A10 of SDRAM. 2. Waveform for DACKn when active low is selected. Figure 25.
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Section 25 Electrical Characteristics Tr Tc1 Tc2 Tc3 Tc4 Trwl CKIO tAD1 tAD1 A25 to A0 tAD1 tAD1 tAD1 Row address tAD1 tAD1 Column address tAD1 tAD1 WRIT command A12/A11*1 tAD1 WriteA command tCSD1 tCSD1 CSn tRWD1 tRWD1 tRASD1 tRASD1 tRWD1 RD/WR RASU/L tCASD1 tCASD1 CASU/L tDQMD1 tDQMD1 DQMxx tWDD2 tWDH2 tWDD2 tWDH2 D31 to D0 tBSD tBSD BS (High) CKE tDACD tDACD DACKn*2 Note: 1. An address pin to be connected to pin A10 of SDRAM. 2.
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Section 25 Electrical Characteristics Tr Trw Tc1 Tc2 Tc3 Tc4 Trwl CKIO tAD1 tAD1 Row address A25 to A0 tAD1 tAD1 tAD1 tAD1 tAD1 Column address tAD1 tAD1 WRIT command A12/A11*1 tAD1 WriteA command tCSD1 tCSD1 CSn tRWD1 tRWD1 tRWD1 tCASD1 tCASD1 RD/WR tRASD1 tRASD1 RASU/L CASU/L tDQMD1 tDQMD1 DQMxx tWDD2 tWDH2 tWDD2 tWDH2 D31 to D0 tBSD tBSD BS (High) CKE tDACD tDACD DACKn*2 Note: 1. An address pin to be connected to pin A10 of SDRAM. 2.
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Section 25 Electrical Characteristics Tr Tc1 Td1 Tc3 Tc2 Td2 Tc4 Td3 Td4 Tde CKIO tAD1 tAD1 Row address A25 to A0 tAD1 tAD1 tAD1 tAD1 tAD1 Column address tAD1 tAD1 Read command A12/A11*1 tCSD1 tCSD1 CSn tRWD1 tRWD1 RD/WR tRASD1 tRASD1 RASU/L tCASD1 tCASD1 CASU/L tDQMD1 tDQMD1 DQMxx tRDS2 tRDH2 tRDS2 tRDH2 D31 to D0 tBSD tBSD BS (High) CKE tDACD tDACD DACKn*2 Note: 1. An address pin to be connected to pin A10 of SDRAM. 2.
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Section 25 Electrical Characteristics Tc1 Tc2 Td1 Tc3 Td2 Tc4 Td3 Td4 Tde CKIO tAD1 A25 to A0 tAD1 tAD1 Column address tAD1 A12/A11*1 tAD1 Read command tCSD1 tCSD1 CSn tRWD1 tRWD1 RD/WR tRASD1 RASU/L tCASD1 tCASD1 CASU/L tDQMD1 tDQMD1 DQMxx tRDS2 tRDH2 tRDS2 tRDH2 D31 to D0 tBSD tBSD BS (High) CKE tDACD tDACD DACKn*2 Note: 1. An address pin to be connected to pin A10 of SDRAM. 2. Waveform for DACKn when active low is selected. Figure 25.
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Section 25 Electrical Characteristics Tp Trw Tr Tc1 Tc2 Td1 Tc3 Td2 Tc4 Td3 Td4 Tde CKIO tAD1 tAD1 Row address A25 to A0 tAD1 tAD1 tAD1 tAD1 tAD1 Column address tAD1 tAD1 tAD1 Read command A12/A11*1 tCSD1 tCSD1 CSn tRWD1 tRWD1 tRASD1 tRASD1 tRWD1 RD/WR tRASD1 tRASD1 RASU/L tCASD1 tCASD1 CASU/L tDQMD1 tDQMD1 DQMxx tRDS2 tRDH2 tRDS2 tRDH2 D31 to D0 tBSD tBSD BS (High) CKE tDACD tDACD DACKn*2 Note: 1. An address pin to be connected to pin A10 of SDRAM. 2.
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Section 25 Electrical Characteristics Tr Tc1 Tc2 Tc3 Tc4 CKIO tAD1 tAD1 Row address A25 to A0 tAD1 tAD1 tAD1 tAD1 tAD1 Column address tAD1 tAD1 Write command A12/A11*1 tCSD1 tCSD1 CSn tRWD1 tRWD1 tRWD1 RD/WR tRASD1 tRASD1 RASU/L tCASD1 tCASD1 CASU/L tDQMD1 tDQMD1 DQMxx tWDD2 tWDH2 tWDD2 tWDH2 D31 to D0 tBSD tBSD BS (High) CKE tDACD tDACD DACKn*2 Note: 1. An address pin to be connected to pin A10 of SDRAM. 2. Waveform for DACKn when active low is selected. Figure 25.
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Section 25 Electrical Characteristics Tnop Tc1 Tc2 Tc3 Tc4 CKIO tAD1 tAD1 tAD1 tAD1 tAD1 Column address A25 to A0 tAD1 tAD1 tAD1 Write command A12/A11*1 tCSD1 tCSD1 CSn tRWD1 tRWD1 tRWD1 RD/WR RASU/L tCASD1 tCASD1 CASU/L tDQMD1 tDQMD1 DQMxx tWDD2 tWDH2 tWDD2 tWDH2 D31 to D0 tBSD tBSD BS (High) CKE tDACD tDACD DACKn*2 Note: 1. An address pin to be connected to pin A10 of SDRAM. 2. Waveform for DACKn when active low is selected. Figure 25.
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Section 25 Electrical Characteristics Tp Tpw Tr Tc1 Tc2 Tc3 Tc4 CKIO tAD1 tAD1 tAD1 tAD1 tAD1 tAD1 tAD1 tAD1 Column address Row address A25 to A0 tAD1 tAD1 Writecommand A12/A11*1 tCSD1 tCSD1 CSn tRWD1 tRWD1 tRASD1 tRASD1 tRWD1 tRWD1 RD/WR tRASD1 tRASD1 RASU/L tCASD1 tCASD1 CASU/L tDQMD1 tDQMD1 DQMxx tWDD2 tWDH2 tWDD2 tWDH2 D31 to D0 tBSD tBSD BS (High) CKE tDACD tDACD DACKn*2 Note: 1. An address pin to be connected to pin A10 of SDRAM. 2.
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Section 25 Electrical Characteristics Tp Tpw Trr Trc Trc Trc CKIO tAD1 tAD1 A25 to A0 tAD1 tAD1 A12/A11*1 tCSD1 tCSD1 tRWD1 tRWD1 tRASD1 tRASD1 tCSD1 tCSD1 CSn tRWD1 RD/WR tRASD1 tRASD1 tCASD1 tCASD1 RASU/L CASU/L DQMxx (Hi-Z)*3 D31 to D0 BS (High) CKE DACKn*2 Note: 1. An address pin to be connected to pin A10 of SDRAM. 2. Waveform for DACKn when active low is selected. 3. Pins D31 to D16 with weak keeper are retained as weak keepers. Figure 25.
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Section 25 Electrical Characteristics Tp Tpw Trr Trc Trc Trc Trc CKIO tAD1 tAD1 A25 to A0 tAD1 tAD1 A12/A11*1 tCSD1 tCSD1 tRWD1 tRWD1 tRASD1 tRASD1 tCSD1 tCSD1 CSn tRWD1 RD/WR tRASD1 tRASD1 tCASD1 tCASD1 RASU/L CASU/L DQMxx (Hi-Z)*3 D31 to D0 BS tCKED1 tCKED1 CKE DACKn*2 Note: 1. An address pin to be connected to pin A10 of SDRAM. 2. Waveform for DACKn when active low is selected. 3. Pins D31 to D16 with weak keeper are retained as weak keepers. Figure 25.
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Section 25 Electrical Characteristics Tp Tpw Trr Trc Trc Trr Trc Trc Tmw Tde CKIO PALL REF REF MRS tAD1 tAD1 tAD1 A25 to A0 tAD1 tAD1 A12/A11*1 tCSD1 tCSD1 tCSD1 tCSD1 tCSD1 tCSD1 tCSD1 tCSD1 tRWD1 tRWD1 tRWD1 CSn tRWD1 tRWD1 RD/WR tRASD1 tRASD1 tRASD1 tRASD1 tRASD1 tRASD1 tRASD1 tRASD1 tCASD1 tCASD1 tCASD1 tCASD1 tCASD1 tCASD1 RASU/L CASU/L DQMxx (Hi-Z)*3 D31 to D0 BS CKE DACKn*2 Note: 1. An address pin to be connected to pin A10 of SDRAM. 2.
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Section 25 Electrical Characteristics Tr Tc Td1 Tde Tap Tr Tc Tnop Trw1 Tap CKIO tAD3 A25 to A0 tAD3 tAD3 Row address Column address tAD3 tAD3 tAD3 tAD3 tAD3 tAD3 Row address tAD3 Column address tAD3 tAD3 ReadA Command A12/A11*1 tCSD2 tAD3 WriteA Command tCSD2 tCSD2 tCSD2 CSn tRWD2 tRWD2 tRWD2 RD/WR tRASD2 tRASD2 tCASD2 tCASD2 tRASD2 tRASD2 RASU/L tCASD2 tCASD2 tCASD2 CASU/L tDQMD2 tDQMD2 tDQMD2 tDQMD2 DQMxx tRDS4 tRDH4 tWDD3 tWDH3 tBSD tBSD D31
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Section 25 Electrical Characteristics Tp Tpw Trr Trc Trc Trc CKIO tAD3 tAD3 tAD3 tAD3 A25 to A0 A12/A11*1 tCSD2 tCSD2 tRWD2 tRWD2 tRASD2 tRASD2 tCSD2 tCSD2 tRASD2 tRASD2 tCASD2 tCASD2 CSn RD/WR RASU/L tCASD2 CASU/L tDQMD2 DQMxx (Hi-Z)*3 D31 to D0 BS tCKED2 tCKED2 CKE DACKn, TENDn*2 Note: 1. 2. 3. An address pin to be connected to pin A10 of SDRAM. Waveform for DACKn and TENDn when active low is selected. Pins D31 to D16 with weak keeper are retained as weak keepers.
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Section 25 Electrical Characteristics 25.3.8 Peripheral Module Signal Timing Table 25.9 Peripheral Module Signal Timing Conditions: VCCQ = 3.0 V to 3.6 V, VCC = 1.8 V ± 5%, AVCC = 3.0 V to 3.6 V, VSS = VSSQ = AVSS = 0 V, Ta = −40°C to +85°C Module Item Symbol Min. SCIF tScyc Input clock cycle (synchronous) (asynchronous) PORT * Unit Figure(s) 16 — tPcyc 25.42 4 — tPcyc 25.42 Input clock rising time tSCKR — 1.5 tPcyc 25.42 Input clock falling time tSCKF — 1.5 tPcyc 25.
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Section 25 Electrical Characteristics tScyc SCK tTXD TxD (data transmission) tRXS tRXH RxD (data reception) Figure 25.43 SCIF Input/Output Timing in Synchronous Mode CKIO tPORTS tPORTH Ports 7 to 0 (read) tPORTD Ports 7 to 0 (write) Figure 25.44 I/O Port Timing CKIO tDRQS tDRQH DREQn Figure 25.45 DREQ Input Timing CKIO tDACD tDACD TEND DACKn Figure 25.46 DACK, TEND Output Timing Rev. 4.00 Sep.
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Section 25 Electrical Characteristics 25.3.9 Multi Function Timer Pulse Unit Timing Table 25.10 lists the multi function timer pulse unit timing. Table 25.10 Multi Function Timer Pulse Unit Timing Conditions: VCC = 1.8 V ± 5%, VCCQ = AVCC = 3.0 V to 3.6 V, VSS = VSSQ = AVSS = 0 V, Ta = −40°C to +85°C Item Symbol Min. Max.
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Section 25 Electrical Characteristics 25.3.10 POE Module Signal Timing Table 25.11 Output Enable (POE) Timing Conditions: VCC = 1.8 V ± 5%, VCCQ = AVCC = 3.0 V to 3.6 V, VSS = VSSQ = AVSS = 0 V, Ta = −40°C to +85°C Item Symbol Min. Max. Unit Figure(s) POE input setup time tPOES Bcyc/2+10 — ns 25.49 POE input pulse width tPOEW 1.5 — tpcyc CKIO tPOES POEn input tPOEW Figure 25.49 POE Input/Output Timing Rev. 4.00 Sep.
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Section 25 Electrical Characteristics 25.3.11 I2C Module Signal Timing Table 25.12 I2C Bus Interface Timing Normal Conditions: VCC = 1.8 V ± 5%, AVCC = VCCQ = 3.0 V to 3.6 V, VSS = AVSS = VSSQ = 0 V, Ta = −40°C to +85°C Specifications Item Symbol Min. Typ. Max. Unit Figure(s) SCL input cycle time tSCL Test Conditions 12 tPcyc + 600 — — ns 25.
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Section 25 Electrical Characteristics VIH SDA VIL tBUF tSTAH tSCLH tSTAS tSP tSTOS SCL P* S* tSF tSCLL [Legend] tSCL S: Start condition P: Stop condition Sr: Start condition for retransmission Sr* P* tSDAS tSR tSDAH Figure 25.50 I2C Bus Interface Input/Output Timing Rev. 4.00 Sep.
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Section 25 Electrical Characteristics 25.3.12 H-UDI Related Pin Timing Table 25.13 H-UDI Related Pin Timing Conditions: VCCQ = 3.0 V to 3.6 V, VCC = 1.8 V ± 5%, AVCC = 3.0 V to 3.6 V, VSS = VSSQ = AVSS = 0 V, Ta = −40°C to +85°C Item Symbol Min. Max. Unit Figure(s) TCK cycle time tTCKcyc 50 — ns 25.51 TCK high pulse width tTCKH 0.4 0.6 tTckcyc TCK low pulse width tTCKL 0.4 0.
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Section 25 Electrical Characteristics RESETP tTRSTS tTRSTH TRST Figure 25.52 TRST Input Timing (Reset-Hold State) tTCKcyc TCK tTDIS tTDIH tTMSS tTMSH TDI TMS tTDOD When boundary scan is not performed tTDOD TDO When boundary scan is performed Figure 25.53 H-UDI Data Transfer Timing TCK tCAPTS tCAPTH Capture Register tUPDATED Update Register Figure 25.54 Boundary-Scan Input/Output Timing Rev. 4.00 Sep.
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Section 25 Electrical Characteristics 25.3.13 USB Module Signal Timing Table 25.14 USB Module Clock Timing Conditions: VCC = 1.8 V ±5%, VCCQ = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, VSS = VSSQ = AVSS = 0 V, Ta = −40°C to +85°C Item Symbol Min. Max. Unit Figure(s) Frequency (48 MHz) tFREQ 47.9 48.1 MHz 25.55 Clock rising time tRAS — 4 ns Clock falling time tFAS — 4 ns Duty cycle (tHIGH/tLOW) tDUTY 90 110 % tFREQ tHIGH UCLK tLOW 90% 10% tRAS tFAS Figure 25.
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Section 25 Electrical Characteristics 25.3.14 USB Transceiver Timing Table 25.15 USB Transceiver Timing Conditions: VCC = 1.8 V ±5%, VCCQ = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, VSS = VSSQ = AVSS = 0 V, Ta = −40°C to +85°C Item Symbol Min. Typ. Max. Unit Test Conditions Rising time tR 4  20 ns CL = 50pF Falling time tF 4 — 20 ns CL = 50pF Rising/falling time ratio tR/tF 90 — 110 % Output crossover voltage VCRS 1.3 — 2.
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Section 25 Electrical Characteristics 25.3.15 AC Characteristics Measurement Conditions • I/O signal reference level: VCCQ/2 (VCCQ = 3.0 to 3.6 V, VCC = 1.8 V ± 5%) • Input pulse level: VSSQ to 3.0 V (where RESETP, RESETM, ASEMD0, NMI, TRST, EXTAL, CKIO, TCK, MD0, MD2, MD3, and Schmitt inputs are within VSSQ to VCCQ) • Input rising and falling times: 1 ns IOL DUT output LSI output pin VREF CL IOH Notes: 1. 2. CL is the total value that includes the capacitance of measurement tools.
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Section 25 Electrical Characteristics 25.4 A/D Converter Characteristics Table 25.16 lists the A/D converter characteristics. Table 25.16 A/D Converter Characteristics Conditions: VCCQ = 3.0 to 3.6 V, VCC = 1.8 V ± 5%, AVCC = 2.7 V to 3.6 V, VSSQ = VSS = AVSS = 0 V, Ta = −40°C to +85°C Item Min. Typ. Max. Unit Resolution 10 10 10 bits Conversion time — — 10.
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Section 25 Electrical Characteristics Rev. 4.00 Sep.
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Appendix Appendix A. Pin States A.1 When Other Function is Selected Table A.
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Appendix Reset State Power Down Mode Sleep BusReleased Reset Type Pin Name Power-On Manual Software Standby Data bus D[15:0] Z I Z I Z D[31:16] Z+ I+ Z+ I+ Z+*6 H O Z/H*3 O Z O Z+ O Z O O/Z+*2*6 Bus control CS0 CS6[A,B] Z+ O Z+/H* H O Z/H*3 3 CS5[A,B] CS[2:4] BS CAS[U,L] 2 Z+ O O/Z+* H O Z/H* 3 O Z H O Z/H*3 O Z CKE Z+ O O/Z+*2 O O/Z+*2*6 WAIT Z I++ Z I++ Z O Z+ RAS[U,L] WE0/DQMLL WE1/DQMLU WE2/DQMUL WE3/DQMUU/AH RD/WR RD DMAC FRAME Z+
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Appendix Reset State Power Down Mode Type Pin Name Power-On Manual Software Standby SCIF[2:0] RxD[2:0] Z+ Z+ TxD[2:0] SCK[2:0] RTS[2:0] AUD H-UDI* USB 8 Z+ Z+ Z+ I+ O/Z+ I+/O I+/O Sleep BusReleased Reset I+ I+ 4 O/Z+ O/Z+ 4 I+/O I+/O 4 I+/O I+/O O/Z+* K/Z+* K/Z+* CTS[2:0] Z+ I+/O K/Z+* I+/O I+/O AUDSYNC Z+ O O O O AUDCK O O O O O AUDATA[3:0] Z+ O O O O ASEBRKAK O O O O O 4 ASEMD0 I I* I* TCK I++ I++ TDI I++ I++ 5 5 5 I* I*5 I++ I
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Appendix [Legend] I: Input I+: Input with weak keeper I++: Input with pull-up MOS O: Output L: Low level output H: High level output Z: Hi-Z (The pin must not be open since the intermediate level at this pin caused a pass though current in the LSI.) Z+: Hi-Z with weak keeper Z++: Hi-Z with pull-up MOS K: Input becomes Hi-Z, output retains state Notes: 1. The EXTAL pin must be pulled up and the XTAL pin must be open. 2. Controlled by the HIZCNT bit in the common control register of the BSC. 3.
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Appendix A.2 When I/O Port is Selected Table A.
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Appendix B. Product Lineup Product Model Package (Code) SH7641 HD6417641BP100 (100 MHz version) P-LFBGA1717-256* Note: * For details of packages, please contact your nearest Renesas Technology sales representative. Rev. 4.00 Sep.
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Appendix Package Dimensions φ0.08 M C φ0.15 M C A B φ0.44 to 0.64 (256 ×) A1 CORNER 20 18 16 14 12 10 8 6 4 2 19 17 15 13 11 9 7 5 3 1 A B C 0.80 D E F G J 15.20 17.00 ± 0.05 H K L M N P R T U V W Y 0.80 A 15.20 17.00 ± 0.05 B 0.20 C 0.15 C 1.40 Max C 0.35 to 0.45 C. 0.15 (4 ×) Package Code JEDEC JEITA P-LFBGA-1717-256 – – Figure C.1 Package Dimensions Rev. 4.00 Sep.
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Appendix Rev. 4.00 Sep.
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Main Revisions and Additions in this Edition Item Page Revisions (See Manual for Details) General Precautions on Handling of Product iv Section 9 Exception Handling 217 5. added. ; 9.5 Note on Initializing this LSI MOV.W MOV.L MOV MOV.B MOV.B MOV.B MOV.L #H'FF40,R10; #H'A4FC0000,R8; #H'10,R9; R10,@R10; R10,@R10; R10,@R10; R9,@R8; MOV.L MOV.W #H'FC000000,R1; @R1,R0; MOV MOV.B MOV.B MOV.B #H'00,R9; R10,@R10; R10,@R10; R10,@R10; ; ; Section 13 Direct Memory Access Controller (DMAC) 446 Added.
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Item Page Revisions (See Manual for Details) Section 25 Electrical Characteristics 949 to 951 and Figure 25.37 Synchronous DRAM Auto-Refreshing Timing D31 to D0 953 (WTRP = 1 Cycle, WTRC = 3 Cycles) Figure 25.38 Synchronous DRAM Self-Refreshing Timing (WTRP = 1 Cycle) Figure 25.39 Synchronous DRAM Mode Register Write Timing (WTRP = 1 Cycle) Figure 25.41 Synchronous DRAM Self-Refreshing Timing in Low-Frequency Mode (WTRP = 2 Cycles) Rev. 4.00 Sep.
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Index Numerics Bus Cycle of Byte-Selection SRAM....... 932 16-Bit/32-Bit displacement....................... 47 Bus state controller ........................................ 146 Bus State Controller................................ 269 Byte-selection SRAM interface .............. 377 A A/D conversion time............................... 810 A/D converter ......................................... 797 A/D Converter Characteristics................ 965 Absolute addresses ...................................
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Direct Memory Access Controller.......... 405 Divider.................................................... 145 DMA address error ................................. 209 DSP addressing....................................... 124 DSP data instructions................................ 84 DSP operation..................................... 88, 99 DSP registers ............................................ 35 Dual address mode.................................. 433 E Endian..............................................
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Multiply and accumulate high register ..... 26 Multiply and accumulate low register....... 26 Multiply/multiply-and-accumulate operations ................................................. 45 Q Quantization error ................................... 813 R N NMI interrupt.......................................... 233 Noise canceler......................................... 501 Nonlinearity error ................................... 813 Normal space interface ........................... 324 O Offset error ....
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ICDRS ................................................ 487 ICDRT ................................................ 487 ICIER.................................................. 482 ICMR.................................................. 480 ICR ..................................................... 225 ICSR ................................................... 484 ICSR1 ................................................. 675 IMCR.................................................. 231 IMR .............................
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USBEPDR0i ....................................... 756 USBEPDR0o ...................................... 756 USBEPDR0s....................................... 757 USBEPSTL......................................... 763 USBEPSZ0o ....................................... 758 USBEPSZ1 ......................................... 759 USBFCLR .......................................... 761 USBIER.............................................. 754 USBIFR .............................................. 750 USBISR ............
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X X/Y data addressing.................................. 52 Rev. 4.00 Sep. 14, 2005 Page 982 of 982 REJ09B0023-0400 X/Y memory ...........................................
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Renesas 32-Bit RISC Microcomputer Hardware Manual SH7641 Publication Date: Rev.1.00 Sep 19, 2003 Rev.4.00 Sep 14, 2005 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp.  2005. Renesas Technology Corp., All rights reserved. Printed in Japan.
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Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan RENESAS SALES OFFICES http://www.renesas.com Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.
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SH7641 Hardware Manual