SH7780 Series MPU/MPC SuperH RISC Engine Family Model SH7781 Hardware Manual

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Revision Date: Jan. 10

2008

Hardware Manual

Renesas 32-Bit RISC Microcomputer

SuperH™ RISC Engine Family

SH7780 Series

Rev.1.00

REJ09B0261-0100

SH7785

Summary of content (1692 pages)

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REJ09B0261-0100 32 SH7785 Hardware Manual Renesas 32-Bit RISC Microcomputer SuperH™ RISC Engine Family SH7780 Series Rev.1.00 Revision Date: Jan.
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Notes regarding these materials 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2.
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General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1.
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Rev.1.00 Jan.
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Preface This LSI is a RISC (Reduced Instruction Set Computer) microcomputer which includes a Renesas Technology-original RISC CPU (SH-4A) and various peripheral functions required to configure a system. Target Users: This manual was written for users who will be using this LSI in the design of application systems. Users of this manual are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers.
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Abbreviations ALU Arithmetic Logic Unit ASID Address Space Identifier BGA Ball Grid Array CMT Timer/Counter (Compare Match Timer) CPG Clock Pulse Generator CPU Central Processing Unit DDR Double Data Rate DDRIF DDR-SDRAM Interface DMA Direct Memory Access DMAC Direct Memory Access Controller FIFO First-In First-Out FPU Floating-point Unit HAC Audio Codec H-UDI User Debugging Interface INTC Interrupt Controller JTAG Joint Test Action Group LBSC Local Bus State Controller LRA
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MSB Most Significant Bit PC Program Counter PCI Peripheral Component Interconnect PCIC PCI (local bus) Controller PFC Pin Function Controller RISC Reduced Instruction Set Computer RTC Realtime Clock SCIF Serial Communication Interface with FIFO SIOF Serial Interface with FIFO SSI Serial Sound Interface TAP Test Access Port TLB Translation Lookaside Buffer TMU Timer Unit UART Universal Asynchronous Receiver/Transmitter UBC User Break Controller WDT Watchdog Timer Rev.1.00 Jan.
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All trademarks and registered trademarks are the property of their respective owners. Rev.1.00 Jan.
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Contents Section 1 Overview .................................................................................................................. 1 1.1 1.2 1.3 1.4 1.5 Features of the SH7785.......................................................................................................... 1 Block Diagram ..................................................................................................................... 13 Pin Arrangement Table ..........................................................
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5.3 5.4 5.5 5.6 5.7 5.2.2 Exception Event Register (EXPEVT)................................................................... 91 5.2.3 Interrupt Event Register (INTEVT)...................................................................... 92 5.2.4 Non-Support Detection Exception Register (EXPMASK) ................................... 93 Exception Handling Functions............................................................................................. 95 5.3.1 Exception Handling Flow ..............
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7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.1.1 Address Spaces ................................................................................................... 146 Register Descriptions ......................................................................................................... 152 7.2.1 Page Table Entry High Register (PTEH)............................................................ 153 7.2.2 Page Table Entry Low Register (PTEL) ............................................................. 154 7.
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7.8.1 Overview of 32-Bit Address Extended Mode..................................................... 199 7.8.2 Transition to 32-Bit Address Extended Mode .................................................... 200 7.8.3 Privileged Space Mapping Buffer (PMB) Configuration ................................... 200 7.8.4 PMB Function..................................................................................................... 202 7.8.5 Memory-Mapped PMB Configuration ..........................................
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8.7 8.8 Store Queues ...................................................................................................................... 238 8.7.1 SQ Configuration................................................................................................ 238 8.7.2 Writing to SQ...................................................................................................... 238 8.7.3 Transfer to External Memory..............................................................................
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10.4 Interrupt Sources................................................................................................................ 324 10.4.1 NMI Interrupts.................................................................................................... 324 10.4.2 IRQ Interrupts..................................................................................................... 324 10.4.3 IRL Interrupts ..................................................................................................
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11.5.9 11.5.10 11.5.11 11.5.12 11.5.13 11.5.14 Bus Arbitration ................................................................................................... 448 Master Mode....................................................................................................... 450 Slave Mode ......................................................................................................... 451 Cooperation between Master and Slave..............................................................
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12.5.11 Method for Securing Time Required for Initialization, Self-Refresh Cancellation, etc. ................................................................................................ 549 12.5.12 Regarding the Supported Clock Ratio ................................................................ 549 12.5.13 Regarding MCKE Signal Operation ................................................................... 550 Section 13 PCI Controller (PCIC) ..........................................................
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14.4.2 Channel Priority.................................................................................................. 706 14.4.3 DMA Transfer Types.......................................................................................... 709 14.4.4 DMA Transfer Flow ........................................................................................... 717 14.4.5 Repeat Mode Transfer ........................................................................................ 719 14.4.
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16.4.1 Reset Request ..................................................................................................... 769 16.4.2 Using Watchdog Timer Mode ............................................................................ 771 16.4.3 Using Interval Timer Mode ................................................................................ 771 16.4.4 Time until WDT Counters Overflow.................................................................. 772 16.4.5 Clearing WDT Counters ..............
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18.3.4 Timer Control Registers (TCRn) (n = 0 to 5) ..................................................... 807 18.3.5 Input Capture Register 2 (TCPR2) ..................................................................... 809 18.4 Operation ........................................................................................................................... 810 18.4.1 Counter Operation .............................................................................................. 810 18.4.
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19.3.26 Color Palette 4 Transparent Color Register (CP4TR) ........................................ 887 19.3.27 Display Off Mode Output Register (DOOR)...................................................... 890 19.3.28 Color Detection Register (CDER) ...................................................................... 891 19.3.29 Background Plane Output Register (BPOR)....................................................... 892 19.3.30 Raster Interrupt Offset Register (RINTOFSR) ............................
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19.4.12 Scroll Display ..................................................................................................... 950 19.4.13 Wraparound Display ........................................................................................... 951 19.4.14 Upper-Left Overflow Display............................................................................. 952 19.4.15 Double Buffer Control ........................................................................................ 953 19.4.16 Sync Mode ..
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20.4 20.5 20.6 20.7 20.3.21 MC Command FIFO (MCCF) .......................................................................... 1000 20.3.22 MC Status Register (MCSR) ............................................................................ 1003 20.3.23 MC Frame Width Setting Register (MCWR) ................................................... 1004 20.3.24 MC Frame Height Setting Register (MCHR) ................................................... 1005 20.3.25 MC Y Padding Size Setting Register (MCYPR) ...
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21.3.12 Serial Port Register n (SCSPTR) ...................................................................... 1066 21.3.13 Line Status Register n (SCLSR) ....................................................................... 1069 21.3.14 Serial Error Register n (SCRER) ...................................................................... 1070 21.4 Operation ......................................................................................................................... 1071 21.4.1 Overview ......
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23.2 Input/Output Pins............................................................................................................. 1153 23.3 Register Descriptions....................................................................................................... 1153 23.3.1 Control Register (SPCR) .................................................................................. 1155 23.3.2 Status Register (SPSR) .....................................................................................
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24.4.1 Operations in MMC Mode................................................................................ 1209 24.5 MMCIF Interrupt Sources................................................................................................ 1239 24.6 Operations when Using DMA.......................................................................................... 1240 24.6.1 Operation in Read Sequence............................................................................. 1240 24.6.
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.4 Operation ......................................................................................................................... 1314 26.4.1 Bus Format ....................................................................................................... 1314 26.4.2 Non-Compressed Modes .................................................................................. 1315 26.4.3 Compressed Modes........................................................................................... 1324 26.4.
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Section 28 General Purpose I/O Ports (GPIO)........................................................... 1377 28.1 Features............................................................................................................................ 1377 28.2 Register Descriptions ....................................................................................................... 1382 28.2.1 Port A Control Register (PACR) ...................................................................... 1386 28.2.
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.2.37 Port L Pull-Up Control Register (PLPUPR)..................................................... 1438 28.2.38 Port M Pull-Up Control Register (PMPUPR)................................................... 1439 28.2.39 Port N Pull-Up Control Register (PNPUPR) .................................................... 1440 28.2.40 Input-Pin Pull-Up Control Register 1 (PPUPR1) ............................................. 1441 28.2.41 Input-Pin Pull-Up Control Register 2 (PPUPR2) ..................................
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30.3.2 Interrupt Source Register (SDINT)................................................................... 1492 30.3.3 Bypass Register (SDBPR) ................................................................................ 1493 30.3.4 Boundary Scan Register (SDBSR) ................................................................... 1493 30.4 Operation ......................................................................................................................... 1503 30.4.
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Appendix A. B. C. D. E. F. ............................................................................................................................ 1627 Package Dimensions ........................................................................................................ 1627 Mode Pin Settings............................................................................................................ 1628 Pin Functions ..............................................................................
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1. Overview Section 1 Overview The SH7785 incorporates a DDR2-SDRAM interface, a PCI controller, a DMA controller, timers, serial interfaces, audio interfaces, a graphics data translation accelerator (GDTA) that supports YUV data conversion and motion compensation processing, and a display unit (DU) that supports digital RGB display.
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1.
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1.
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1.
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1.
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1. Overview Item Features Local bus state controller (LBSC) • A dedicated Local-bus interface ⎯ Controls the external memory space divided into seven 64-Mbyte (max.) areas ⎯ The interface type, bus width, and wait-cycle insertion can be set for each area. • SRAM interface ⎯ Wait-cycle insertion can be set by register values.
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1.
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1. Overview Item Features PCI bus controller (PCIC) • PCI bus controller (supports a subset of revision 2.
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1.
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1.
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1. Overview Item Features Synchronized serial • I/O with FIFO • (SIOF) • Serial protocol interface (HSPI) Multimedia card interface (MMCIF) Audio codec interface (HAC) Number of channels: One (max.
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1. Overview Item Features Serial sound interface (SSI) • Number of channels: Two (max.) • Supports transfer of compressed and non-compressed data • Selectable frame size • Number of channels: One (max.
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1. Overview 1.2 Block Diagram A block diagram of the SH7785 is given as figure 1.1.
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1. Overview 1.3 Pin Arrangement Table Table 1.2 Pin Function No. Pin Name I/O Function No.
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1. Overview No. Pin Name I/O Function No.
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1. Overview No. Pin Name I/O Function No.
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1. Overview No. Pin Name I/O Function 155 D37/AD5/DR5 IO/IO/O Local bus data 37/PCI No.
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1. Overview No. Pin Name I/O 181 D63/AD31 IO/IO Function No.
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1. Overview No. Pin Name I/O Function No.
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1. Overview No. Pin Name I/O 249 SIOF_SCK/ IO/I/IO HAC0_BITCLK/ Function No.
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1. Overview No. Pin Name I/O Function No.
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1. Overview 1.4 Pin Arrangement Package: 436-pin FC-BGA, 19 mm x 19 mm, ball pitch: 0.
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1.
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1. Overview 1.5 Physical Memory Address Map The SH7785 supports 32-bit virtual address space, and supports both 29-bit and 32-bit physical address spaces. For details of mappings from the virtual address space to the physical address spaces, see section 7, Memory Management Unit (MMU). Figure 1.4 shows the relationship between the AREASEL bits and the physical memory address map. The 32-bit physical address space corresponds with the address space of the SuperHyway bus.
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2. Programming Model Section 2 Programming Model The programming model of this LSI is explained in this section. This LSI has registers and data formats as shown below. 2.1 Data Formats The data formats supported in this LSI are shown in figure 2.1.
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2. Programming Model 2.2 Register Descriptions 2.2.1 Privileged Mode and Banks (1) Processing Modes This LSI has two processing modes, user mode and privileged mode. This LSI normally operates in user mode, and switches to privileged mode when an exception occurs or an interrupt is accepted. There are four kinds of registers—general registers, system registers, control registers, and floating-point registers—and the registers that can be accessed differ in the two processing modes.
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2. Programming Model (DBR), which can only be accessed in privileged mode. Some bits of the status register (such as the RB bit) can only be accessed in privileged mode. (4) System Registers System registers comprise the multiply-and-accumulate registers (MACH/MACL), the procedure register (PR), and the program counter (PC). Access to these registers does not depend on the processing mode.
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2. Programming Model Table 2.
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2.
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2. Programming Model 2.2.2 General Registers Figure 2.3 shows the relationship between the processing modes and general registers. This LSI has twenty-four 32-bit general registers (R0_BANK0 to R7_BANK0, R0_BANK1 to R7_BANK1, and R8 to R15). However, only 16 of these can be accessed as general registers R0 to R15 in one processing mode. This LSI has two processing modes, user mode and privileged mode. • R0_BANK0 to R7_BANK0 Allocated to R0 to R7 in user mode (SR.MD = 0) Allocated to R0 to R7 when SR.
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2. Programming Model Note on Programming: 2.2.3 As the user's R0 to R7 are assigned to R0_BANK0 to R7_BANK0, and after an exception or interrupt R0 to R7 are assigned to R0_BANK1 to R7_BANK1, it is not necessary for the interrupt handler to save and restore the user's R0 to R7 (R0_BANK0 to R7_BANK0). Floating-Point Registers Figure 2.4 shows the floating-point register configuration.
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2. Programming Model 7. Single-precision floating-point extended register matrix, XMTRX: XMTRX comprises all 16 XF registers. XMTRX = XF0 XF1 XF2 XF3 XF4 XF5 XF6 XF7 XF8 XF9 XF10 XF11 XF12 XF13 XF14 XF15 FPSCR.FR = 0 FV0 DR0 DR2 FV4 DR4 DR6 FV8 DR8 DR10 FV12 DR12 DR14 XMTRX XD0 XD2 XD4 XD6 XD8 XD10 XD12 XD14 FPSCR.
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2. Programming Model 2.2.
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2. Programming Model Bit Bit Name 27 to 16 — Initial Value R/W Description All 0 R Reserved For details on reading/writing this bit, see General Precautions on Handling of Product. 15 FD 0 R/W FPU Disable Bit When this bit is set to 1 and an FPU instruction is not in a delay slot, a general FPU disable exception occurs. When this bit is set to 1 and an FPU instruction is in a delay slot, a slot FPU disable exception occurs. (FPU instructions: H'F*** instructions and LDS (.L)/STS(.
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2. Programming Model (2) Saved Status Register (SSR) (32 bits, Privileged Mode, Initial Value = Undefined) The contents of SR are saved to SSR in the event of an exception or interrupt. (3) Saved Program Counter (SPC) (32 bits, Privileged Mode, Initial Value = Undefined) The address of an instruction at which an interrupt or exception occurs is saved to SPC.
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2.
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2. Programming Model Bit Bit Name 17 to 12 Cause Initial Value R/W Description 000000 R/W FPU Exception Cause Field FPU Exception Enable Field FPU Exception Flag Field Each time an FPU operation instruction is executed, the FPU exception cause field is cleared to 0. When an FPU exception occurs, the bits corresponding to FPU exception cause field and flag field are set to 1. The FPU exception flag field remains set to 1 until it is cleared to 0 by software.
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2. Programming Model 63 0 Floating-point register DR (2i) 63 0 FR (2i) 63 FR (2i+1) 32 31 0 Memory area 8n 8n+3 8n+4 8n+7 63 0 Floating-point register 63 0 0 *2 63 32 31 0 FR (2i) FR (2i+1) 63 0 DR (2i) *1, *2 63 FR (2i) 63 DR (2i) DR (2i) 0 63 4m 8n+3 63 FR (2i+1) 32 31 0 FR (2i) 0 63 8n+4 8n+7 FR (2i+1) 32 31 0 8n+4 8n+3 8n Memory area 4n+3 4n 4m+3 (1) SZ = 0 8n 8n+7 (2) SZ = 1, PR = 0 (3) SZ = 1, PR = 1 Notes: 1.
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2. Programming Model 2.3 Memory-Mapped Registers Some control registers are mapped to the following memory areas. Each of the mapped registers has two addresses. H'1C00 0000 to H'1FFF FFFF H'FC00 0000 to H'FFFF FFFF These two areas are used as follows. • H'1C00 0000 to H'1FFF FFFF This area must be accessed using the address translation function of the MMU. Setting the page number of this area to the corresponding field of the TLB enables access to a memory-mapped register.
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2. Programming Model 2.4 Data Formats in Registers Register operands are always longwords (32 bits). When a memory operand is only a byte (8 bits) or a word (16 bits), it is sign-extended into a longword when loaded into a register. 7 6 0 S 31 S 7 6 S 15 14 0 0 S 31 S 15 14 S 0 Figure 2.6 Formats of Byte Data and Word Data in Register 2.5 Data Formats in Memory Memory data formats are classified into bytes, words, and longwords.
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2. Programming Model A+1 A 31 7 A+2 23 A+3 15 07 07 A + 11 A + 10 A + 9 7 0 31 07 0 7 0 15 Address A Byte 0 Byte 1 Byte 2 Byte 3 Address A + 4 Address A + 8 15 0 15 Word 0 31 Big endian 07 07 7 0 07 0 0 15 Word 1 0 A+8 15 Byte 3 Byte 2 Byte 1 Byte 0 Address A + 8 Word 1 Longword 23 31 0 Word 0 Longword 0 Address A + 4 Address A Little endian Figure 2.7 Data Formats in Memory For the 64-bit data format, see figure 2.5. 2.
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2. Programming Model From any state when reset/manual reset input Reset state Reset/manual reset clearance Reset/manual reset input Instruction execution state Reset/manual reset input Sleep instruction execution Power-down state Interrupt occurence Figure 2.8 Processing State Transitions Rev.1.00 Jan.
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2. Programming Model 2.7 Usage Notes 2.7.1 Notes on Self-Modifying Code To accelerate the processing speed, the instruction prefetching capability of this LSI has been significantly enhanced from that of the SH-4. Therefore, in the case when a code in memory is rewritten and attempted to be executed immediately, there is increased possibility that the code before being modified, which has already been prefetched, is executed.
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2. Programming Model Rev.1.00 Jan.
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3. Instruction Set Section 3 Instruction Set This LSI's instruction set is implemented with 16-bit fixed-length instructions. This LSI can use byte (8-bit), word (16-bit), longword (32-bit), and quadword (64-bit) data sizes for memory access. Single-precision floating-point data (32 bits) can be moved to and from memory using longword or quadword size. Double-precision floating-point data (64 bits) can be moved to and from memory using longword size.
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3. Instruction Set Table 3.1 Execution Order of Delayed Branch Instructions Instructions BRA TARGET ADD TARGET Execution Order (Delayed branch instruction) BRA (Delay slot) ↓ : ADD : ↓ target-inst (Branch destination instruction) target-inst A slot illegal instruction exception may occur when a specific instruction is executed in a delay slot. For details, see section 5, Exception Handling.
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3. Instruction Set 3.2 Addressing Modes Addressing modes and effective address calculation methods are shown in table 3.2. When a location in virtual memory space is accessed (AT in MMUCR = 1), the effective address is translated into a physical memory address. If multiple virtual memory space systems are selected (SV in MMUCR = 0), the least significant bit of PTEH is also referenced as the access ASID. For details, see section 7, Memory Management Unit (MMU). Table 3.
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3. Instruction Set Addressing Mode Instruction Format Register indirect with predecrement @–Rn Effective Address Calculation Method Effective address is register Rn contents, decremented by a constant beforehand: 1 for a byte operand, 2 for a word operand, 4 for a longword operand, 8 for a quadword operand.
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3. Instruction Set Addressing Mode Instruction Format GBR indirect @(disp:8, with displace- GBR) ment Effective Address Calculation Method Effective address is register GBR contents with 8-bit displacement disp added. After disp is zero-extended, it is multiplied by 1 (byte), 2 (word), or 4 (longword), according to the operand size.
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3. Instruction Set Addressing Instruction Mode Format Effective Address Calculation Method Calculation Formula PC-relative PC + 4 + disp × 2 → BranchTarget disp:8 Effective address is PC + 4 with 8-bit displacement disp added after being sign-extended and multiplied by 2. PC + 4 + PC + 4 + disp × 2 disp (sign-extended) × 2 PC-relative disp:12 Effective address is PC + 4 with 12-bit displacement disp added after being sign-extended and multiplied by 2.
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3. Instruction Set Addressing Instruction Mode Format Effective Address Calculation Method Calculation Formula Immediate #imm:8 8-bit immediate data imm of TST, AND, OR, or XOR instruction is zero-extended. — #imm:8 8-bit immediate data imm of MOV, ADD, or CMP/EQ instruction is sign-extended. — #imm:8 8-bit immediate data imm of TRAPA instruction is zero-extended and multiplied by 4.
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3. Instruction Set 3.3 Instruction Set Table 3.3 shows the notation used in the SH instruction lists shown in tables 3.4 to 3.13. Table 3.3 Notation Used in Instruction List Item Format Description Instruction mnemonic OP.
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3. Instruction Set Item Format Privileged mode Description "Privileged" means the instruction can only be executed in privileged mode. T bit Value of T bit after —: No change instruction execution New ⎯ "New" means the instruction which has been newly added in the SH-4A with H’20-valued VER bits in the processor version register (PVR). Note: Scaling (×1, ×2, ×4, or ×8) is executed according to the size of the instruction operand. Table 3.
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3. Instruction Set Instruction Operation Instruction Code Privileged T Bit New MOV.B @(disp*,Rm),R0 (disp + Rm) → sign extension → R0 10000100mmmmdddd — — — MOV.W @(disp*,Rm),R0 (disp × 2 + Rm) → sign extension → R0 10000101mmmmdddd — — — MOV.L @(disp*,Rm),Rn (disp × 4 + Rm) → Rn 0101nnnnmmmmdddd — — — MOV.B Rm,@(R0,Rn) Rm → (R0 + Rn) 0000nnnnmmmm0100 — — — MOV.W Rm,@(R0,Rn) Rm → (R0 + Rn) 0000nnnnmmmm0101 — — — MOV.
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3. Instruction Set Instruction Operation Instruction Code Privileged T Bit New MOVT Rn T → Rn 0000nnnn00101001 — — — SWAP.B Rm,Rn Rm → swap lower 2 bytes → Rn 0110nnnnmmmm1000 — — — SWAP.W Rm,Rn Rm → swap upper/lower words → Rn 0110nnnnmmmm1001 — — — XTRCT Rm,Rn Rm:Rn middle 32 bits → Rn 0010nnnnmmmm1101 — — — Note: * Table 3.5 The assembler of Renesas uses the value after scaling (×1, ×2, or ×4) as the displacement (disp).
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3. Instruction Set Instruction Operation Instruction Code Privileged T Bit New CMP/STR Rm,Rn When any bytes are equal, 0010nnnnmmmm1100 1→T Otherwise, 0 → T — Comparison — result DIV1 Rm,Rn 1-step division (Rn ÷ Rm) 0011nnnnmmmm0100 — Calculation result — DIV0S Rm,Rn MSB of Rn → Q, MSB of Rm → M, M^Q → T 0010nnnnmmmm0111 — Calculation result — 0 → M/Q/T 0000000000011001 — 0 — DIV0U DMULS.L Rm,Rn Signed, Rn × Rm → MAC, 32 × 32 → 64 bits 0011nnnnmmmm1101 — — — DMULU.
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3. Instruction Set Instruction Operation Instruction Code Privileged T Bit New — — — MULU.W Rm,Rn Unsigned, Rn × Rm → MACL 16 × 16 → 32 bits 0010nnnnmmmm1110 NEG Rm,Rn 0 – Rm → Rn 0110nnnnmmmm1011 — — — NEGC Rm,Rn 0 – Rm – T → Rn, borrow → T 0110nnnnmmmm1010 — Borrow — SUB Rm,Rn Rn – Rm → Rn 0011nnnnmmmm1000 — — — SUBC Rm,Rn Rn – Rm – T → Rn, borrow → T 0011nnnnmmmm1010 — Borrow — SUBV Rm,Rn Rn – Rm → Rn, underflow → T 0011nnnnmmmm1011 — Underflow — Table 3.
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3. Instruction Set Instruction Operation Instruction Code Privileged T Bit New XOR R0 ∧ imm → R0 11001010iiiiiiii — — — (R0 + GBR) ∧ imm → (R0 + GBR) 11001110iiiiiiii — — — #imm,R0 XOR.B #imm, @(R0,GBR) Table 3.
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3. Instruction Set Table 3.
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3. Instruction Set Instruction Operation Instruction Code Privileged T Bit New LDC Rm,SSR Rm → SSR 0100mmmm00111110 Privileged — — LDC Rm,SPC Rm → SPC 0100mmmm01001110 Privileged — — LDC Rm,DBR Rm → DBR 0100mmmm11111010 Privileged — — LDC Rm,Rn_BANK Rm → Rn_BANK (n = 0 to 7) 0100mmmm1nnn1110 Privileged — — LDC.L @Rm+,SR (Rm) → SR, Rm + 4 → Rm Privileged LSB — LDC.L @Rm+,GBR (Rm) → GBR, Rm + 4 → Rm 0100mmmm00010111 — — — LDC.
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3.
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3. Instruction Set Instruction Operation Instruction Code Privileged T Bit New SYNCO Data accesses invoked by the following instructions are not executed until execution of data accesses which precede this instruction has been completed. 0000000010101011 ⎯ ⎯ New PC + 2 → SPC, 11000011iiiiiiii SR → SSR, R15 → SGR, 1 → SR.MD/BL/RB, #imm << 2 → TRA, H'160 → EXPEVT, VBR + H'0100 → PC — — — TRAPA #imm Table 3.
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3.
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3. Instruction Set Table 3.12 Floating-Point Control Instructions Instruction Operation Instruction Code Privileged T Bit LDS Rm,FPSCR New Rm → FPSCR 0100mmmm01101010 — — — LDS Rm,FPUL Rm → FPUL 0100mmmm01011010 — — — LDS.L @Rm+,FPSCR (Rm) → FPSCR, Rm+4 → Rm 0100mmmm01100110 — — — LDS.L @Rm+,FPUL (Rm) → FPUL, Rm+4 → Rm 0100mmmm01010110 — — — STS FPSCR,Rn FPSCR → Rn 0000nnnn01101010 — — — STS FPUL,Rn FPUL → Rn 0000nnnn01011010 — — — STS.
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4. Pipelining Section 4 Pipelining This LSI is a 2-ILP (instruction-level-parallelism) superscalar pipelining microprocessor. Instruction execution is pipelined, and two instructions can be executed in parallel. 4.1 Pipelines Figure 4.1 shows the basic pipelines. Normally, a pipeline consists of eight stages: instruction fetch (I1/I2/I3), decode and register read (ID), execution (E1/E2/E3), and write-back (WB). An instruction is executed as a combination of basic pipelines. 1.
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4. Pipelining Figure 4.2 shows the instruction execution patterns. Representations in figure 4.2 and their descriptions are listed in table 4.1. Table 4.
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4. Pipelining (1-1) BF, BF/S, BT, BT/S, BRA, BSR:1 issue cycle + 0 to 3 branch cycles I1 I2 I3 ID E1/S1 E2/s2 E3/s3 (I1) (I2) (I3) WB Note: In branch instructions that are categorized as (1-1), the number of branch cycles may be reduced by prefetching.
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4. Pipelining (2-1) 1-step operation (EX type): 1 issue cycle EXT[SU].
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4. Pipelining (3-1) Load/store: 1 issue cycle MOV.[BWL], MOV.[BWL] @(d,GBR) I1 I2 I3 ID S1 S2 S3 WB S2 S3 WB ID E1S1 E2S2 E3S3 S2 E1S1 ID S3 E2S2 WB E3S3 WB ID E1S1 E2S2 (3-2) AND.B, OR.B, XOR.B, TST.B: 3 issue cycles I1 I2 ID I3 S1 ID WB (3-3) TAS.B: 4 issue cycles I1 I3 I2 ID S1 ID E3S3 WB (3-4) PREF, OCBI, OCBP, OCBWB, MOVCA.
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4. Pipelining (4-1) LDC to Rp_BANK/SSR/SPC/VBR: 1 issue cycle I1 I2 I3 ID s1 s2 s3 WB s1 ID s2 s3 WB (4-2) LDC to DBR/SGR: 4 issue cycles I1 I2 I3 ID ID ID (4-3) LDC to GBR: 1 issue cycle I1 I2 I3 ID s1 s2 s3 WB E3s3 WB (4-4) LDC to SR: 4 issue cycles + 4 branch cycles I1 I2 I3 ID E1s1 ID E2s2 ID ID (I1) I2 I3 ID S1 (I3) (ID) (Branch to the next instruction.) (4-5) LDC.L to Rp_BANK/SSR/SPC/VBR: 1 issue cycle I1 (I2) S2 S3 WB S2 S3 WB (4-6) LDC.
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4. Pipelining (4-9) STC from DBR/GBR/Rp_BANK/SSR/SPC/VBR/SGR: 1 issue cycle I1 I2 I3 ID s1 s2 s3 WB ID E1s1 E2s2 E3s3 WB (4-10) STC from SR: 1 issue cycle I1 I2 I3 (4-11) STC.L from DBR/GBR/Rp_BANK/SSR/SPC/VBR/SGR: 1 issue cycle I1 I2 I3 S1 S2 S3 WB ID E1S1 E2S2 E3S3 WB ID s1 s2 s3 WB ID S1 S2 S3 WB ID s1 s2 s3 WB S1 S2 S3 WB ID (4-12) STC.L from SR: 1 issue cycle I1 I2 I3 (4-13) LDS to PR: 1 issue cycle I1 I2 I3 (4-14) LDS.
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4. Pipelining (5-1) LDS to MACH/L: 1 issue cycle I1 I2 I3 ID s1 s2 s3 WB MS S1 S2 S3 WB MS s1 s2 s3 WB MS S1 S2 S3 WB MS E1 M2 M3 MS M2 M3 M2 M3 (5-2) LDS.L to MACH/L: 1 issue cycle I1 I2 I3 ID (5-3) STS from MACH/L: 1 issue cycle I1 I2 I3 ID (5-4) STS.L from MACH/L: 1 issue cycle I1 I2 I3 ID (5-5) MULS.W, MULU.W: 1 issue cycle I1 I2 I3 ID (5-6) DMULS.L, DMULU.L, MUL.
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4. Pipelining (6-1) LDS to FPUL: 1 issue cycle I1 I2 I3 ID s1 FS1 s2 FS2 s3 FS3 FS4 FS1 s1 FS2 s2 FS3 s3 FS4 WB S1 FS1 S2 FS2 S3 FS3 WB FS4 FS1 S1 FS2 S2 FS3 S3 FS4 WB s1 FS1 s2 FS2 s3 FS3 FS4 FS1 s1 FS2 s2 FS3 s3 FS4 WB S1 FS1 S2 FS2 S3 FS3 WB FS4 (6-8) STS.L from FPSCR: 1 issue cycle I3 ID I1 I2 FS1 S1 FS2 S2 FS3 S3 FS4 WB FS (6-2) STS from FPUL: 1 issue cycle I1 I2 I3 ID (6-3) LDS.L to FPUL: 1 issue cycle I1 I2 I3 ID (6-4) STS.
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4.
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4.
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4. Pipelining 4.2 Parallel-Executability Instructions are categorized into six groups according to the internal function blocks used, as shown in table 4.2. Table 4.3 shows the parallel-executability of pairs of instructions in terms of groups. For example, ADD in the EX group and BRA in the BR group can be executed in parallel. Table 4.
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4. Pipelining Instruction Group FE CO Instruction FADD FDIV FRCHG FSCA FSUB FIPR FSCHG FSRRA FCMP (S/D) FLOAT FSQRT FPCHG FCNVDS FMAC FTRC FCNVSD FMUL FTRV AND.B #imm,@(R0,GBR) LDC.L @Rm+,SR PREFI TRAPA ICBI LDTLB RTE TST.B #imm,@(R0,GBR) LDC Rm,DBR MAC.L SLEEP XOR.B #imm,@(R0,GBR) LDC Rm, SGR MAC.W STC SR,Rn LDC Rm,SR MOVCO STC.L SR,@-Rn LDC.L @Rm+,DBR MOVLI SYNCO LDC.L @Rm+,SGR OR.B #imm,@(R0,GBR) TAS.
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4. Pipelining Table 4.3 Combination of Preceding and Following Instructions Preceding Instruction (addr) EX Following Instruction (addr+2) MT BR LS FE EX No Yes Yes Yes Yes MT Yes Yes Yes Yes Yes BR Yes Yes No Yes Yes LS Yes Yes Yes No Yes FE Yes Yes Yes Yes No CO Rev.1.00 Jan.
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4. Pipelining 4.3 Issue Rates and Execution Cycles Instruction execution cycles are summarized in table 4.4. Instruction Group in the table 4.4 corresponds to the category in the table 4.2. Penalty cycles due to a pipeline stall are not considered in the issue rates and execution cycles in this section. 1. Issue Rate Issue rates indicates the issue period between one instruction and next instruction. E.g. AND.
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4. Pipelining Table 4.4 Functional Category Data transfer instructions Issue Rates and Execution Cycles No. Instruction Instruction Group Execution Execution Pattern Issue Rate Cycles 1 EXTS.B Rm,Rn EX 1 1 2-1 2 EXTS.W Rm,Rn EX 1 1 2-1 3 EXTU.B Rm,Rn EX 1 1 2-1 4 EXTU.W Rm,Rn EX 1 1 2-1 5 MOV Rm,Rn MT 1 1 2-4 6 MOV #imm,Rn MT 1 1 2-3 7 MOVA @(disp,PC),R0 LS 1 1 2-2 8 MOV.W @(disp,PC),Rn LS 1 1 3-1 9 MOV.L @(disp,PC),Rn LS 1 1 3-1 10 MOV.
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4. Pipelining Functional Category Data transfer instructions Fixed-point arithmetic instructions Instruction Group Execution Execution Pattern Issue Rate Cycles Rm,@-Rn LS 1 1 3-1 No. Instruction 30 MOV.L 31 MOV.B R0,@(disp,Rn) LS 1 1 3-1 32 MOV.W R0,@(disp,Rn) LS 1 1 3-1 33 MOV.L Rm,@(disp,Rn) LS 1 1 3-1 34 MOV.B Rm,@(R0,Rn) LS 1 1 3-1 35 MOV.W Rm,@(R0,Rn) LS 1 1 3-1 36 MOV.L Rm,@(R0,Rn) LS 1 1 3-1 37 MOV.B R0,@(disp,GBR) LS 1 1 3-1 38 MOV.
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4. Pipelining Functional Category Fixed-point arithmetic instructions Logical instructions No. Instruction Rm,Rn Instruction Group Execution Execution Pattern Issue Rate Cycles EX 1 60 CMP/GT 61 CMP/HI Rm,Rn EX 1 1 2-1 62 CMP/HS Rm,Rn EX 1 1 2-1 63 CMP/PL Rn EX 1 1 2-1 64 CMP/PZ Rn EX 1 1 2-1 65 CMP/STR Rm,Rn EX 1 1 2-1 66 DIV0S Rm,Rn EX 1 1 2-1 67 DIV0U EX 1 1 2-1 68 DIV1 Rm,Rn EX 1 1 2-1 69 DMULS.L Rm,Rn EX 1 2 5-6 70 DMULU.
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4. Pipelining Functional Category Logical instructions Shift instructions Branch instructions No. Instruction 90 TST Rm,Rn Instruction Group Execution Execution Pattern Issue Rate Cycles EX 1 1 2-1 91 TST #imm,R0 EX 1 1 2-1 92 TST.B #imm,@(R0,GBR) CO 3 3 3-2 93 XOR Rm,Rn EX 1 1 2-1 94 XOR #imm,R0 EX 1 1 2-1 95 XOR.
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4. Pipelining Functional Category Branch instructions System control instruction No.
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4. Pipelining Functional Category System control instructions No. Instruction 150 LDC.L @Rm+,SPC Instruction Group Execution Execution Pattern Issue Rate Cycles LS 1 1 4-5 151 LDC.L @Rm+,VBR LS 1 1 4-5 152 LDS Rm,MACH LS 1 1 5-1 153 LDS Rm,MACL LS 1 1 5-1 154 LDS Rm,PR LS 1 1 4-13 155 LDS.L @Rm+,MACH LS 1 1 5-2 156 LDS.L @Rm+,MACL LS 1 1 5-2 157 LDS.
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4. Pipelining Functional Category Singleprecision floating-point instructions No. Instruction 180 FLDI0 FRn Instruction Group Execution Execution Pattern Issue Rate Cycles LS 1 1 6-13 181 FLDI1 FRn LS 1 1 6-13 182 FMOV FRm,FRn LS 1 1 6-9 183 FMOV.S @Rm,FRn LS 1 1 6-9 184 FMOV.S @Rm+,FRn LS 1 1 6-9 185 FMOV.S @(R0,Rm),FRn LS 1 1 6-9 186 FMOV.S FRm,@Rn LS 1 1 6-9 187 FMOV.S FRm,@-Rn LS 1 1 6-9 188 FMOV.
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4. Pipelining Functional Category Doubleprecision floating-point instructions FPU system control instructions Graphics acceleration instructions No.
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4. Pipelining Functional Category Graphics acceleration instructions No. Instruction Instruction Group Execution Execution Pattern Issue Rate Cycles 241 FRCHG FE 1 1 6-14 242 FSCHG FE 1 1 6-14 243 FPCHG FE 1 1 6-14 244 FSRRA FRn FE 1 1 6-21 245 FSCA FPUL,DRn FE 1 3 6-22 246 FTRV XMTRX,FVn FE 1 4 6-20 Rev.1.00 Jan.
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5. Exception Handling Section 5 Exception Handling 5.1 Summary of Exception Handling Exception handling processing is handled by a special routine which is executed by a reset, general exception handling, or interrupt. For example, if the executing instruction ends abnormally, appropriate action must be taken in order to return to the original program sequence, or report the abnormality before terminating the processing.
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5. Exception Handling Table 5.2 States of Register in Each Operating Mode Register Name Abbr. Power-on Reset Manual Reset Sleep Standby TRAPA exception register TRA Undefined Undefined Retained Retained Exception event register EXPEVT H'0000 0000 H'0000 0020 Retained Retained Interrupt event register INTEVT Undefined Retained Retained Non-support detection exception register EXPMASK H'0000 0013 H'0000 0013 Retained Retained 5.2.
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5. Exception Handling 5.2.2 Exception Event Register (EXPEVT) The exception event register (EXPEVT) consists of a 12-bit exception code. The exception code set in EXPEVT is that for a reset or general exception event. The exception code is set automatically by hardware when an exception occurs. EXPEVT can also be modified by software.
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5. Exception Handling 5.2.3 Interrupt Event Register (INTEVT) The interrupt event register (INTEVT) consists of a 14-bit exception code. The exception code is set automatically by hardware when an exception occurs. INTEVT can also be modified by software.
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5. Exception Handling 5.2.4 Non-Support Detection Exception Register (EXPMASK) The non-support detection exception register (EXPMASK) is used to enable or disable the generation of exceptions in response to the use of any of functions 1 to 3 listed below. The functions of 1 to 3 are planned not to be supported in the future SuperH-family products.
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5. Exception Handling Bit Bit Name Initial Value R/W Description 31 to 5 ⎯ All 0 R Reserved For details on reading/writing these bits, see General Precautions on Handling of Product. 4 MMCAW 1 R/W Memory-Mapped Cache Associative Write 0: Memory-mapped cache associative write is disabled. (A data address error exception will occur.) 1: Memory-mapped cache associative write is enabled. For further details, refer to section 8.6.5, MemoryMapped Cache Associative Write Operation.
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5. Exception Handling 5.3 Exception Handling Functions 5.3.1 Exception Handling Flow In exception handling, the contents of the program counter (PC), status register (SR), and R15 are saved in the saved program counter (SPC), saved status register (SSR), and saved general register15 (SGR), and the CPU starts execution of the appropriate exception handling routine according to the vector address. An exception handling routine is a program written by the user to handle a specific exception.
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5. Exception Handling 5.4 Exception Types and Priorities Table 5.3 shows the types of exceptions, with their relative priorities, vector addresses, and exception/interrupt codes. Table 5.
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5. Exception Handling Exception Transition 3 Direction* Exception Execution Category Mode Exception Priority Priority 2 2 Level* Order* Vector Address Offset Exception 4 Code* General exception Completion type Unconditional trap (TRAPA) 2 4 (VBR) H'100 H'160 User break after instruction execution* 2 10 (VBR/DBR) H'100/— H'1E0 Interrupt Completion type Nonmaskable interrupt 3 — (VBR) H'600 H'1C0 General interrupt request 4 — (VBR) H'600 — Notes: 1.
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5. Exception Handling 5.5 Exception Flow 5.5.1 Exception Flow Figure 5.1 shows an outline flowchart of the basic operations in instruction execution and exception handling. For the sake of clarity, the following description assumes that instructions are executed sequentially, one by one. Figure 5.1 shows the relative priority order of the different kinds of exceptions (reset, general exception, and interrupt).
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5. Exception Handling Reset requested? Yes No Execute next instruction General exception requested? Yes No Interrupt requested? No Is highestYes priority exception re-exception type? Cancel instruction execution No result Yes SSR ← SR SPC ← PC SGR ← R15 EXPEVT/INTEVT ← exception code SR.{MD,RB,BL} ← 111 SR.IMASK ← received interuupt level (*) PC ← (CBCR.UBDE=1 && User_Break? DBR: (VBR + Offset)) EXPEVT ← exception code SR.
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5. Exception Handling 5.5.2 Exception Source Acceptance A priority ranking is provided for all exceptions for use in determining which of two or more simultaneously generated exceptions should be accepted.
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5. Exception Handling 5.5.3 Exception Requests and BL Bit When the BL bit in SR is 0, general exceptions and interrupts are accepted. When the BL bit in SR is 1 and an general exception other than a user break is generated, the CPU's internal registers and the registers of the other modules are set to their states following a manual reset, and the CPU branches to the same address as in a reset (H'A0000000). For the operation in the event of a user break, see section 29, User Break Controller (UBC).
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5. Exception Handling 5.6 Description of Exceptions The various exception handling operations explained here are exception sources, transition address on the occurrence of exception, and processor operation when a transition is made. 5.6.1 (1) Resets Power-On Reset • Condition: Power-on reset request • Operations: Exception code H'000 is set in EXPEVT, initialization of the CPU and on-chip peripheral module is carried out, and then a branch is made to the reset vector (H'A0000000).
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5. Exception Handling (4) Instruction TLB Multiple Hit Exception • Source: Multiple ITLB address matches • Transition address: H'A0000000 • Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred. Exception code H'140 is set in EXPEVT, initialization of VBR and SR is performed, and a branch is made to PC = H'A0000000.
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5. Exception Handling 5.6.2 (1) General Exceptions Data TLB Miss Exception • Source: Address mismatch in UTLB address comparison • Transition address: VBR + H'00000400 • Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred.
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5. Exception Handling (2) Instruction TLB Miss Exception • Source: Address mismatch in ITLB address comparison • Transition address: VBR + H'00000400 • Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred. The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR.
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5. Exception Handling (3) Initial Page Write Exception • Source: TLB is hit in a store access, but dirty bit D = 0 • Transition address: VBR + H'00000100 • Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred. The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR.
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5. Exception Handling (4) Data TLB Protection Violation Exception • Source: The access does not accord with the UTLB protection information (PR bits or EPR bits) shown in table 5.4 and table 5.5. Table 5.
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5. Exception Handling The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR. The R15 contents at this time are saved in SGR. Exception code H'0A0 (for a read access) or H'0C0 (for a write access) is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0100. Data_TLB_protection_violation_exception() { TEA = EXCEPTION_ADDRESS; PTEH.
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5. Exception Handling (5) Instruction TLB Protection Violation Exception • Source: The access does not accord with the ITLB protection information (PR bits or EPR bits) shown in table 5.6 and table5.7. Table 5.6 ITLB Protection Information (TLB Compatible Mode) PR Privileged Mode User Mode 0 Access possible Access not possible 1 Access possible Access possible Table 5.
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5. Exception Handling ITLB_protection_violation_exception() { TEA = EXCEPTION_ADDRESS; PTEH.VPN = PAGE_NUMBER; SPC = PC; SSR = SR; SGR = R15; EXPEVT = H'0000 00A0; SR.MD = 1; SR.RB = 1; SR.
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5. Exception Handling • Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred. The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR. The R15 contents at this time are saved in SGR. Exception code H'0E0 (for a read access) or H'100 (for a write access) is set in EXPEVT.
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5. Exception Handling (7) Instruction Address Error • Sources: ⎯ Instruction fetch from other than a word boundary (2n +1) ⎯ Instruction fetch from area H'80000000 to H'FFFFFFFF in user mode Area H'E5000000 to H'E5FFFFFF can be accessed in user mode. For details, see section 9, On-Chip Memory.
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5. Exception Handling (8) Unconditional Trap • Source: Execution of TRAPA instruction • Transition address: VBR + H'00000100 • Transition operations: As this is a processing-completion-type exception, the PC contents for the instruction following the TRAPA instruction are saved in SPC. The value of SR and R15 when the TRAPA instruction is executed are saved in SSR and SGR. The 8-bit immediate value in the TRAPA instruction is multiplied by 4, and the result is set in TRA [9:0].
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5.
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5. Exception Handling (10) Slot Illegal Instruction Exception • Sources: ⎯ Decoding of an undefined instruction in a delay slot Delayed branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S Undefined instruction: H'FFFD ⎯ Decoding of an instruction that modifies PC in a delay slot Instructions that modify PC: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT, BF, BT/S, BF/S, TRAPA, LDC Rm,SR, LDC.
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5. Exception Handling (11) General FPU Disable Exception • Source: Decoding of an FPU instruction* not in a delay slot with SR.FD = 1 • Transition address: VBR + H'00000100 • Transition operations: The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR. The R15 contents at this time are saved in SGR. Exception code H'800 is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0100.
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5. Exception Handling (12) Slot FPU Disable Exception • Source: Decoding of an FPU instruction in a delay slot with SR.FD =1 • Transition address: VBR + H'00000100 • Transition operations: The PC contents for the preceding delayed branch instruction are saved in SPC. The SR and R15 contents when this exception occurred are saved in SSR and SGR. Exception code H'820 is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0100.
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5. Exception Handling (13) Pre-Execution User Break/Post-Execution User Break • Source: Fulfilling of a break condition set in the user break controller • Transition address: VBR + H'00000100, or DBR • Transition operations: In the case of a post-execution break, the PC contents for the instruction following the instruction at which the breakpoint is set are set in SPC. In the case of a pre-execution break, the PC contents for the instruction at which the breakpoint is set are set in SPC.
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5. Exception Handling (14) FPU Exception • Source: Exception due to execution of a floating-point operation • Transition address: VBR + H'00000100 • Transition operations: The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR . The R15 contents at this time are saved in SGR. Exception code H'120 is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0100.
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5. Exception Handling 5.6.3 (1) Interrupts NMI (Nonmaskable Interrupt) • Source: NMI pin edge detection • Transition address: VBR + H'00000600 • Transition operations: The PC and SR contents for the instruction immediately after this exception is accepted are saved in SPC and SSR. The R15 contents at this time are saved in SGR. Exception code H'1C0 is set in INTEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0600.
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5. Exception Handling The code corresponding to the each interrupt source is set in INTEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to VBR + H'0600. When the INTMU bit in CPUOPM is 1, IMASK bit in SR is changed to accepted interrupt level. For details, see section 10, Interrupt Controller (INTC). Module_interruption() { SPC = PC; SSR = SR; SGR = R15; INTEVT = H'0000 0400 ~ H'0000 3FE0; SR.MD = 1; SR.RB = 1; SR.BL = 1; if (cond) SR.
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5. Exception Handling 8. Initial page write exception in second data transfer (2) Indivisible Delayed Branch Instruction and Delay Slot Instruction As a delayed branch instruction and its associated delay slot instruction are indivisible, they are treated as a single instruction. Consequently, the priority order for exceptions that occur in these instructions differs from the usual priority order. The priority order shown below is for the case where the delay slot instruction has only one data transfer.
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5. Exception Handling 5.7 (1) Usage Notes Return from Exception Handling A. Check the BL bit in SR with software. If SPC and SSR have been saved to memory, set the BL bit in SR to 1 before restoring them. B. Issue an RTE instruction. When RTE is executed, the SPC contents are saved in PC, the SSR contents are saved in SR, and branch is made to the SPC address to return from the exception handling routine. (2) If a General Exception or Interrupt Occurs When BL Bit in SR = 1 A.
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5. Exception Handling other exceptions is determined depending on the processing mode by SR after restoring or the BL bit. The completion type exception is accepted before branching to the destination of RTE instruction. However, if the re-execution type exception is occurred, the operation cannot be guaranteed. B. The user break is not accepted by the instruction in the delay slot of the RTE instruction. (5) Changing the SR Register Value and Accepting Exception A.
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6. Floating-Point Unit (FPU) Section 6 Floating-Point Unit (FPU) 6.1 Features The FPU has the following features.
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6. Floating-Point Unit (FPU) 6.2 Data Formats 6.2.1 Floating-Point Format A floating-point number consists of the following three fields: • Sign bit (s) • Exponent field (e) • Fraction field (f) This LSI can handle single-precision and double-precision floating-point numbers, using the formats shown in figures 6.1 and 6.2. 31 30 s 23 22 e 0 f Figure 6.1 Format of Single-Precision Floating-Point Number 63 62 s 52 51 e 0 f Figure 6.
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6. Floating-Point Unit (FPU) Table 6.
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6. Floating-Point Unit (FPU) Table 6.
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6. Floating-Point Unit (FPU) 6.2.2 Non-Numbers (NaN) Figure 6.3 shows the bit pattern of a non-number (NaN). A value is NaN in the following case: • Sign bit: Don't care • Exponent field: All bits are 1 • Fraction field: At least one bit is 1 The NaN is a signaling NaN (sNaN) if the MSB of the fraction field is 1, and a quiet NaN (qNaN) if the MSB is 0. 31 30 x 23 22 11111111 0 Nxxxxxxxxxxxxxxxxxxxxxx N = 1:sNaN N = 0:qNaN Figure 6.
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6. Floating-Point Unit (FPU) See section 10, Instruction Descriptions of the SH-4A Extended Functions Software Manual for details of floating-point operations when a non-number (NaN) is input. 6.2.3 Denormalized Numbers For a denormalized number floating-point value, the exponent field is expressed as 0, and the fraction field as a non-zero value.
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6. Floating-Point Unit (FPU) 6.3 Register Descriptions 6.3.1 Floating-Point Registers Figure 6.4 shows the floating-point register configuration. There are thirty-two 32-bit floatingpoint registers comprised with two banks: FPR0_BANK0 to FPR15_BANK0, and FPR0_BANK1 to FPR15_BANK1. These thirty-two registers are referenced as FR0 to FR15, DR0/2/4/6/8/10/12/14, FV0/4/8/12, XF0 to XF15, XD0/2/4/6/8/10/12/14, and XMTRX.
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6. Floating-Point Unit (FPU) 7. Single-precision floating-point extended register matrix, XMTRX: XMTRX comprises all 16 XF registers. XMTRX = XF0 XF1 XF2 XF3 XF4 XF5 XF6 XF7 XF8 XF9 XF10 XF11 XF12 XF13 XF14 XF15 FPSCR.FR = 0 FV0 DR0 DR2 FV4 DR4 DR6 FV8 DR8 DR10 FV12 DR12 DR14 XMTRX XD0 XD2 XD4 XD6 XD8 XD10 XD12 XD14 FPSCR.
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6. Floating-Point Unit (FPU) 6.3.
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6. Floating-Point Unit (FPU) Initial Value R/W Description 17 to 12 Cause All 0 R/W 11 to 7 Enable All 0 R/W 6 to 2 Flag All 0 R/W FPU Exception Cause Field FPU Exception Enable Field FPU Exception Flag Field Each time an FPU operation instruction is executed, the FPU exception cause field is cleared to 0. When an FPU exception occurs, the bits corresponding to FPU exception cause field and flag field are set to 1.
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6. Floating-Point Unit (FPU) 63 0 Floating-point register DR (2i) 63 0 FR (2i) 63 FR (2i+1) 32 31 0 Memory area 8n 8n+3 8n+4 8n+7 63 0 Floating-point register 63 0 DR (2i) 0 63 FR (2i+1) 32 31 63 0 DR (2i) *2 *1, *2 63 FR (2i) 63 DR (2i) 0 FR (2i) 0 63 4m 8n+3 63 FR (2i+1) 32 31 0 FR (2i) FR (2i+1) 0 63 32 31 0 8n+4 8n+7 8n+4 8n+3 8n Memory area 4n+3 4n 4m+3 (1) SZ = 0 8n 8n+7 (2) SZ = 1, PR = 0 (3) SZ = 1, PR = 1 Notes: 1.
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6. Floating-Point Unit (FPU) Table 6.3 Bit Allocation for FPU Exception Handling Field Name FPU Error (E) Invalid Operation (V) Division by Zero (Z) Overflow (O) Underflo w (U) Inexact (I) Cause FPU exception cause field Bit 17 Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Enable FPU exception enable field None Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Flag FPU exception flag field None Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 6.3.
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6. Floating-Point Unit (FPU) 6.4 Rounding In a floating-point instruction, rounding is performed when generating the final operation result from the intermediate result. Therefore, the result of combination instructions such as FMAC, FTRV, and FIPR will differ from the result when using a basic instruction such as FADD, FSUB, or FMUL. Rounding is performed once in FMAC, but twice in FADD, FSUB, and FMUL. Which of the two rounding methods is to be used is determined by the RM bits in FPSCR. FPSCR.
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6. Floating-Point Unit (FPU) 6.5 Floating-Point Exceptions 6.5.1 General FPU Disable Exceptions and Slot FPU Disable Exceptions FPU-related exceptions are occurred when an FPU instruction is executed with SR.FD set to 1. When the FPU instruction is in other than delayed slot, the general FPU disable exception is occurred. When the FPU instruction is in the delay slot, the slot FPU disable exception is occurred. 6.5.
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6. Floating-Point Unit (FPU) 6.5.3 FPU Exception Handling FPU exception handling is initiated in the following cases: • FPU error (E): FPSCR.DN = 0 and a denormalized number is input • Invalid operation (V): FPSCR.Enable.V = 1 and (instruction = FTRV or invalid operation) • Division by zero (Z): FPSCR.Enable.Z = 1 and division with a zero divisor or the input of FSRRA is zero • Overflow (O): FPSCR.Enable.O = 1 and possibility of operation result overflow • Underflow (U): FPSCR.Enable.
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6. Floating-Point Unit (FPU) 6.6 Graphics Support Functions This LSI supports two kinds of graphics functions: new instructions for geometric operations, and pair single-precision transfer instructions that enable high-speed data transfer. 6.6.1 Geometric Operation Instructions Geometric operation instructions perform approximate-value computations.
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6. Floating-Point Unit (FPU) (2) FTRV XMTRX, FVn (n: 0, 4, 8, 12) This instruction is basically used for the following purposes: • Matrix (4 × 4) ⋅ vector (4): This operation is generally used for viewpoint changes, angle changes, or movements called vector transformations (4-dimensional). Since affine transformation processing for angle + parallel movement basically requires a 4 × 4 matrix, this LSI supports 4-dimensional operations.
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6. Floating-Point Unit (FPU) This instruction changes the value of the SZ bit in FPSCR, enabling fast switching between use and non-use of pair single-precision data transfer. Rev.1.00 Jan.
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7. Memory Management Unit (MMU) Section 7 Memory Management Unit (MMU) This LSI supports an 8-bit address space identifier, a 32-bit virtual address space, and a 29-bit or 32-bit physical address space. Address translation from virtual addresses to physical addresses is enabled by the memory management unit (MMU) in this LSI. The MMU performs high-speed address translation by caching user-created address translation table information in an address translation buffer (translation lookaside buffer: TLB).
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7. Memory Management Unit (MMU) 7.1 Overview of MMU The MMU was conceived as a means of making efficient use of physical memory. As shown in (0) in figure 7.
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7. Memory Management Unit (MMU) There are two methods by which the MMU can perform mapping from virtual memory to physical memory: the paging method, using fixed-length address translation, and the segment method, using variable-length address translation. With the paging method, the unit of translation is a fixed-size address space called a page.
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7. Memory Management Unit (MMU) 7.1.1 (1) Address Spaces Virtual Address Space This LSI supports a 32-bit virtual address space, and can access a 4-Gbyte address space. The virtual address space is divided into a number of areas, as shown in figures 7.2 and 7.3. In privileged mode, the 4-Gbyte space from the P0 area to the P4 area can be accessed. In user mode, a 2-Gbyte space in the U0 area can be accessed.
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7.
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7. Memory Management Unit (MMU) (b) P1 Area The P1 area does not allow address translation using the TLB but can be accessed using the cache. Regardless of whether the MMU is enabled or disabled, clearing the upper 3 bits of an address to 0 gives the corresponding physical address. Whether or not the cache is used is determined by the CCR setting. When the cache is used, switching between the copy-back method and the write-through method for write accesses is specified by the CB bit in CCR.
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7. Memory Management Unit (MMU) The area from H'E000 0000 to H'E3FF FFFF comprises addresses for accessing the store queues (SQs). In user mode, the access right is specified by the SQMD bit in MMUCR. For details, see section 8.7, Store Queues. The area from H'E500 0000 to H'E5FF FFFF comprises addresses for accessing the on-chip memory. In user mode, the access right is specified by the RMD bit in RAMCR. For details, see section 9, On-Chip Memory.
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7. Memory Management Unit (MMU) (2) Physical Address Space This LSI supports a 29-bit physical address space. The physical address space is divided into eight areas as shown in figure 7.5. Area 7 is a reserved area. For details, see section 11, Local Bus State Controller (LBSC) section of the hardware manual of the product.
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7. Memory Management Unit (MMU) the return from the exception handling routine, the instruction which caused the TLB miss exception is re-executed. (4) Single Virtual Memory Mode and Multiple Virtual Memory Mode There are two virtual memory systems, single virtual memory and multiple virtual memory, either of which can be selected with the SV bit in MMUCR.
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7. Memory Management Unit (MMU) 7.2 Register Descriptions The following registers are related to MMU processing. Table 7.
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7. Memory Management Unit (MMU) Register Name Abbreviation Power-on Reset Instruction re-fetch inhibit control register IRMCR H'0000 0000 H'0000 0000 Retained 7.2.1 Manual Reset Sleep Standby Retained Page Table Entry High Register (PTEH) PTEH consists of the virtual page number (VPN) and address space identifier (ASID). When an MMU exception or address error exception occurs, the VPN of the virtual address at which the exception occurred is set in the VPN bit by hardware.
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7. Memory Management Unit (MMU) Bit Bit Name 31 to 10 VPN Initial Value R/W Description Undefined R/W Virtual Page Number 9, 8 ⎯ All 0 R Reserved For details on reading from or writing to these bits, see description in General Precautions on Handling of Product. 7 to 0 ASID Undefined R/W Address Space Identifier 7.2.
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7. Memory Management Unit (MMU) Initial Value Bit Bit Name R/W Description 8 V Undefined R/W Page Management Information 7 SZ1 Undefined R/W 6 PR1 Undefined R/W The meaning of each bit is same as that of corresponding bit in Common TLB (UTLB). 5 PR0 Undefined R/W 4 SZ0 Undefined R/W 3 C Undefined R/W 2 D Undefined R/W 1 SH Undefined R/W 0 WT Undefined R/W 7.2.3 Translation Table Base Register (TTB) For details, see section 7.3, TLB Functions (TLB Compatible Mode; MMUCR.
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7. Memory Management Unit (MMU) 7.2.4 TLB Exception Address Register (TEA) After an MMU exception or address error exception occurs, the virtual address at which the exception occurred is stored. The contents of this register can be changed by software. Bit: 31 30 TEA Initial value: R/W: R/W Bit: 15 7.2.
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7.
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7. Memory Management Unit (MMU) Bit Bit Name Initial Value R/W Description 25, 24 ⎯ All 0 R Reserved For details on reading from or writing to these bits, see description in General Precautions on Handling of Product. 23 to 18 URB 000000 R/W UTLB Replace Boundary These bits indicate the UTLB entry boundary at which replacement is to be performed. Valid only when URB ≠ 0.
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7. Memory Management Unit (MMU) Bit Bit Name Initial Value R/W Description 7 ME 0 R/W TLB Extended Mode Switching 0: TLB compatible mode 1: TLB extended mode For modifying the ME bit value, always set the TI bit to 1 to invalidate the contents of ITLB and UTLB. The selection of TLB operating mode made by the ME bit does not affect the functionality or operation of the PMB.
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7. Memory Management Unit (MMU) Bit Initial Bit Name Value R/W Description 31 to 14 ⎯ R Reserved All 0 For details on reading/writing these bits, see General Precautions on Handling of Product. 13 to 8 EPR Undefined R/W Page Control Information 7 to 4 ESZ Undefined R/W Each bit has the same function as the corresponding bit of the unified TLB (UTLB). For details, see section 7.4, TLB Functions (TLB Extended Mode; MMUCR.
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7. Memory Management Unit (MMU) Bit Bit Name Initial Value R/W Description 31 to 8 ⎯ All 0 R Reserved For details on reading from or writing to these bits, see description in General Precautions on Handling of Product. 7 to 0 UB H'00 R/W Buffered Write Control for Each Area (64 Mbytes) When writing is performed without using the cache or in the cache write-through mode, these bits specify whether the next bus access from the CPU waits for the end of writing for each area.
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7. Memory Management Unit (MMU) 7.2.8 Instruction Re-Fetch Inhibit Control Register (IRMCR) When the specific resource is changed, IRMCR controls whether the instruction fetch is performed again for the next instruction. The specific resource means the part of control registers, TLB, and cache. In the initial state, the instruction fetch is performed again for the next instruction after changing the resource.
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7. Memory Management Unit (MMU) Bit Bit Name Initial Value R/W Description 3 R1 0 R/W Re-Fetch Inhibit 1 after Register Change When a register allocated in addresses H'FF200000 to H'FF2FFFFF is changed, this bit controls whether refetch is performed for the next instruction.
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7. Memory Management Unit (MMU) 7.3 TLB Functions (TLB Compatible Mode; MMUCR.ME = 0) 7.3.1 Unified TLB (UTLB) Configuration The UTLB is used for the following two purposes: 1. To translate a virtual address to a physical address in a data access 2. As a table of address translation information to be recorded in the ITLB in the event of an ITLB miss The UTLB is so called because of its use for the above two purposes.
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7. Memory Management Unit (MMU) • SH: Share status bit When 0, pages are not shared by processes. When 1, pages are shared by processes. • SZ[1:0]: Page size bits Specify the page size. 00: 1-Kbyte page 01: 4-Kbyte page 10: 64-Kbyte page 11: 1-Mbyte page • V: Validity bit Indicates whether the entry is valid. 0: Invalid 1: Valid Cleared to 0 by a power-on reset. Not affected by a manual reset. • PPN: Physical page number Upper 22 bits of the physical address of the physical page number.
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7. Memory Management Unit (MMU) 1: Cacheable When the control register area is mapped, this bit must be cleared to 0. • D: Dirty bit Indicates whether a write has been performed to a page. 0: Write has not been performed 1: Write has been performed • WT: Write-through bit Specifies the cache write mode.
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7. Memory Management Unit (MMU) 7.3.2 Instruction TLB (ITLB) Configuration The ITLB is used to translate a virtual address to a physical address in an instruction access. Information in the address translation table located in the UTLB is cached into the ITLB. Figure 7.8 shows the ITLB configuration. The ITLB consists of four fully-associative type entries.
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7. Memory Management Unit (MMU) Data access to virtual address (VA) VA is in P4 area VA is in P2 area VA is in P1 area VA is in P0, U0, or P3 area MMUCR.AT = 1 CCR.OCE? 0 No 1 Yes CCR.OCE? 0 1 CCR.CB? 1 0 0 CCR.WT? 1 No No SH = 0 and (MMUCR.SV = 0 or SR.MD = 0) VPNs match and V = 1 Yes Yes No VPNs match, ASIDs match, and V=1 Data TLB miss exception Yes Only one entry matches No Yes Data TLB multiple hit exception SR.
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7. Memory Management Unit (MMU) Figure 7.10 shows a flowchart of a memory access using the ITLB. Instruction access to virtual address (VA) VA is in P4 area VA is in P2 area VA is in P0, U0, or P3 area VA is in P1 area No Yes CCR.ICE? 0 MMUCR.AT = 1 1 No No Hardware ITLB miss handling VPNs match and V = 1 Yes Yes No Yes VPNs match, ASIDs match, and V=1 Yes Search UTLB Record in ITLB SH = 0 and (MMUCR.SV = 0 or SR.
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7. Memory Management Unit (MMU) 7.4 TLB Functions (TLB Extended Mode; MMUCR.ME = 1) 7.4.1 Unified TLB (UTLB) Configuration Figure 7.11 shows the configuration of the UTLB in TLB extended mode. Figure 7.12 shows the relationship between the page size and address format.
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7. Memory Management Unit (MMU) 0001: 4-Kbyte page 0010: 8-Kbyte page 0100: 64-Kbyte page 0101: 256-Kbyte page 0111: 1-Mbyte page 1000: 4-Mbyte page 1100: 64-Mbyte page Note: When a value other than those listed above is recorded, operation is not guaranteed. • V: Validity bit Indicates whether the entry is valid. 0: Invalid 1: Valid Cleared to 0 by a power-on reset. Not affected by a manual reset. • PPN: Physical page number Upper 19 bits of the physical address. With a 1-Kbyte page, PPN[28:10] are valid.
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7. Memory Management Unit (MMU) EPR[1]: Writing in user mode EPR[0]: Execution in user mode (instruction fetch) • C: Cacheability bit Indicates whether a page is cacheable. 0: Not cacheable 1: Cacheable When the control register area is mapped, this bit must be cleared to 0. • D: Dirty bit Indicates whether a write has been performed to a page. 0: Write has not been performed. 1: Write has been performed. • WT: Write-through bit Specifies the cache write mode. 0: Copy-back mode 1: Write-through mode Rev.
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7.
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7. Memory Management Unit (MMU) 7.4.3 Address Translation Method Figure 7.14 is a flowchart of memory access using the UTLB in TLB extended mode. Rev.1.00 Jan.
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7. Memory Management Unit (MMU) Data access to virtual address (VA) VA is in P4 area VA is in P2 area VA is in P0, U0, or P3 area VA is in P1 area MMUCR.AT = 1 CCR.OCE? 0 No 1 Yes 0 CCR.OCE? 1 CCR.CB? 1 0 0 CCR.WT? 1 No No SH = 0 and (MMUCR.SV = 0 or SR.MD = 0) VPNs match and V = 1 Yes Yes VPNs match, ASIDs match, and V=1 No Data TLB miss exception Yes Only one entry matches No Yes Data TLB multiple hit exception SR.
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7. Memory Management Unit (MMU) Figure 7.15 is a flowchart of memory access using the ITLB in TLB extended mode. Instruction access to virtual address (VA) VA is in P4 area VA is in P2 area VA is in P0, U0, or P3 area VA is in P1 area MMUCR.AT = 1 No Yes CCR.ICE? 0 1 No No VPNs match and V = 1 Yes Yes Hardware ITLB miss handling Record in ITLB SH = 0 and (MMUCR.SV = 0 or SR.
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7. Memory Management Unit (MMU) 7.5 MMU Functions 7.5.1 MMU Hardware Management This LSI supports the following MMU functions. 1. The MMU decodes the virtual address to be accessed by software, and performs address translation by controlling the UTLB/ITLB in accordance with the MMUCR settings. 2. The MMU determines the cache access status on the basis of the page management information read during address translation (C and WT bits). 3.
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7. Memory Management Unit (MMU) 7.5.3 MMU Instruction (LDTLB) A TLB load instruction (LDTLB) is provided for recording UTLB entries. When an LDTLB instruction is issued, this LSI copies the contents of PTEH and PTEL (also the contents of PTEA in TLB extended mode) to the UTLB entry indicated by the URC bit in MMUCR. ITLB entries are not updated by the LDTLB instruction, and therefore address translation information purged from the UTLB entry may still remain in the ITLB entry.
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7. Memory Management Unit (MMU) The operation of the LDTLB instruction is shown in figures 7.16 and 7.17.
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7. Memory Management Unit (MMU) MMUCR − LRUI − URB URC SV ME − SQMD Entry specification PTEH PTEL − VPN TI − AT ASID PTEA − − PPN V − C D SH WT − EPR ESZ − Write Entry 0 ASID[7:0] VPN[31:10] V PPN[28:10] ESZ[3:0] SH C EPR[5:0] D WT Entry 1 ASID[7:0] VPN[31:10] V PPN[28:10] ESZ[3:0] SH C EPR[5:0] D WT Entry 2 ASID[7:0] VPN[31:10] V PPN[28:10] ESZ[3:0] SH C EPR[5:0] D WT Entry 63 ASID[7:0] VPN[31:10] V PPN[28:10] ESZ[3:0] SH C EPR[5:0] D WT Figure 7.
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7. Memory Management Unit (MMU) 7.5.5 Avoiding Synonym Problems When information on 1- or 4-Kbyte pages is written as TLB entries, a synonym problem may arise. The problem is that, when a number of virtual addresses are mapped onto a single physical address, the same physical address data is written to a number of cache entries, and it becomes impossible to guarantee data integrity. This problem does not occur with the instruction TLB and instruction cache because only data is read in these cases.
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7. Memory Management Unit (MMU) 7.6 MMU Exceptions There are seven MMU exceptions: instruction TLB multiple hit exception, instruction TLB miss exception, instruction TLB protection violation exception, data TLB multiple hit exception, data TLB miss exception, data TLB protection violation exception, and initial page write exception. Refer to figures 7.9, 7.10, 7.14, 7.15, and section 5, Exception Handling for the conditions under which each of these exceptions occurs. 7.6.
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7. Memory Management Unit (MMU) 7.6.2 Instruction TLB Miss Exception An instruction TLB miss exception occurs when address translation information for the virtual address to which an instruction access is made is not found in the UTLB entries by the hardware ITLB miss handling routine. The instruction TLB miss exception processing carried out by hardware and software is shown below. This is the same as the processing for a data TLB miss exception.
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7. Memory Management Unit (MMU) 3. In TLB compatible mode, execute the LDTLB instruction and write the contents of PTEH and PTEL to the TLB. In TLB extended mode, execute the LDTLB instruction and write the contents of PTEH, PTEL, PTEA to the UTLB. 4. Finally, execute the exception handling return instruction (RTE) to terminate the exception handling routine and return control to the normal flow. The RTE instruction should be issued at least one instruction after the LDTLB instruction.
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7. Memory Management Unit (MMU) (2) Software Processing (Instruction TLB Protection Violation Exception Handling Routine) Resolve the instruction TLB protection violation, execute the exception handling return instruction (RTE), terminate the exception handling routine, and return control to the normal flow. The RTE instruction should be issued at least one instruction after the LDTLB instruction. 7.6.
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7. Memory Management Unit (MMU) 3. Sets exception code H'040 in the case of a read, or H'060 in the case of a write in EXPEVT (OCBP, OCBWB: read; OCBI, MOVCA.L: write). 4. Sets the PC value indicating the address of the instruction at which the exception occurred in SPC. If the exception occurred at a delay slot, sets the PC value indicating the address of the delayed branch instruction in SPC. 5. Sets the SR contents at the time of the exception in SSR. The R15 contents at this time are saved in SGR. 6.
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7. Memory Management Unit (MMU) 7.6.6 Data TLB Protection Violation Exception A data TLB protection violation exception occurs when, even though a UTLB entry contains address translation information matching the virtual address to which a data access is made, the actual access type is not permitted by the access right specified by the PR or EPR bit. The data TLB protection violation exception processing carried out by hardware and software is shown below.
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7. Memory Management Unit (MMU) 7.6.7 Initial Page Write Exception An initial page write exception occurs when the D bit is 0 even though a UTLB entry contains address translation information matching the virtual address to which a data access (write) is made, and the access is permitted. The initial page write exception processing carried out by hardware and software is shown below.
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7. Memory Management Unit (MMU) 5. In TLB compatible mode, execute the LDTLB instruction and write the contents of PTEH and PTEL to the TLB. In TLB extended mode, execute the LDTLB instruction and write the contents of PTEH, PTEL, PTEA to the UTLB. 6. Finally, execute the exception handling return instruction (RTE), terminate the exception handling routine, and return control to the normal flow. The RTE instruction should be issued at least one instruction after the LDTLB instruction. Rev.1.00 Jan.
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7. Memory Management Unit (MMU) 7.7 Memory-Mapped TLB Configuration To enable the ITLB and UTLB to be managed by software, their contents are allowed to be read from and written to by a program in the P1/P2 area with a MOV instruction in privileged mode. Operation is not guaranteed if access is made from a program in another area.
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7. Memory Management Unit (MMU) 7.7.1 ITLB Address Array The ITLB address array is allocated to addresses H'F200 0000 to H'F2FF FFFF in the P4 area. An address array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing). Information for selecting the entry to be accessed is specified in the address field, and VPN, V, and ASID to be written to the address array are specified in the data field.
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7. Memory Management Unit (MMU) 7.7.2 ITLB Data Array (TLB Compatible Mode) The ITLB data array is allocated to addresses H'F300 0000 to H'F37F FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing). Information for selecting the entry to be accessed is specified in the address field, and PPN, V, SZ, PR, C, and SH to be written to the data array are specified in the data field.
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7. Memory Management Unit (MMU) 7.7.3 ITLB Data Array (TLB Extended Mode) In TLB extended mode the names of the data arrays have been changed from ITLB data array to ITLB data array 1, ITLB data array 2 is added, and the EPR and ESZ bits are accessible. In TLB extended mode, the PR and SZ bits of ITLB data array 1 are reserved and 0 should be specified as the write value for these bits.
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7. Memory Management Unit (MMU) (2) ITLB Data Array 2 The ITLB data array is allocated to addresses H'F380 0000 to H'F3FF FFFF in the P4 area. Access to data array 2 requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing). Information for selecting the entry to be accessed is specified in the address field, and EPR and ESZ to be written to data array 2 are specified in the data field.
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7. Memory Management Unit (MMU) 7.7.4 UTLB Address Array The UTLB address array is allocated to addresses H'F600 0000 to H'F60F FFFF in the P4 area. An address array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing). Information for selecting the entry to be accessed is specified in the address field, and VPN, D, V, and ASID to be written to the address array are specified in the data field.
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7. Memory Management Unit (MMU) 31 20 19 31 A * * * * * 0 0 E 10 9 8 7 Data field D V VPN VPN: V: E: D: *: 2 1 0 8 7 14 13 Address field 1 1 1 1 0 1 1 0 0 0 0 0 * * * * * * Virtual page number Validity bit Entry Dirty bit Don't care 0 ASID ASID: Address space identifier A: Association bit : Reserved bits (write value should be 0 and read value is undefined ) Figure 7.22 Memory-Mapped UTLB Address Array 7.7.
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7. Memory Management Unit (MMU) 31 14 13 2019 8 7 Address field 1 1 1 1 0 1 1 1 0 0 0 0 * * * * * * 31 E 29 28 Data field 10 9 8 7 6 5 4 3 2 1 0 V PPN PPN: V: E: SZ: D: *: 2 1 0 * * * * * * 0 0 Physical page number Validity bit Entry Page size bits Dirty bit Don't care PR: C: SH: WT: : PR C D SH Protection key data SZ1 WT Cacheability bit Share status bit Write-through bit Reserved bits (write value should be 0 and read value is undefined ) Figure 7.
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7. Memory Management Unit (MMU) (2) UTLB Data Array 2 The UTLB data array is allocated to addresses H'F780 0000 to H'F78F FFFF in the P4 area. Access to data array 2 requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing). Information for selecting the entry to be accessed is specified in the address field, and EPR and ESZ to be written to data array 2 are specified in the data field.
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7. Memory Management Unit (MMU) 7.8 32-Bit Address Extended Mode Setting the SE bit in PASCR to 1 changes mode from 29-bit address mode which handles the 29bit physical address space to 32-bit address extended mode which handles the 32-bit physical address space. Virtual address space 29-bits address space U0/P0 (2 Gbytes) 0.5 Gbyte Virtual address space 32-bit address space U0/P0 (2 Gbytes) 4 Gbytes P1/P2 (1 Gbyte) P1 (0.5 Gbyte) P2 (0.5 Gbyte) P3 (0.5 Gbyte) P3 (0.5 Gbyte) P4 (0.
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7. Memory Management Unit (MMU) 7.8.2 Transition to 32-Bit Address Extended Mode This LSI enters 29-bit address mode after a power-on reset. Transition is made to 32-bit address extended mode by setting the SE bit in PASCR to 1. In 32-bit address extended mode, the MMU operates as follows. 1. When the AT bit in MMUCR is 0, virtual addresses in the U0, P0, or P3 area become 32-bit physical addresses. Addresses in the P1 or P2 area are translated according to the PMB mapping information.
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7. Memory Management Unit (MMU) Legend: • VPN: Virtual page number For 16-Mbyte page: Upper 8 bits of virtual address For 64-Mbyte page: Upper 6 bits of virtual address For 128-Mbyte page: Upper 5 bits of virtual address For 512-Mbyte page: Upper 3 bits of virtual address Note: B'10 should be set to the upper 2 bits of VPN in order to indicate P1 or P2 area. • SZ: Page size bits Specify the page size.
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7. Memory Management Unit (MMU) • WT: Write-through bit Specifies the cache write mode. 0: Copy-back mode 1: Write-through mode • UB: Buffered write bit Specifies whether a buffered write is performed. 0: Buffered write (Data access of subsequent processing proceeds without waiting for the write to complete.) 1: Unbuffered write (Data access of subsequent processing is stalled until the write has completed.) 7.8.4 PMB Function This LSI supports the following PMB functions. 1.
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7. Memory Management Unit (MMU) 7.8.5 Memory-Mapped PMB Configuration To enable the PMB to be managed by software, its contents are allowed to be read from and written to by a P1 or P2 area program with a MOV instruction in privileged mode. The PMB address array is allocated to addresses H'F610 0000 to H'F61F FFFF in the P4 area and the PMB data array to addresses H'F710 0000 to H'F71F FFFF in the P4 area.
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7. Memory Management Unit (MMU) 31 20 19 E 24 23 31 Data field 8 7 12 11 Address field 1 1 1 1 0 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 8 0 V VPN VPN: Physical page number V: Validity bit E: Entry : Reserved bits (write value should be 0 and read value is undefined ) Figure 7.
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7. Memory Management Unit (MMU) Bit Bit Name Initial Value R/W Description 30 to 8 ⎯ All 0 R Reserved For details on reading from or writing to these bits, see description in General Precautions on Handling of Product. 7 to 0 UB All 0 R/W Buffered Write Control for Each Area (64 Mbytes) When writing is performed without using the cache or in the cache write-through mode, these bits specify whether the CPU waits for the end of writing for each area.
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7. Memory Management Unit (MMU) (5) CCR.CB The CB bit in CCR is invalid. Whether a cacheable write for the P1 area is performed in copyback mode or write-though mode is determined by the WT bit in the PMB. (6) IRMCR.MT The MT bit in IRMCR is valid for a memory-mapped PMB write. (7) QACR0, QACR1 AREA0[4:2]/AREA1[4:2] fields of QACR0/QACR1 are extended to AREA0[7:2]/AREA1[7:2] corresponding to physical address [31:26].
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7. Memory Management Unit (MMU) 7.9 32-Bit Boot Function The address mode of this LSI after a power-on reset or manual reset can be switched between 29bit address mode and 32-bit address extended mode by specifying external pins. The following changes apply when this LSI is booted up in 32-bit address extended mode. 7.9.
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7. Memory Management Unit (MMU) C. If the MT bit in IRMCR is set to 0 (initial value) before accessing the memory-mapped PMB, no specific sequence is required. However, correct operation with method C may no longer be guaranteed in future SuperHfamily products. Selection of step A or B is recommended to ensure compatibility with future SuperH-family products. (2) When the Program Modifying the PMB is in Areas Other than the P1 or P2 Area 1.
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7. Memory Management Unit (MMU) 7.10 Usage Notes 7.10.1 Note on Using LDTLB Instruction When using an LDTLB instruction instead of software to a value to the MMUCR. URC, execute 1 or 2 below. 1. In 29-bit address mode, follow A. and B. below. In 32-bit address mode, follow A. through D. below. A.
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7. Memory Management Unit (MMU) Notes: 1. An exception handling routine is an entire set of instructions that are executed from the address (VBR + offset) upon occurrence of an exception to the RTE for returning to the original program or to the RTE delay slot. 2. MMU-related exceptions are: instruction TLB miss exception, instruction TLB miss protection violation exception, data TLB miss exception, data TLB protection violation exception, and initial page write exception. 3.
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8. Caches Section 8 Caches This LSI has an on-chip 32-Kbyte instruction cache (IC) for instructions and an on-chip 32-Kbyte operand cache (OC) for data. 8.1 Features The features of the cache are given in table 8.1. This LSI supports two 32-byte store queues (SQs) to perform high-speed writes to external memory. The features of the store queues are given in table 8.2. Table 8.
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8. Caches This LSI has an IC way prediction scheme to reduce power consumption. In addition, memorymapped associative writing, which is detectable as an exception, can be enabled by using the nonsupport detection exception register (EXPMASK). For details, see section 5, Exception Handling.
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8. Caches Virtual address 31 13 12 10 5 4 [12:5] 2 0 Longword (LW) selection Entry selection 22 Address array (way 0 to way 3) 8 0 3 Data array (way 0 to way3) Tag V LW0 LW1 LW2 LW3 LW4 LW5 LW6 LW7 19 bits 1 bit 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits LRU MMU 19 255 6 bits Comparison Read data (Way 0 to way 3) Hit signal Figure 8.
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8. Caches • Data array The data field holds 32 bytes (256 bits) of data per cache line. The data array is not initialized by a power-on or manual reset. • LRU In a 4-way set-associative method, up to 4 items of data can be registered in the cache at each entry address. When an entry is registered, the LRU bit indicates which of the 4 ways it is to be registered in. The LRU mechanism uses 6 bits of each entry, and its usage is controlled by hardware.
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8. Caches 8.2 Register Descriptions The following registers are related to cache. Table 8.3 Register Configuration Register Name Abbreviation R/W P4 Address* Area 7 Address* Size Cache control register CCR R/W H'FF00 001C H'1F00 001C 32 Queue address control register 0 QACR0 R/W H'FF00 0038 H'1F00 0038 32 Queue address control register 1 QACR1 R/W H'FF00 003C H'1F00 003C 32 On-chip memory control register RAMCR R/W H'FF00 0074 H'1F00 0074 32 Note: * Table 8.
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8. Caches 8.2.1 Cache Control Register (CCR) CCR controls the cache operating mode, the cache write mode, and invalidation of all cache entries. CCR modifications must only be made by a program in the non-cacheable P2 area or IL memory. After CCR has been updated, execute one of the following three methods before an access (including an instruction fetch) to the cacheable area is performed. 1. Execute a branch using the RTE instruction. In this case, the branch destination may be the cacheable area. 2.
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8. Caches Bit Bit Name Initial Value R/W Description 10, 9 ⎯ All 0 R Reserved For details on reading from or writing to these bits, see description in General Precautions on Handling of Product. 8 ICE 0 R/W IC Enable Bit Selects whether the IC is used. Note however when address translation is performed, the IC cannot be used unless the C bit in the page management information is also 1.
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8. Caches 8.2.2 Queue Address Control Register 0 (QACR0) QACR0 specifies the area onto which store queue 0 (SQ0) is mapped when the MMU is disabled.
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8. Caches 8.2.3 Queue Address Control Register 1 (QACR1) QACR1 specifies the area onto which store queue 1 (SQ1) is mapped when the MMU is disabled.
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8. Caches 8.2.4 On-Chip Memory Control Register (RAMCR) RAMCR controls the number of ways in the IC and OC and prediction of the IC way. RAMCR modifications must only be made by a program in the non-cacheable P2 area. After RAMCR has been updated, execute one of the following three methods before an access (including an instruction fetch) to the cacheable area, the IL memory area, the OL memory area, or the U memory area is performed. 1. Execute a branch using the RTE instruction.
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8. Caches Bit Bit Name Initial Value R/W Description 8 RP 0 R/W On-Chip Memory Protection Enable Bit For details, see section 9.4, On-Chip Memory Protective Functions. 7 IC2W 0 R/W IC Two-Way Mode bit 0: IC is a four-way operation 1: IC is a two-way operation For details, see section 8.4.3, IC Two-Way Mode. 6 OC2W 0 R/W OC Two-Way Mode bit 0: OC is a four-way operation 1: OC is a two-way operation For details, see section 8.3.6, OC Two-Way Mode.
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8. Caches 8.3 Operand Cache Operation 8.3.1 Read Operation When the Operand Cache (OC) is enabled (OCE = 1 in CCR) and data is read from a cacheable area, the cache operates as follows: 1. The tag, V bit, U bit, and LRU bits on each way are read from the cache line indexed by virtual address bits [12:5]. 2.
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8. Caches write-back buffer is then written back to external memory. 8.3.2 Prefetch Operation When the Operand Cache (OC) is enabled (OCE = 1 in CCR) and data is prefetched from a cacheable area, the cache operates as follows: 1. The tag, V bit, U bit, and LRU bits on each way are read from the cache line indexed by virtual address bits [12:5]. 2.
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8. Caches 8.3.3 Write Operation When the Operand Cache (OC) is enabled (OCE = 1 in CCR) and data is written to a cacheable area, the cache operates as follows: 1. The tag, V bit, U bit, and LRU bits on each way are read from the cache line indexed by virtual address bits [12:5]. 2. The tag, read from each way, is compared with bits [28:10] of the physical address resulting from virtual address translation by the MMU: ⎯ If there is a way whose tag matches and its V bit is 1, see No.
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8. Caches 6. Cache miss (copy-back, with write-back) The tag and data field of the cache line on the way which is selected to replace are saved in the write-back buffer. Then a data write in accordance with the access size is performed for the data field on the hit way which is indexed by virtual address bits [4:0].
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8. Caches 8.3.6 OC Two-Way Mode When the OC2W bit in RAMCR is set to 1, OC two-way mode which only uses way 0 and way 1 in the OC is entered. Thus, power consumption can be reduced. In this mode, only way 0 and way 1 are used even if a memory-mapped OC access is made. The OC2W bit should be modified by a program in the P2 area.
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8. Caches 8.4 Instruction Cache Operation 8.4.1 Read Operation When the IC is enabled (ICE = 1 in CCR) and instruction fetches are performed from a cacheable area, the instruction cache operates as follows: 1. The tag, V bit, U bit and LRU bits on each way are read from the cache line indexed by virtual address bits [12:5]. 2.
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8. Caches 3. Cache hit The LRU bits is updated to indicate the way is the latest one. 4. Cache miss Data is read into the cache line on a way which selected using the LRU bits to replace from the physical address space corresponding to the virtual address. Data reading is performed, using the wraparound method, in order from the quad-word data (8 bytes) including the cachemissed data. In the prefetch operation, the CPU doesn't wait the data arrived.
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8. Caches 8.5 Cache Operation Instruction 8.5.1 Coherency between Cache and External Memory (1) Cache Operation Instruction Coherency between cache and external memory should be assured by software. In this LSI, the following six instructions are supported for cache operations. Details of these instructions are given in section 11, Instruction Descriptions of the SH-4A Extended Functions Software Manual.
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8. Caches • FLUSH transaction When the operand cache is enabled, the FLUSH transaction checks the operand cache and if the hit line is dirty, then the data is written back to the external memory. If the transaction is not hit to the cache or the hit entry is not dirty, it is no-operation.
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8. Caches the dirty bit to 0. This operation is only executable in privileged mode, and an address error exception occurs in user mode. TLB-related exceptions do not occur. Do not execute this instruction to invalidate the memory-mapped array areas and control register areas for which Rn[31:24] is not H'F4, and their reserved areas (H'F0 to H'F3, H'F5 to H'FF). 8.5.2 Prefetch Operation This LSI supports a prefetch instruction to reduce the cache fill penalty incurred as the result of a cache miss.
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8. Caches 8.6 Memory-Mapped Cache Configuration The IC and OC can be managed by software. The contents of IC data array can be read from or written to by a program in the P2 area by means of a MOV instruction in privileged mode. The contents of IC address array can also be read from or written to in privileged mode by a program in the P2 area or the IL memory area by means of a MOV instruction. Operation is not guaranteed if access is made from a program in another area.
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8. Caches In the data field, the tag is indicated by bits [31:10], and the V bit by bit [0]. As the IC address array tag is 19 bits in length, data field bits [31:29] are not used in the case of a write in which association is not performed. Data field bits [31:29] are used for the virtual address specification only in the case of a write in which association is performed. The following three kinds of operation can be used on the IC address array: 1.
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8. Caches 8.6.2 IC Data Array The IC data array is allocated to addresses H'F100 0000 to H'F1FF FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification. The way and entry to be accessed are specified in the address field, and the longword data to be written is specified in the data field.
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8. Caches 32-bit data field specification. The way and entry to be accessed are specified in the address field, and the write tag, U bit, and V bit are specified in the data field. In the address field, bits [31:24] have the value H'F4 indicating the OC address array, and the way is specified by bits [14:13] and the entry by bits [12:5]. The association bit (A bit) [3] in the address field specifies whether or not association is performed when writing to the OC address array.
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8. Caches 24 23 31 15 141312 Address field 1 1 1 1 0 1 0 0 * * * * * * * * * Way 31 Data field 5 4 3 2 1 0 Entry 0 A 0 0 0 10 9 Tag 2 1 0 U V V : Validity bit U : Dirty bit A : Association bit : Reserved bits (write value should be 0 and read value is undefined ) * : Don't care Figure 8.7 Memory-Mapped OC Address Array (Cache size = 32 Kbytes) 8.6.4 OC Data Array The OC data array is allocated to addresses H'F500 0000 to H'F5FF FFFF in the P4 area.
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8. Caches 31 24 23 15 141312 Address field 1 1 1 1 0 1 0 1 * * * * * * * * * 31 Data field 5 4 3 2 1 0 Entry Way L 0 0 0 Longword data L : Longword specification bits * : Don't care Figure 8.8 Memory-Mapped OC Data Array (Cache size = 32 Kbytes) 8.6.5 Memory-Mapped Cache Associative Write Operation Associative writing to the IC and OC address arrays may not be supported in future SuperHfamily products. The use of instructions ICBI, OCBI, OCBP, and OCBWB is recommended.
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8. Caches 8.7 Store Queues This LSI supports two 32-byte store queues (SQs) to perform high-speed writes to external memory. 8.7.1 SQ Configuration There are two 32-byte store queues, SQ0 and SQ1, as shown in figure 8.9. These two store queues can be set independently. SQ0 SQ0[0] SQ0[1] SQ0[2] SQ0[3] SQ0[4] SQ0[5] SQ0[6] SQ0[7] SQ1 SQ1[0] SQ1[1] SQ1[2] SQ1[3] SQ1[4] SQ1[5] SQ1[6] SQ1[7] 4 byte 4 byte 4 byte 4 byte 4 byte 4 byte 4 byte 4 byte Figure 8.
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8. Caches 8.7.3 Transfer to External Memory Transfer from the SQs to external memory can be performed with a prefetch instruction (PREF). Issuing a PREF instruction for addresses H'E000 0000 to H'E3FF FFFC in the P4 area starts a transfer from the SQs to external memory. The transfer length is fixed at 32 bytes, and the start address is always at a 32-byte boundary. While the contents of one SQ are being transferred to external memory, the other SQ can be written to without a penalty cycle.
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8. Caches Physical address bits [4:0] are always fixed at 0 since burst transfer starts at a 32-byte boundary. 8.7.4 Determination of SQ Access Exception Determination of an exception in a write to an SQ or transfer to external memory (PREF instruction) is performed as follows according to whether the MMU is enabled or disabled. If an exception occurs during a write to an SQ, the SQ contents before the write are retained.
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8. Caches 8.8 Notes on Using 32-Bit Address Extended Mode In 32-bit address extended mode, the items described in this section are extended as follows. 1. The tag bits [28:10] (19 bits) in the IC and OC are extended to bits [31:10] (22 bits). 2. An instruction which operates the IC (a memory-mapped IC access and writing to the ICI bit in CCR) should be located in the P1 or P2 area. The cacheable bit (C bit) in the corresponding entry in the PMB should be 0. 3.
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8. Caches Rev.1.00 Jan.
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9. On-Chip Memory Section 9 On-Chip Memory This LSI includes three types of memory modules for storage of instructions and data: OL memory, IL memory, and U memory. The OL memory is suitable for data storage while the IL memory is suitable for instruction storage. The U memory can store instructions and/or data. 9.1 (1) Features OL Memory • Capacity The OL memory in this LSI is 16 Kbytes. • Page The OL memory is divided into four pages (pages 0A, 0B, 1A and 1B).
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9. On-Chip Memory (2) IL Memory • Capacity The IL memory in this LSI is 8 Kbytes. • Page The IL memory is divided into two pages (pages 0 and 1). • Memory map The IL memory is allocated to the addresses shown in table 9.2 in both the virtual address space and the physical address space. Table 9.
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9. On-Chip Memory The CPU can access the P4 area in the virtual address space (when SR.MD = 1) or on-chip memory area (when SR.MD = 0 and RAMCR.RMD = 1). Access operations involving these addresses are always non-cacheable. Table 9.
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9. On-Chip Memory 9.2 Register Descriptions The following registers are related to the on-chip memory. Table 9.
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9. On-Chip Memory 9.2.1 On-Chip Memory Control Register (RAMCR) RAMCR controls the protective functions in the on-chip memory. When updating RAMCR, please follow limitation described at section 8.2.4, On-Chip Memory Control Register (RAMCR).
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9. On-Chip Memory Bit Bit Name Initial Value R/W Description 6 OC2W 0 R/W OC Two-Way Mode For further details, refer to section 8.3.6, OC Two-Way Mode. 5 ICWPD 0 R/W IC Way Prediction Disable For further details, refer to section 8.4.4, Instruction Cache Way Prediction Operation. 4 to 0 — All 0 R Reserved For read/write in these bits, refer to General Precautions on Handling of Product. 9.2.2 OL memory Transfer Source Address Register 0 (LSA0) When MMUCR.AT = 0 or RAMCR.
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9. On-Chip Memory Bit Bit Name Initial Value 5 to 0 L0SSZ Undefined R/W R/W Description OL memory Page 0 Block Transfer Source Address Select When MMUCR.AT = 0 or RAMCR.RP = 0, these bits select whether the operand addresses or L0SADR values are used as bits 15 to 10 of the transfer source physical address for block transfer to page 0A or 0B in the OL memory. L0SSZ[5:0] correspond to the transfer source physical addresses [15:10].
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9. On-Chip Memory 9.2.3 OL memory Transfer Source Address Register 1 (LSA1) When MMUCR.AT = 0 or RAMCR.RP = 0, the LSA1 specifies the transfer source physical address for block transfer to page 1A or 1B in the OL memory.
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9. On-Chip Memory Bit Bit Name Initial Value 5 to 0 L1SSZ Undefined R/W R/W Description OL memory Page 1 Block Transfer Source Address Select When MMUCR.AT = 0 or RAMCR.RP = 0, these bits select whether the operand addresses or L1SADR values are used as bits 15 to 10 of the transfer source physical address for block transfer to page 1A or 1B in the OL memory. L1SSZ bits [5:0] correspond to the transfer source physical addresses [15:10].
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9. On-Chip Memory 9.2.4 OL memory Transfer Destination Address Register 0 (LDA0) When MMUCR.AT = 0 or RAMCR.RP = 0, LDA0 specifies the transfer destination physical address for block transfer to page 0A or 0B of the OL memory.
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9. On-Chip Memory Bit Bit Name Initial Value 5 to 0 L0DSZ Undefined R/W R/W Description OL memory Page 0 Block Transfer Destination Address Select When MMUCR.AT = 0 or RAMCR.RP = 0, these bits select whether the operand addresses or L0DADR values are used as bits 15 to 10 of the transfer destination physical address for block transfer to page 0A or 0B in the OL memory. L0DSZ bits [5:0] correspond to the transfer destination physical address bits [15:10].
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9. On-Chip Memory 9.2.5 OL memory Transfer Destination Address Register 1 (LDA1) When MMUCR.AT = 0 or RAMCR.RP = 0, LDA1 specifies the transfer destination physical address for block transfer to page 1A or 1B in the OL memory.
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9. On-Chip Memory Bit Bit Name Initial Value 5 to 0 L1DSZ Undefined R/W R/W Description OL memory Page 1 Block Transfer Destination Address Select When MMUCR.AT = 0 or RAMCR.RP = 0, these bits select whether the operand addresses or L1DADR values are used as bits 15 to 10 of the transfer destination physical address for block transfer to page 1A or 1B in the OL memory. L1DSZ bits [5:0] correspond to the transfer destination physical addresses [15:10].
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9. On-Chip Memory 9.3 Operation 9.3.1 Instruction Fetch Access from the CPU (1) OL Memory Instruction fetch access from the CPU is performed via the cache/RAM internal bus. This access takes more than one cycle. (2) IL Memory Instruction fetch access from the CPU is performed directly via the instruction bus for a given virtual address. In the case of successive accesses to the same page of IL memory and as long as no page conflict occurs, the access takes one cycle.
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9. On-Chip Memory (3) U Memory Operand access from the CPU and read access from the FPU are performed via the read buffer. The read buffer is configured with two sets of one-line 32-byte buffers, and holds up to two lines which have been accessed through operand access by the CPU and accessed through read access by the FPU. The U memory can be accessed in one cycle when the read buffer is hit.
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9. On-Chip Memory (1) When MMU is Enabled (MMUCR.AT = 1) and RAMCR.RP = 1 An address of the OL memory area is specified to the UTLB VPN field, and to the physical address of the transfer source (in the case of the PREF instruction) or the transfer destination (in the case of the OCBWB instruction) to the PPN field. The ASID, V, SZ, SH, PR, and D bits have the same meaning as normal address conversion; however, the C and WT bits have no meaning in this page.
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9. On-Chip Memory When the PREF instruction is issued to the OL memory area, the physical address bits [28:10] are generated in accordance with the LSA0 or LSA1 specification. The physical address bits [9:5] are generated from the virtual address. The physical address bits [4:0] are fixed to 0. Block transfer is performed from the external memory specified by these physical addresses to the OL memory.
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9. On-Chip Memory 9.4 On-Chip Memory Protective Functions This LSI implements the following protective functions to the on-chip memory by using the onchip memory access mode bit (RMD) and the on-chip memory protection enable bit (RP) in the on-chip memory control register (RAMCR). • Protective functions for access from the CPU and FPU When RAMCR.RMD = 0, and the on-chip memory is accessed in user mode, it is determined to be an address error exception. When MMUCR.AT = 1 and RAMCR.
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9. On-Chip Memory 9.5 Usage Notes 9.5.1 Page Conflict In the event of simultaneous access to the same page from different buses, page conflict occurs. Although each access is completed correctly, this kind of conflict tends to lower OL memory accessibility. Therefore it is advisable to provide all possible preventative software measures. For example, conflicts will not occur if each bus accesses different pages. 9.5.
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9. On-Chip Memory (2) IL Memory In order to allocate instructions in the IL memory, write an instruction to the IL memory, execute the following sequence, then branch to the rewritten instruction. • SYNCO • ICBI @Rn In this case, the target for the ICBI instruction can be any address (IL memory address may be possible) within the range where no address error exception occurs, and cache hit/miss is possible.
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10. Interrupt Controller (INTC) Section 10 Interrupt Controller (INTC) The interrupt controller (INTC) determines the priority of interrupt sources and controls the flow of interrupt requests to the CPU (SH-4A). The INTC has registers for setting the priority of each of the interrupts and processing of interrupt requests follows the priority order set in these registers by the user. 10.
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10. Interrupt Controller (INTC) Figure 10.1 shows a block diagram of the INTC. IRQOUT NMI IRQ 8 CPU IRL IRQ/IRL7 to IRQ/IRL0 IRQ/IRL7 to IRQ/IRL4 and GPIO port L4 to L1 are multiplexed Priority determination for external interrupts (levels 1 to 15) Comparator Input control Comparator NMI USERIMASK.UIMASK Interrupt acceptance SR.
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10. Interrupt Controller (INTC) The details of the input control circuit of figure 10.1 are shown in figure 10.2. Input control NMI detector*4 NMI IRQ/IRL7 to IRQ/IRL0 IRL/IRQ pin mode controller*1 IRL mask controller Noise canceller Noise canceller for level detection IRL detector*2 IRQ detector*3 NMI interrupt request INTC IRL IRQ Priority determination for external interrupts ICR0 INTREQ ICR1 INTMSK2 INTMSK1 INTMSK0 Notes: 1. 2. 3. 4. The internal signal for IRQ is fixed when ICR0.
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10. Interrupt Controller (INTC) 10.1.1 Interrupt Method The basic flow of exception handling for interrupts is as follows. In interrupt exception handling, the contents of the program counter (PC), status register (SR), and general register 15 (R15) are saved in the saved program counter (SPC), saved status register (SSR), and saved general register15 (SGR), and the CPU starts execution of the interrupt exception handling routine at the corresponding vector address.
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10. Interrupt Controller (INTC) 10.1.2 Interrupt Sources Table 10.1 shows an example of the interrupt types. The INTC supports both external interrupts and on-chip peripheral module interrupts. External interrupts refer to the interrupts input through the external NMI, IRL, and IRQ pins. The IRQ and IRL interrupts are assigned to the same pins in the SH7785. The pin functions are selected to suit the system configuration.
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10. Interrupt Controller (INTC) Number of Sources (Max.) Priority Source External interrupts IRL IRQ interrupt 2 8 INTEVT Remarks Inverse of values on the input pins (because the signals are active low) H'320 IRL[3:0] pin = HLLH (H'9) H'C20 IRL[7:4] pin = HLLH (H'9) H'340 IRL[3:0] pin = HLHL (H'A) Input level H: high level L: low level (see table 10.
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10. Interrupt Controller (INTC) Number of Sources (Max.
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10. Interrupt Controller (INTC) Source SIOF On-chip module MMCIF interrupts* Number of Sources (Max.
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10. Interrupt Controller (INTC) BRI0, BRI1, BRI2, BRI3, BRI4, BRI5: SCIF channels 0 to 5 break interrupt TXI0, TXI1, TXI2, TXI3, TXI4, TXI5: SCIF channels 0 to 5 transmission data empty interrupt FLSTE: FLCTL error interrupt FLTEND: FLCTL error interrupt FLTRQ0: FLCTL data FIFO transfer request interrupt FLTRQ1: FLCTL control code FIFO transfer request interrupt Note: * Abbreviations used in the sources of the on-chip peripheral module interrupts. Rev.1.00 Jan.
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10. Interrupt Controller (INTC) 10.2 Input/Output Pins Table 10.2 shows the pin configuration. Table 10.2 INTC Pin Configuration Pin Name Function I/O NMI Nonmaskable Input interrupt input pin Description Nonmaskable interrupt request signal input Interrupt request signal input of IRQ7 to IRQ0 or IRL[7:4] and IRL[3:0] IRQ/IRL7 to External IRQ/IRL0 interrupt input pins Input IRQOUT Output Informs an external device of the generation of an interrupt request.
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10. Interrupt Controller (INTC) 10.3 Register Descriptions Table 10.3 shows the INTC register configuration. Table 10.4 shows the register states in each operating mode. Table 10.3 INTC Register Configuration Name Abbreviation R/W P4 Address Area 7 Address Access Sync.
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10. Interrupt Controller (INTC) Name Abbreviation R/W P4 Address Area 7 Address Access Sync.
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10. Interrupt Controller (INTC) Table 10.
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10.
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10. Interrupt Controller (INTC) 10.3.1 (1) External Interrupt Request Registers Interrupt Control Register 0 (ICR0) ICR0 is a 32-bit readable and partially writable register that sets the input signal detection mode for the external interrupt input pins and NMI pin, and indicates the level being input on the NMI pin.
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10. Interrupt Controller (INTC) Bit Name Initial Value R/W Description 25 NMIB 0 R/W NMI Block Mode Selects whether an NMI interrupt is held until the BL bit in SR is cleared to 0 or detected immediately when the BL bit in SR of the CPU is set to 1.
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10. Interrupt Controller (INTC) Initial Value Bit Name 21 LVLMODE 0 R/W Description R/W Level-sense IRQ/IRL with holding function Selects whether or not to use the holding function for level-sense IRQ and IRL interrupts.
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10. Interrupt Controller (INTC) (2) Interrupt Control Register 1 (ICR1) ICR1 is a 32-bit readable/writable register that specifies the individual input signal detection modes for the respective external interrupt input pins IRQ/IRL7 to IRQ/IRL0. These settings are only valid when IRLM0 or IRLM1 of ICR0 is set to 1 so that IRQ/IRL3 to IRQ/IRL0 or IRQ/IRL7 to IRQ/IRL4 pins are used as individual interrupts (IRQ7 to IRQ0 interrupts) inputs.
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10. Interrupt Controller (INTC) IRQ and IRL Interrupt Requests). 2. When the IRQnS setting is changed from edge sense (IRQnS is 00 or 01) to level sense (IRQnS is 10 or 11), the IRQ interrupt source that has been edge sensed is cleared. When the IRQnS setting is changed from level sense (IRQnS is 10 or 11) to edge sense (IRQnS is 00 or 01), the IRQ interrupt source that has been sensed or held is cleared.
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10. Interrupt Controller (INTC) (3) Interrupt Priority Register (INTPRI) INTPRI is a 32-bit readable/writable register used to set the priorities of IRQ[7:0] (as levels from 15 to 0). These settings are only valid for IRQ/IRL7 to IRQ/IRL4 or IRQ/IRL3 to IRQ/IRL0 when set up as individual IRQ interrupts (IRQ7 to IRQ0 interrupts) by setting the IRLM0 or IRLM1 bit in ICR0 to 1.
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10. Interrupt Controller (INTC) (4) Interrupt Source Register (INTREQ) INTREQ is a 32-bit readable and conditionally writable register that indicates which of the IRQ [n] (n = 0 to 7) interrupts is currently asserting a request for the INTC. Even if an interrupt is masked by the setting in INTPRI or INTMSK0, operation of the corresponding INTREQ bit is not affected.
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10. Interrupt Controller (INTC) (5) Interrupt Mask Register 0 (INTMSK0) INTMSK0 is a 32-bit readable and conditionally writable register that sets masking for each of the interrupt requests IRQn (n = 0 to 7). To clear the mask setting for an interrupt, write 1 to the corresponding bit in INTMSKCLR0. Writing 0 to the bits in INTMSK0 has no effect.
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10. Interrupt Controller (INTC) Bit Name Initial Value R/W Description 26 IM05 1 R/W Sets masking of individual pin interrupt source on IRQ5. [When read] 0: The interrupts are accepted. 25 IM06 1 R/W Sets masking of individual pin interrupt source on IRQ6. 1: The interrupts are masked. 24 IM07 1 R/W Sets masking of individual pin interrupt source on IRQ7. 0: No effect 23 to 0 All 0 R [When written] 1: Masks the interrupt Reserved These bits are always read as 0.
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10. Interrupt Controller (INTC) (6) Interrupt Mask Register 1 (INTMSK1) INTMSK1 is a 32-bit readable and conditionally writable register that sets masking for IRL interrupt requests. To clear the mask setting for the interrupt, write 1 to the corresponding bit in INTMSKCLR1. Writing 0 to the bits in INTMSK1 has no effect.
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10. Interrupt Controller (INTC) (7) Interrupt Mask Register 2 (INTMSK2) INTMSK2 is a 32-bit readable and conditionally writable register that sets masking for IRL interrupt requests for input level pattern on the IRL pins. To clear the mask setting for the interrupt, write 1 to the corresponding bit in INTMSKCLR2. Writing 0 to the bits in INTMSK2 has no effect.
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10. Interrupt Controller (INTC) Bit Name Initial Value R/W Description 26 IM010 0 R/W 25 IM009 0 R/W 24 IM008 0 R/W Masks the interrupt source [When read] of IRL3 to IRL0 = LHLH 0: The interrupt is (H'5). accepted. Masks the interrupt source 1: The interrupt is of IRL3 to IRL0 = LHHL masked. (H'6). [When written] Masks the interrupt source 0: No effect of IRL3 to IRL0 = LHHH 1: Masks the interrupt (H'7). 23 IM007 0 R/W Masks the interrupt source of IRL3 to IRL0 = HLLL (H'8).
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10. Interrupt Controller (INTC) Bit Name Initial Value R/W Description 15 IM115 0 R/W 14 IM114 0 R/W 13 IM113 0 R/W Masks the interrupt source [When read] of IRL7 to IRL4 = LLLL 0: The interrupt is (H'0). accepted. Masks the interrupt source 1: The interrupt is of IRL7 to IRL4 = LLLH masked. (H'1). [When written] Masks the interrupt source 0: No effect of IRL7 to IRL4 = LLHL 1: Masks the interrupt (H'2). 12 IM112 0 R/W Masks the interrupt source of IRL7 to IRL4 = LLHH (H'3).
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10. Interrupt Controller (INTC) Bit Name Initial Value R/W Description 2 IM102 0 R/W 1 IM101 0 R/W Masks the interrupt source [When read] of IRL7 to IRL4 = HHLH 0: The interrupt is (H'D). accepted. Masks the interrupt source 1: The interrupt is of IRL7 to IRL4 = HHHL masked. (H'E). [When written] 0: No effect 1: Masks the interrupt 0 — 0 R Reserved This bit is always read as 0. The write value should always be 0. Rev.1.00 Jan.
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10. Interrupt Controller (INTC) (8) Interrupt Mask Clear Register 0 (INTMSKCLR0) INTMSKCLR0 is a 32-bit write-only register that clears the mask settings for each of the interrupt requests IRQn (n = 0 to 7). Undefined values are read from this register.
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10. Interrupt Controller (INTC) (9) Interrupt Mask Clear Register 1 (INTMSKCLR1) INTMSKCLR1 is a 32-bit write-only register that clears the mask settings for the IRL interrupt requests. Undefined values are read from this register.
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10. Interrupt Controller (INTC) (10) Interrupt Mask Clear Register 2 (INTMSKCLR2) INTMSKCLR2 is a 32-bit write-only register that clears the mask settings for the IRL interrupt requests for each input level pattern on the IRL pins. Undefined values are read from this register.
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10. Interrupt Controller (INTC) Bit Name Initial Value R/W Description 23 IC007 0 R/W Clears masking of the interrupt source of IRL3 to IRL0 = HLLL (H'8). [When read] Clears masking of the interrupt source of IRL3 to IRL0 = HLLH (H'9). [When written] 22 IC006 0 R/W 21 IC005 0 R/W Clears masking of the interrupt source of IRL3 to IRL0 = HLHL (H'A). 20 IC004 0 R/W Clears masking of the interrupt source of IRL3 to IRL0 = HLHH (H'B).
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10. Interrupt Controller (INTC) Bit Name Initial Value R/W Description 11 IC111 0 R/W Clears masking of the interrupt source of IRL7 to IRL4 = LHLL (H'4). [When read] Clears masking of the interrupt source of IRL7 to IRL4 = LHLH (H'5). [When written] 10 IC110 0 R/W 9 IC109 0 R/W Clears masking of the interrupt source of IRL7 to IRL4 = LHHL (H'6). 8 IC108 0 R/W Clears masking of the interrupt source of IRL7 to IRL4 = LHHH (H'7).
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10. Interrupt Controller (INTC) (11) NMI Flag Control Register (NMIFCR) NMIFCR is a 32-bit readable and conditionally writable register that has an NMI flag (NMIFL bit). The NMIFL bit is automatically set to 1 when an NMI interrupt is detected by the INTC. Writing 0 to the NMIFL bit clears it. The value of the NMIFL bit does not affect acceptance of the NMI by the CPU. Although an NMI request detected by the INTC is cleared when the CPU accepts the NMI, the NMIFL bit is not cleared automatically.
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10. Interrupt Controller (INTC) Bit Name Initial Value R/W 16 NMIFL 0 R/(W) NMI Flag (NMI Interrupt Request Detection) Description Indicates whether an NMI interrupt request signal has been detected. This bit is automatically set to 1 when the INTC detects an NMI interrupt request. Write 0 to clear the bit. Writing 1 to this bit has no effect.
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10. Interrupt Controller (INTC) 10.3.2 (1) User Mode Interrupt Disable Function User Interrupt Mask Level Setting Register (USERIMASK) USERIMASK is a 32-bit readable and conditionally writable register that sets the acceptable interrupt level. This register is allocated to the 64-Kbyte page that the other registers in the INTC are not allocated. Therefore, only this register can be set to be accessible in user mode by changing the address to area 7 address through the MMU.
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10. Interrupt Controller (INTC) Initial Value R/W Description 31 to 24 (Code for writing) H'00 R/W Code for writing (H'A5) 23 to 8 All 0 Bit Name — These bits are always read as 0. Set these bits to H'A5 when writing to the UIMASK bits (Write to the UIMASK bits with these bits set to H'A5). R Reserved These bits are always read as 0. The write value should always be 0.
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10. Interrupt Controller (INTC) 3. Branch to the device driver. 4. In the device driver operating in user mode, set the UIMASK bits to mask the B-type interrupts. 5. Process more urgent interrupts in the device driver. 6. Clear the UIMASK bit to 0 and return from the processing by the device driver. 10.3.
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10. Interrupt Controller (INTC) Table 10.
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10. Interrupt Controller (INTC) (2) Interrupt Source Register (Not affected by Mask Setting) (INT2A0) INT2A0 is a 32-bit read-only register that indicates the interrupt sources of on-chip peripheral modules. Even if an interrupt is masked by the interrupt mask register, the corresponding bit in INT2A0 is set (further interrupt operation is not performed for the corresponding bit). Use INT2A1 instead if the bits for the interrupt sources masked by the interrupt mask registers should not be set.
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10. Interrupt Controller (INTC) Bit Initial Value R/W Source Function Description 21 Undefined R HSPI HSPI interrupt source indication 20 Undefined R SIOF SIOF interrupt source indication 19 Undefined R PCIC (5) PCIERR and PCIPWD3 to PCIPWD0 interrupt source indication These bits indicate the interrupt source of each peripheral module that is generating an interrupt. (INT2A0 is not affected by the setting of the interrupt mask register).
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10. Interrupt Controller (INTC) Bit Initial Value 5 Undefined R 4 R/W Source Function Description SCIF channel 3 SCIF channel 3 interrupt source indication Undefined R SCIF channel 2 SCIF channel 2 interrupt source indication 3 Undefined R SCIF channel 1 SCIF channel 1 interrupt source indication These bits indicate the interrupt source of each peripheral module that is generating an interrupt. (INT2A0 is not affected by the setting of the interrupt mask register).
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10. Interrupt Controller (INTC) Table 10.7 Reflection time for INT2A0 and INT2A1 when Interrupt Source Bit in Peripheral Module Is Set/Cleared Module WDT, TMU, SCIF, HSPI, SIOF, MMCIF, DU, SSI, HAC, FLCTL Relation between Setting/Clearing Interrupt Source of Module and Indication by INT2A0 and INT2A1 When an interrupt source bit is set in the register* in the module that indicates generation of interrupt requests, the same interrupt status information is read from that register and INT2A0 or INT2A1.
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10. Interrupt Controller (INTC) Module DMAC Relation between Setting/Clearing Interrupt Source of Module and Indication by INT2A0 and INT2A1 Interrupt sources When the DMAE0 or DMAE1 interrupt source bit (i.e. the AE bit DMAE0, DMAE1 in DMAOR0 or DMAOR1) is set, the same interrupt status information is read from registers DMAOR0 and DMAOR1 and registers INT2A0 and INT2A1. This means that the time required for reflection in INT2A0 and INT2A1 is guaranteed by hardware.
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10. Interrupt Controller (INTC) (3) Interrupt Source Register (Affected by Mask States) (INT2A1) INT2A1 is a 32-bit read-only register that indicates the interrupt sources of on-chip peripheral modules. If an interrupt is masked by the interrupt mask register, the corresponding bit in INT2A1 is not set to 1. Use INT2A0 to check whether interrupts have been generated, regardless of the state of the interrupt mask register.
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10. Interrupt Controller (INTC) Bit Initial Value R/W Source 20 0 R 19 0 18 Function Description SIOF SIOF interrupt source indication R PCIC (5) PCIERR and PCIPWD3 to PCIPWD0 interrupt source indication These bits indicate the interrupt source of each peripheral module that is generating an interrupt. (INT2A1 is affected by the setting of the interrupt mask register).
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10. Interrupt Controller (INTC) Bit Initial Value R/W Source 3 0 R 2 0 1 0 Function Description SCIF channel 1 SCIF channel 1 interrupt source indication R SCIF channel 0 SCIF channel 0 interrupt source indication 0 R TMU channels 3 to 5 These bits indicate the interrupt source of each peripheral module that is generating an interrupt. (INT2A1 is affected by the setting of the interrupt mask register).
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10. Interrupt Controller (INTC) (4) Interrupt Mask Register (INT2MSKR) INT2MSKR is a 32-bit readable/writable register that can mask interrupts for sources indicated in the interrupt source register. When a bit in this register is set to 1, the interrupt in the corresponding bit is not notified. INT2MSKR is initialized to H'FFFF FFFF (all masked) by a reset.
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10.
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10. Interrupt Controller (INTC) (5) Interrupt Mask Clear Register (INT2MSKCR) INT2MSKCR is a 32-bit write-only register that clears the masking set in the interrupt mask register. When the corresponding bit in this register is set to 1, the interrupt source masking is cleared. These bits are always read as 0.
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10.
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10. Interrupt Controller (INTC) 10.3.4 Individual On-Chip Module Interrupt Source Registers (INT2B0 to INT2B7) INT2B0 to INT2B7 are registers that indicate more details on each interrupt source, in addition to the interrupt source that is corresponding to each module and is indicated in the interrupt source register. INT2B0 to INT2B7 are 32-bit read-only registers that are not affected by the masked state in the interrupt mask register.
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10. Interrupt Controller (INTC) (2) INT2B1: Detailed Interrupt Sources for the SCIF Module Bit Name Detailed Source Description SCIF 31 to 24 ⎯ Reserved These bits are read as 0 and cannot be modified. 23 TXI5 SCIF channel 5 transmit FIFO data empty interrupt SCIF interrupt sources are indicated. This register indicates the SCIF interrupt sources even if the mask setting for SCIF is made in the interrupt mask register.
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10. Interrupt Controller (INTC) Module Bit Name Detailed Source Description SCIF 11 TXI2 SCIF channel 2 transmit FIFO data empty interrupt 10 BRI2 SCIF channel 2 break interrupt or overrun error interrupt SCIF interrupt sources are indicated. This register indicates the SCIF interrupt sources even if the mask setting for SCIF is made in the interrupt mask register.
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10. Interrupt Controller (INTC) (3) INT2B2: Detailed Interrupt Sources for the DMAC Module Bit Name Detailed Source Description DMAC 31 to 14 ⎯ Reserved These bits are read as 0 and cannot be modified. 13 DMAE1 Channels 6 to 11 DMA address error interrupt DMAC interrupt sources are indicated. This register indicates the DMAC interrupt sources even if the mask setting for DMAC is made in the interrupt mask register.
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10. Interrupt Controller (INTC) (4) INT2B3: Detailed Interrupt Sources for the PCIC Module Bit Name Detailed Source Description PCIC 31 to 10 ⎯ Reserved These bits are read as 0 and cannot be modified. 9 PCIPWD0 PCIC power state D0 state interrupt PCIC interrupt sources are indicated. This register indicates the PCIC interrupt sources even if the mask setting for PCIC is made in the interrupt mask register.
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10. Interrupt Controller (INTC) (5) INT2B4: Detailed Interrupt Sources for the MMCIF Module Bit Name Detailed Source MMCIF 31 to 4 ⎯ 3 FRDY 2 ERR Reserved MMCIF interrupt sources are These bits are read as 0 indicated. This register indicates the and cannot be modified. MMCIF interrupt sources even if the mask setting for MMCIF is made in FIFO ready end interrupt the interrupt mask register.
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10. Interrupt Controller (INTC) (7) INT2B6: Detailed Interrupt Sources for the GPIO Module Bit Name GPIO 31 to 26 ⎯ 25 PORTL7I 24 PORTL6I Detailed Source Reserved These bits are read as 0 and cannot be modified. Description GPIO interrupt sources are indicated. This register indicates the GPIO interrupt sources even if the mask setting for GPIO is made in GPIO interrupt from port L the interrupt mask register.
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10. Interrupt Controller (INTC) (8) INT2B7: Detailed Interrupt Sources for the GDTA Module Bit Name Detailed Source Description GDTA 31 to 3 ⎯ Reserved These bits are read as 0 and cannot be modified. 2 GAERI GDTA error interrupt 1 GAMCI MC transfer end interrupt GDTA interrupt sources are indicated. This register indicates the GDTA interrupt sources even if the mask setting for GDTA is made in the interrupt mask register. 0 GACLI CL transfer end interrupt Rev.1.00 Jan.
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10. Interrupt Controller (INTC) 10.3.5 GPIO Interrupt Set Register (INT2GPIC) INT2GPIC enables interrupt requests input from the pins 0 to 5 of port E, pins 1 to 4 of port H, pins 6 and 7 of port L, as GPIO interrupts. A GPIO interrupt is a low-active interrupt. Enable interrupt requests after setting the pins corresponding to the port control register (E, H, and L) used for GPIO interrupts to be input pins from ports For the port control registers, see section 28, General Purpose I/O Ports (GPIO).
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10. Interrupt Controller (INTC) Initial Value R/W Bit Name 18 PORTH3E 0 R/W Enables interrupt request from pin 3 Enables a GPIO interrupt request for each pin. of port H. 17 PORTH2E 0 R/W 16 PORTH1E 0 R/W Enables interrupt request from pin 2 0: Disable the corresponding interrupt of port H. request Enables interrupt request from pin 1 1: Enable the of port H. corresponding interrupt Reserved request These bits are always read as 0. The write value should always be 0.
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10. Interrupt Controller (INTC) 10.4 Interrupt Sources There are four types of interrupt sources, NMI, IRQ, IRL, and on-chip module interrupts. Each interrupt has a priority level (16 to 0). Level 16 is the highest and level 1 is the lowest. When the level is set to 0, the interrupt is masked and interrupt requests are ignored. 10.4.1 NMI Interrupts The NMI interrupt has the highest priority of level 16. The interrupt is always accepted unless the BL bit in SR of the CPU is set to 1.
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10. Interrupt Controller (INTC) (2) Dependence on ICR0.LVLMODE Setting For the IRQ interrupt at level detection, there are the following features according to the setting of ICR0.LVLMODE. The initial value of the ICR0 bit in LVLMODE is 0. It is recommended to set the bit to 1 before using the INTC. (a) ICR0.
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10. Interrupt Controller (INTC) SH7785 Interrupt requests Priority encoder IRL3 to IRL0 IRQ/IRL3 to IRQ/IRL0 Interrupt requests Priority encoder IRL7 to IRL4 IRQ/IRL7 to IRQ/IRL4 Figure 10.3 Example of IRL Interrupt Connection Table 10.
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10. Interrupt Controller (INTC) The priority of IRL interrupts should be retained from when an interrupt is accepted to when interrupt handling starts. The level can be changed to a higher level. When the INTMU bit in CPUOPM is set to 1, the interrupt mask level (IMASK) bit in SR is automatically set to the level of the accepted interrupt. When the INTMU bit in CPUOPM is cleared to 0, the IMASK bit in SR is not affected.
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10. Interrupt Controller (INTC) An on-chip peripheral module interrupt source flag or an interrupt enable flag should be updated when the BL bit in SR is set to 1 or when the corresponding interrupt is not generated by the setting of interrupt masking occurs. To prevent the acceptance of incorrect interrupts by the updated interrupt source, read from the on-chip peripheral module register that has the corresponding flag.
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10. Interrupt Controller (INTC) An interrupt request is masked if priority level H'01 is set. INTC Priority level: H'01 0 INTC distinguishes between priority levels H'1A and H'1B, although both become the same level after truncating the least significant bit for the CPU.
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10. Interrupt Controller (INTC) Table 10.
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10. Interrupt Controller (INTC) Interrupt Source INTEVT Interrupt Code Priority Mask/Clear Register & Bit INTMSK2[7] INTMSKCLR2[7] IRL IRL[3:0] = HLLL (H'8) H'300 L: Low level input IRL[7:4] = HLLL (H'8) H'C00 IRL[3:0] = HLLH (H'9) H'320 IRL[7:4] = HLLH (H'9) H'C20 H: High level input (See table 10.
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10.
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10.
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10.
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10.
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10.
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10. Interrupt Controller (INTC) 10.5 Operation 10.5.1 Interrupt Sequence The sequence of interrupt operations is described below. Figure 10.4 shows a flowchart of the operations. 1. Interrupt request sources send interrupt request signals to the INTC. 2. The INTC selects the interrupt with the highest priority among the interrupts that have been sent, according to the priority set in INTPRI and INT2PRI0 to INT2PRI9. Lower priority interrupts are held as pending interrupts.
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10. Interrupt Controller (INTC) Program execution state Yes ICR0.MAI = 1? No Is NMI input low? Yes No No Interrupt generated? Yes Yes SR.BL = 0 or sleep mode? No No ICR0.NMIB = 1? Yes No NMI? Yes NMI? No Level 15 interrupt? Yes Yes Yes Level 14 interrupt? Is SR.IMASK level 14 or less? No No Yes Yes Level 1 interrupt? Is SR.IMASK level 13 or less? No Yes No CPUOPM.INTMU = 1? Yes Set SR.
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10. Interrupt Controller (INTC) 10.5.2 Multiple Interrupts To handle multiple interrupts, the procedure for the interrupt handling routine should be as follows. 1. To identify the interrupt source, set the value of INTEVT to an offset and branch it to the interrupt handling routine for each interrupt source. 2. Clear the corresponding interrupt source in the interrupt handling routine. 3. Save SSR and SPC on the stack. 4. Clear the BL bit in SR.
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10. Interrupt Controller (INTC) 10.6 Interrupt Response Time Table 10.14 shows response time. The response time is the interval from generation of an interrupt request until the start of interrupt exception handling and until fetching of the first instruction of the exception handling routine. Table 10.
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10. Interrupt Controller (INTC) Table 10.15 shows response time. The response time is from the interrupt exception handling to the start of fetching the first instruction in exception handling routine. In this case, suppose that the setting values of the following registers that enable or disable interrupt, INTMSK0, INTMSK1, INTMSK2, INT2MSKR, and INT2GPIC, are changed from the interrupt disable state to the interrupt enable state. Table 10.
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10. Interrupt Controller (INTC) Table 10.16 shows response time. The response time is the time until when the interrupt request signal from the INTC to the CPU is negated. In this case, suppose that the setting values of the following registers, INTMSK0, INTMSK1, INTMSK2, INT2MSKR, and INT2GPIC, are changed from the interrupt enable state to the interrupt disable state. Table 10.
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10. Interrupt Controller (INTC) 10.7 Usage Notes 10.7.1 Example of Handing Routine of IRL Interrupts and Level Detection IRQ Interrupts when ICR0.LVLMODE = 0 When ICR0.LVLMODE is 0, IRL interrupt requests and level detection IRQ interrupt requests that the INTC retains should be cleared in the interrupt handling routine because the CPU detects after accepting interrupts. The IRQ interrupt sources (INTREQ) should also be cleared.
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10. Interrupt Controller (INTC) 10.7.2 Notes on Setting IRQ/IRL[7:0] Pin Function When the IRQ/IRL[7:0] pin functions are switched, the INTC may retain an incorrectly detected interrupt request. Therefore, mask the IRL and IRQ interrupt requests before switching the IRQ/IRL[7:0] pin functions. Table 10.
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10. Interrupt Controller (INTC) 10.7.3 Clearing IRQ and IRL Interrupt Requests To clear the interrupt request retained in the INTC, follow the procedure below. (1) Clearing Interrupt Request Independent from ICR0.LVLMODE Setting ⎯ Clearing IRQ interrupt requests at edge detection To clear the interrupt requests IRQ7 to IRQ0 setting edge detection, read the IR7 to IR0 bits corresponding to INTREQ as 1 and write 0 to the bits.
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10. Interrupt Controller (INTC) Rev.1.00 Jan.
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11. Local Bus State Controller (LBSC) Section 11 Local Bus State Controller (LBSC) The local bus state controller (LBSC) divides the external memory space and outputs control signals according to the specification of each memory and bus interface. The LBSC function enables connection of the SRAM or ROM, etc. to this LSI. The LBSC also supports the PCMCIA interface protocol, which implements simple system design and high-speed data transfers in a compact system. 11.
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11. Local Bus State Controller (LBSC) SuperHyway bus Figure 11.1 shows a block diagram of the LBSC. Bus interface CSnWCR CS0 to CS6 CE2A to CE2B ... RDY Wait controller Area controller CSnBCR Module bus ... BS RD R/W WE7 to WE0 IORD, IOWR REG BCR Memory controller CSnPCR IOIS16 LBSC Legend: CSnWCR: CSn wait control register (n = 0 to 6) CSnBCR: CSn bus control register (n = 0 to 6) BCR: Bus control register CSnPCR: CSn PCMCIA control register (n = 5 and 6) Figure 11.
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11. Local Bus State Controller (LBSC) 11.2 Input/Output Pins Table 11.1 shows the LBSC pin configuration. Table 11.
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11.
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11. Local Bus State Controller (LBSC) Pin Name Function I/O Description BACK Bus Request Acknowledge O Bus request acknowledge signal PCMCIA Card Select O CE2A* , CE2B*2 1 Multiplexed with Port M0 (GPIO input/output).
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11.
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11. Local Bus State Controller (LBSC) 11.3 Overview of Areas 11.3.1 Space Divisions The LSI has a 32-bit virtual address space as the architecture. The virtual address space is divided into five areas according to the upper address value. Also, the memory space of the local bus has a 29-bit address space, and it is divided into eight areas. A virtual address can be allocated to any external address by the address changing unit (MMU). For details, see section 7, Memory Management Unit (MMU).
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11. Local Bus State Controller (LBSC) Table 11.
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11. Local Bus State Controller (LBSC) Area 6 External addresses Size H'1800 0000 to H'1BFF FFFF 7* 7 Connectable Memory 64 Mbytes SRAM Specifiable Bus Width (bits) 8, 16, 32, 64*2 2 MPX 32, 64* Burst ROM 8, 16, 32, 64*2 PCMCIA 8, 16* H'1C00 0000 to 64 Mbytes ⎯ H'1FFF FFFF Access Size*7 8/16/32 bits, 32 bytes 2, 5 ⎯ — Notes: 1. The memory bus width is specified by the external pins. 2. The memory bus width is specified by the register. 3.
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11. Local Bus State Controller (LBSC) 11.3.2 Memory Bus Width The memory bus width of the LBSC can be set independently for each area. In area 0, a bus width of 8, 16, 32, or 64 bits is selected according to the external pin settings at a power-on reset by the PRESET pin. The relation between the external pins (MODE 6 and MODE 5) and the bus width at a power-on reset is shown below.
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11. Local Bus State Controller (LBSC) 11.3.3 PCMCIA Support This LSI supports the PCMCIA interface specifications for areas 5 and 6 in the external memory space. The IC memory card interface and I/O card interface specified in JEIDA specifications version 4.2 (PCMCIA2.1) are supported. Both the IC memory card interface and the I/O card interface are supported in areas 5 and 6 in the external memory space. The PCMCIA interface is supported only in little endian mode. Table 11.
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11. Local Bus State Controller (LBSC) Table 11.
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11.
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11.
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11. Local Bus State Controller (LBSC) 11.4 Register Descriptions Table 11.5 shows registers for the LBSC. These registers control the interface with each memory, wait state, etc. Table 11.5 Register Configuration (1) Area 7 Address Access Size* Sync Clock Register Name Abbrev.
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11. Local Bus State Controller (LBSC) Table 11.5 Register Configuration (2) Register Name Abbrev.
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11. Local Bus State Controller (LBSC) 11.4.1 Memory Address Map Select Register (MMSELR) MMSELR is a 32-bit register that selects memory address maps for areas 2 to 5. This register should be accessed at the address H'FC40 0020 in longword. To prevent incorrect writing, writing is accepted only when the upper 16-bit data is H'A5A5. The upper 29 bits are always read as 0. This register is initialized to H'0000 0000 by a power-on reset or a manual reset.
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11.
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11. Local Bus State Controller (LBSC) Example: ----------------------------------------------------------------------MOV.L #H'FC400020, R0 ; MOV.L #MMSELR_DATA, R1 ; MMSELR_DATA=Writing value of MMSELR SYNCO ; (upper word=H'A5A5) MOV.L R1, @R0 ; Writing to MMSELR MOV.L @R0, R2 MOV.
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11. Local Bus State Controller (LBSC) 11.4.2 Bus Control Register (BCR) BCR is a 32-bit readable/writable register that specifies the function, bus cycle state, etc for each area. BCR is initialized to H'0000 0000 in big endian mode and to H'8000 0000 in little endian mode by a power-on reset, however, not initialized by a manual reset.
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11. Local Bus State Controller (LBSC) Bit Bit Name Initial Value R/W Description 26 DPUP 0 R/W 25 ⎯ 0 R Data Pin Pull-Up Resistor Control Specifies the pull-up resistor state of the data pins (D63 to D0). This bit is initialized at a power-on reset. The pins are not pulled up when access is performed or when the bus is released, even if the pull-up resistor is on. 0: Some cycles of the pull-up resistors of the data pins (D63 to D0) are turned on before and after a memory access.
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11. Local Bus State Controller (LBSC) Bit Bit Name Initial Value R/W 19, 18 ⎯ All 0 R Description Reserved These bits are always read as 0. The write value should always be 0. 17 BREQEN 0 R/W BREQ Enable Specifies whether an external request can be accepted or not. In the initialized state at a power-on reset, an external request is not accepted. When this LSI is booted up in slave mode, an external request is accepted regardless of the BREQEN value.
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11. Local Bus State Controller (LBSC) Initial Value Bit Bit Name 6 to 0 ASYNC[6:0] All 0 R/W Description R/W Asynchronous Input These bits enable asynchronous inputs of the corresponding pins.
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11. Local Bus State Controller (LBSC) 11.4.3 CSn Bus Control Register (CSnBCR) CSnBCR are 32-bit readable/writable registers that specify the bus width for area n (n = 0 to 6), idle mode between cycles, burst ROM setting and memory types. Some types of memory continue to drive the data bus immediately after the read signal is turned off. Therefore, data buses may collide with each other when different memory areas are accessed consecutively or memory writing is performed immediately after it is read.
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11. Local Bus State Controller (LBSC) Bit Bit Name 30 to 28 IWW Initial Value R/W Description 111 R/W Idle Cycles between Write-Read/Write-Write These bits specify the number of idle cycles to be inserted after the access of the memory connected to the space. The target cycles are write-read and writewrite cycles. For details, see section 11.5.8, Wait Cycles between Access Cycles.
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11. Local Bus State Controller (LBSC) Bit Bit Name Initial Value R/W 23 ⎯ 0 R Description Reserved This bit is always read as 0. The write value should always be 0. 22 to 20 IWRWS 111 R/W Idle Cycles between Read-Write in Same Space These bits specify the number of idle cycles to be inserted after the access to the memory connected to the space. The target cycles are read-write cycles in which consecutive accesses are performed to the same space. For details, see section 11.5.
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11. Local Bus State Controller (LBSC) Bit Bit Name Initial Value R/W Description 15 ⎯ 0 R Reserved This bit is always read as 0. The write value should always be 0. 14 to 12 IWRRS 111 R/W Idle Cycles between Read-Read in Same Space These bits specify the number of idle cycles to be inserted after the memory connected to the space is accessed. The target cycles are read-read cycles in which consecutive accesses are performed to the same space. For details, see section 11.5.
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11. Local Bus State Controller (LBSC) Bit Bit Name Initial Value R/W 9, 8 SZ 11 R/W* Description Bus Width In CS0BCR, the external pins (MODE5 and MODE6) to specify the bus size are sampled at a power-on reset. When using the MPX interface, set these bits to 00 or 11. When using the byte control SRAM interface, set these bits to 00, 10 or 11. 00: 64 bits (can be specified when the MODE 12 and MODE 11 pins are set to 1 and 0 respectively.
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11. Local Bus State Controller (LBSC) Bit Bit Name Initial Value R/W Description 6 to 4 BW 111 R/W Burst Pitch When the burst ROM interface is used, these bits specify the number of wait cycles to be inserted after the second data access in a burst transfer.
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11. Local Bus State Controller (LBSC) 11.4.
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11. Local Bus State Controller (LBSC) Bit Bit Name Initial Value R/W Description 27 ⎯ 0 R Reserved This bit is always read as 0. The write value should always be 0. 26 to 24 ADH 111 R/W Address Hold Cycle These bits specify the number of cycles to be inserted as the address hold time with respect to CSn negation. (Only valid when the SRAM interface, byte control SRAM interface, or burst ROM interface is selected.
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11. Local Bus State Controller (LBSC) Bit Bit Name Initial Value R/W Description 19 ⎯ 0 R Reserved This bit is always read as 0. The write value should always be 0. 18 to 16 RDH 111 R/W RD Hold Cycle (RD Negation–CSn Negation Delay Cycle) These bits specify the number of cycles to be inserted as the time from RD negation to CSn negation. (Only valid when the SRAM interface, byte control SRAM interface, or burst ROM interface is selected.
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11. Local Bus State Controller (LBSC) Bit Bit Name Initial Value R/W Description 11 ⎯ 0 R Reserved This bit is always read as 0. The write value should always be 0. 10 to 8 WTH 111 R/W WE Hold Cycle (WE Negation–CSn Negation Delay Cycle) These bits specify the number of cycles to be inserted as the time from WE negation to CSn negation. (Only valid when the SRAM interface, byte control SRAM interface, or burst ROM interface is selected.) 000: No cycle inserted (0.
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11. Local Bus State Controller (LBSC) Bit Bit Name Initial Value R/W Description 3 to 0 IW[3:0] 1111 R/W Insert Wait Cycle These bits specify the number of wait cycles to be inserted. The wait cycles are as follows when the SRAM interface, byte control SRAM interface, burst ROM interface (first data cycle only), or PCMCIA interface is selected. Insertion of external wait cycles by the RDY pin is not possible when "no cycle inserted" is selected.
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11. Local Bus State Controller (LBSC) 11.4.5 CSn PCMCIA Control Register (CSnPCR) CSnPCR is a 32-bit readable/writable register that specifies the timing for the PCMCIA interface connected to area n (CSnPCR, n = 5 or 6), the space property, and the assert/negate timing for the OE and WE signals. Also, areas 5 and 6 in CSnPCR can be set for the first half and second half individually.
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11. Local Bus State Controller (LBSC) Bit Bit Name Initial Value R/W Description 27 ⎯ 0 R Reserved This bit is always read as 0. The write value should always be 0. 26 to 24 SAB 111 R/W Space Property B These bits specify the space property of PCMCIA connected to the second half of the area.
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11. Local Bus State Controller (LBSC) Bit Bit Name 19 to 16 PCIW Initial Value R/W Description 0000 R/W PCMCIA Insert Wait Cycle B These bits specify the number of wait cycles to be inserted. The bit settings are selected when the access area of PCMCIA interface is the second half. When the access area of PCMCIA interface is the first half, the number of wait cycles set by the IW bit in CSnWCR is selected.
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11. Local Bus State Controller (LBSC) Bit Bit Name 14 to 12 TEDA Initial Value R/W Description 000 R/W OE/WE Assert Delay A These bits set the delay time from address output to OE/WE assertion when the first half area is accessed with the connected PCMCIA interface.
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11. Local Bus State Controller (LBSC) Bit Bit Name Initial Value R/W Description 6 to 4 TEHA 000 R/W OE/WE Negation-Address Delay A These bits set the delay time from OE/WE negation to address hold when the first half area is accessed with the connected PCMCIA interface.
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11. Local Bus State Controller (LBSC) 11.5 Operation 11.5.1 Endian/Access Size and Data Alignment This LSI supports both big and little endian modes. In big endian mode, the most significant byte (MSByte) in a string of byte data is stored at address 0, and in little endian mode, the least significant byte (LSByte) in a string of byte data is stored at address 0. The mode is specified by the external pin (MODE8 pin) at a power-on reset by the PRESET pin.
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11. Local Bus State Controller (LBSC) Table 11.6 64-Bit External Device/Big Endian Access and Data Alignment (1) Operation Data Bus Access D63 to D55 to D47 to D39 to D31 to D23 to Size Address No.
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11. Local Bus State Controller (LBSC) Table 11.7 64-Bit External Device/Big Endian Access and Data Alignment (2) Operation Strobe Signal Access Size Address No.
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11. Local Bus State Controller (LBSC) Table 11.8 32-Bit External Device/Big-Endian Access and Data Alignment Operation Data Bus Strobe Signals Access Size Address D31 to No.
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11. Local Bus State Controller (LBSC) Table 11.9 16-Bit External Device/Big-Endian Access and Data Alignment Operation Data Bus Access Size Address D31 to No.
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11. Local Bus State Controller (LBSC) Table 11.10 8-Bit External Device/Big-Endian Access and Data Alignment Operation Data Bus Strobe Signals Access Size Address No.
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11. Local Bus State Controller (LBSC) Table 11.11 64-Bit External Device/Little Endian Access and Data Alignment (1) Operation Data Bus Access D63 to D55 to D47 to D39 to D31 to D23 to Size Address No.
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11. Local Bus State Controller (LBSC) Table 11.12 64-Bit External Device/Little Endian Access and Data Alignment (2) Operation Strobe Signal Access Size Address No.
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11. Local Bus State Controller (LBSC) Table 11.13 32-Bit External Device/Little-Endian Access and Data Alignment Operation Data Bus Strobe Signals Access Size Address No.
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11. Local Bus State Controller (LBSC) Table 11.14 16-Bit External Device/Little-Endian Access and Data Alignment Operation Data Bus Strobe Signals Access Size Address No.
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11. Local Bus State Controller (LBSC) Table 11.15 8-Bit External Device/Little-Endian Access and Data Alignment Operation Data Bus Strobe Signals Access Size Address No.
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11. Local Bus State Controller (LBSC) 11.5.2 (1) Areas Area 0 Area 0 is an area where bits 28 to 26 in the local bus address are 000. The interface that can be set for this area is the SRAM, burst ROM or MPX interface. A bus width of 8, 16, 32, or 64 bits is selectable by external pins MODE6 and MODE5 at a poweron reset. For details, see section 11.3.2, Memory Bus Width. When area 0 is accessed, the CS0 signal is asserted.
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11. Local Bus State Controller (LBSC) For the number of bus cycles, 0 to 25 wait cycles to be inserted can be selected by CS1WCR. When the burst ROM interface is used, the number of a burst pitch is selectable in the range from 0 to 7 with the BW bits in CS1BCR. Any number of wait cycles can be inserted in each bus cycle through the external wait pin (RDY). (when no cycles are inserted, the RDY signal is ignored.
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11. Local Bus State Controller (LBSC) (4) Area 3 Area 3 is an area where bits 28 to 26 in the local bus address are 011. The interface that can be set for this area is the SRAM, MPX, or burst ROM interface. A bus width of 8, 16, 32, or 64 bits is selectable by bits SZ in CS3BCR. When the MPX interface is used, a bus width of 32 or 64 bits should be selected by the SZ bits in CS3BCR. When area 3 is accessed, the CS3 signal is asserted.
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11. Local Bus State Controller (LBSC) For the number of bus cycles, 0 to 25 wait cycles inserted can be selected by CS4WCR. When the burst ROM interface is used, the number of a burst pitch is selectable in the range from 0 to 7 with the BW bits in CS4BCR. Any number of wait cycles can be inserted in each bus cycle through the external wait pin (RDY). (when no cycles are inserted, the RDY signal is ignored.
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11. Local Bus State Controller (LBSC) CS5PCR. In addition, the number of wait cycles can be specified in the range from 0 to 50 cycles by the PCWA/B bit. The number of wait cycles specified by CS5PCR is added to the value specified by bits IW3 to IW0 in CS5WCR or bits PCIW3 to PCIW0 in CS5PCR. (7) Area 6 Area 6 is an area where bits 28 to 26 in the local bus address are 110. The interface is that can be set for this area is the SRAM, MPX, burst ROM, and PCMCIA interface.
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11. Local Bus State Controller (LBSC) 11.5.3 (1) SRAM interface Basic Timing The strobe signals for the SRAM interface in this LSI are output primarily based on the SRAM connection. Figure 11.5 shows the basic timing of the SRAM interface. Normal access without wait cycles is completed in two cycles. The BS signal is asserted for one or two cycles to indicate the start of a bus cycle.
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11. Local Bus State Controller (LBSC) T1 T2 CLKOUT A25 to A0 CSn R/W RD D31 to D0 (In reading) WEn D31 to D0 (In writing) BS RDY DACKn In this example, DACKn is high-active. Figure 11.5 Basic Timing of SRAM Interface Rev.1.00 Jan.
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11. Local Bus State Controller (LBSC) Figures 11.6 to 11.8 show examples of connections to SRAM with 32-, 16- and 8-bit data width, respectively.
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11. Local Bus State Controller (LBSC) 128K × 8 bits SRAM SH7785 •••• •••• A0 CS OE I/O7 •••• •••• D8 WE1 D7 •••• I/O0 WE D0 WE0 •••• •••• •••• A16 A0 CS OE I/O7 •••• •••• A1 CSn RD D15 •••• •••• A16 A17 I/O0 WE Figure 11.7 Example of 16-Bit Data Width SRAM Connection Rev.1.00 Jan.
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11. Local Bus State Controller (LBSC) 128K × 8 bits SRAM D0 WE0 •••• •••• A16 •••• A0 CS OE I/O7 •••• •••• A0 CSn RD D7 •••• •••• A16 •••• SH7785 I/O0 WE Figure 11.8 Example of 8-Bit Data Width SRAM Connection (2) Wait Cycle Control Wait cycle insertion for the SRAM interface can be controlled by CSnWCR. If the IW bits in CSnWCR are set to a value other than 0, a software wait is inserted in accordance with the wait control bits. For details, see section 11.4.
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11. Local Bus State Controller (LBSC) T1 Tw T2 CLKOUT A25 to A0 CSn R/W RD D31 to D0 (In reading) WEn D31 to D0 (In writing) BS RDY DACKn : Sampling Timing In this example, DACKn is active-high. (The circle indicates the sampling timing.) Figure 11.9 SRAM Interface Wait Timing (Software Wait Only) Rev.1.00 Jan.
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11. Local Bus State Controller (LBSC) When software wait insertion is specified by CSnWCR, the external wait input signal, RDY, is also sampled. The RDY signal sampling timing is shown in figure 11.10, where a single wait cycle is specified as a software wait. The RDY signal is sampled at the transition from the Tw state to the T2 state. Therefore, the assertion of the RDY signal has no effect in the T1 cycle or in the first Tw cycle. The RDY signal is sampled on the rising edge of the clock.
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11. Local Bus State Controller (LBSC) (3) Read-Strobe/Write-Strobe Timing When the SRAM interface is used, the strobe signal negation timing in reading can be specified with the RDSPL bit in CSnBCR. For details of settings, see section 11.4.3, CSn Bus Control Register (CSnBCR). The RDSPL bit should be cleared to 0 when a byte control SRAM is specified. Rev.1.00 Jan.
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11.
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11. Local Bus State Controller (LBSC) 11.5.4 Burst ROM Interface When the TYPE bit in CSnBCR is set to 010, a burst ROM can be connected to areas 0 to 6. The burst ROM interface provides high-speed access to ROM that has a burst access function. The burst access timing of burst ROM is shown in figure 11.12. The wait cycle is set to 0. Although the access is similar to that of the SRAM interface, only the address is changed when the first cycle ends and then the next access is started.
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11. Local Bus State Controller (LBSC) T1 TB2 TB1 TB2 TB1 TB2 TB1 T2 CLKOUT A25 to A5 A4 to A0 CSn R/W RD D31 to D0 (In reading) BS RDY Figure 11.12 Burst ROM Basic Timing Rev.1.00 Jan.
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11. Local Bus State Controller (LBSC) T1 Tw Twe TB2 TB1 Tw TB2 TB1 Tw CLKOUT A25 to A5 A4 to A0 CSn R/W RD D31 to D0 (In reading) BS RDY Figure 11.13 Burst ROM Wait Timing Rev.1.00 Jan.
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11. Local Bus State Controller (LBSC) TAS1 T1 TS1 TB2 TB1 TB2 TB1 TB2 TB1 T2 TH1 TAH1 CLKOUT A25 to A5 A4 to A0 CSn R/W RD *2 D31 to D0 (In reading) BS RDY DACKn *1 Notes: 1. 2. In this example, DACKn is active-high. When RDSPL in CSnBCR is set to 1. Figure 11.14 Burst ROM Wait Timing Rev.1.00 Jan.
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11. Local Bus State Controller (LBSC) 11.5.5 PCMCIA Interface By setting the TYPE bits in CS5BCR and CS6BCR, the bus interface for the external space areas 5 and 6 can be set to the IC memory card interface or I/O card interface, which is stipulated in JEIDA specification version 4.2 (PCMCIA 2.1). Figure 11.15 shows the connection example of this LSI and PCMCIA card.
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11. Local Bus State Controller (LBSC) complement mode. To access the Device Control Register and Alternate Status Register, use a CPU byte access (do not use a DMA transfer), and to access the Data Register, use the CPU word access (do not use a DMA transfer). To access the Data Port use a DMA transfer. When a CPU byte access is executed, CE1x is negated and CE2x is asserted (x = A, B). When a CPU word access is executed, CE1x is asserted and CE2x is negated.
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11. Local Bus State Controller (LBSC) Table 11.
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11.
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11. Local Bus State Controller (LBSC) A25 to A0 A25 to A0 G D15 to D0 D7 to D0 R/W CE1B/(CS6) D15 to D0 CE1A/(CS5) G DIR CE2B D15 to D8 CE2A PC card (memory I/O) G DIR SH7785 CE1 CE2 OE RD WE/PGM (IORD) WE1 ICIORD ICIOWR (IOWR) G REG REG WAIT RDY IOIS16 (IOIS6) Card detection circuit CD1, CD2 A25 to A0 G D7 to D0 D15 to D0 G DIR D15 to D8 PC card (memory I/O) G DIR CE1 CE2 OE WE/PGM G REG WAIT Card detection circuit Figure 11.16 Example of PCMCIA Interface Rev.1.00 Jan.
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11. Local Bus State Controller (LBSC) (1) Memory Card Interface Basic Timing Figure 11.17 shows the basic timing for the PCMCIA memory card interface, and figure 11.18 shows the wait timing for the PCMCIA memory card interface. Tpcm1 Tpcm2 CLKOUT A25 to A0 CExx REG R/W RD (In reading) D15 to D0 (In reading) WE1 (In writing) D15 to D0 (In writing) BS DACKn (DA) In this example, DACKn is active-high. Figure 11.17 Basic Timing for PCMCIA Memory Card Interface Rev.1.00 Jan.
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11. Local Bus State Controller (LBSC) Tpcm0 Tpcm0w Tpcm1 Tpcm1w Tpcm1w Tpcm2 Tpcm2w CLKOUT A25 to A0 CExx REG R/W RD (In reading) D15 to D0 (In reading) WE1 (In writing) D15 to D0 (In writing) BS RDY DACKn In this example, DACKn is active-high. Figure 11.18 Wait Timing for PCMCIA Memory Card Interface Rev.1.00 Jan.
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11. Local Bus State Controller (LBSC) (2) I/O Card Interface Timing Figures 11.19 and 11.20 show the timing for the PCMCIA I/O card interface. When a PCMCIA card is accessed as the I/O card interface, dynamic sizing with the I/O bus width can be performed using the IOIS16 pin. With the 16-bit bus width selected, if the IOIS16 signal is high during the word-size I/O bus cycle, the I/O port is recognized as eight bits in bus width.
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11. Local Bus State Controller (LBSC) Tpci1 Tpci2 CLKOUT A25 to A0 CExx REG R/W ICIORD (In reading) D15 to D0 (In reading) ICIOWR (In writing) D15 to D0 (In writing) BS DACKn In this example, DACKn is active-high. Figure 11.19 Basic Timing for PCMCIA I/O Card Interface Rev.1.00 Jan.
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11. Local Bus State Controller (LBSC) Tpci0 Tpci0w Tpci1 Tpci1w Tpci1w Tpci2 Tpci2w CLKOUT A25 to A0 CExx REG R/W ICIORD (In reading) D15 to D0 (In reading) ICIOWR (In writing) D15 to D0 (In writing) BS RDY IOIS16 DACKn In this example, DACKn is active-high. Figure 11.20 Wait Timing for PCMCIA I/O Card Interface Rev.1.00 Jan.
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11. Local Bus State Controller (LBSC) Tpci0 Tpci Tpci1w Tpci2 Tpci2w Tpci0 Tpci Tpci1w Tpci2 Tpci2w CLKOUT A25 to A1 A0 CExx REG R/W IORD (WE2) (In reading) D15 to D0 (In reading) IOWR (WE3) (In writing) D15 to D0 (In writing) BS RDY IOIS16 DACKn In this example, DACKn is active-high. Figure 11.21 Dynamic Bus Sizing Timing for PCMCIA I/O Card Interface Rev.1.00 Jan.
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11. Local Bus State Controller (LBSC) 11.5.6 MPX Interface When both the MODE 7 pin is set to 0 at a power-on reset by the PRESET pin, the MPX interface is selected for area 0. The MPX interface is selected for areas 1 to 6 by the MPX bit in CS1BCR, CS2BCR, and CS4BCR to CS6BCR. The MPX interface provides an address/data multiplex-type bus protocol and facilitates connection with external memory controller chips using an address/data multiplex-type 64- or 32-bit single bus.
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11. Local Bus State Controller (LBSC) SH7785 CLKOUT CSn BS RD R/W D31 to D0 RDY MPX device CLK CS BS FRAME WE I/O31 to I/O0 RDY Figure 11.22 Example of 32-Bit Data Width MPX Connection SH7785 CLKOUT CSn BS RD RD/WR D63 to D0 RDY MPX device CLK CS BS FRAME WE I/O63 to I/O0 RDY Figure 11.23 Example of 64-Bit Data Width MPX Connection The MPX interface timing is shown below. When the MPX interface is used for area 0, the bus size should be set to 64 or 32 bits by MODE5 and MODE6.
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11. Local Bus State Controller (LBSC) Tmd1w Tm1 Tmd1 Tm1 CLKOUT RD/FRAME D63 to D0 A D0 A CSn R/W RDY BS DACK Figure 11.24 MPX Interface Timing 1 (Single Read Cycle, IW = 0000, No External Wait, 64-Bit Bus Width) Rev.1.00 Jan.
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11. Local Bus State Controller (LBSC) Tm1 Tmd1w Tmd1w Tmd1 CLKOUT RD/FRAME D63 to D0 A D0 CSn R/W RDY BS DACKn In this example, DACKn is active-high. The circles indicate the sampling timing. Figure 11.25 MPX Interface Timing 2 (Single Read, IW = 0000, One External Wait Inserted, 64-Bit Bus Width) Rev.1.00 Jan.
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11. Local Bus State Controller (LBSC) Tm1 Tmd1 CLKOUT RD/FRAME D63 to D0 A D0 CSn R/W RDY BS DACKn In this example, DACKn is active-high. The circle indicates the sampling timing. Figure 11.26 MPX Interface Timing 3 (Single Write Cycle, IW = 0000, No External Wait, 64-Bit Bus Width) Rev.1.00 Jan.
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11. Local Bus State Controller (LBSC) Tm1 Tmd1w Tmd1w Tmd1 CLKOUT RD/FRAME D63 to D0 A D0 CSn R/W RDY BS DACKn In this example, DACKn is active-high. Figure 11.27 MPX Interface Timing 4 (Single Write Cycle, IW = 0001, One External Wait Inserted, 64-Bit Bus Width) Rev.1.00 Jan.
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11. Local Bus State Controller (LBSC) Tm1 Tmd1w Tmd1 Tmd2 Tmd3 Tmd4 CLKOUT RD/FRAME D63 to D0 A D0 D1 D2 D3 CSn R/W RDY BS DACKn In this example, DACKn is active-high. Figure 11.28 MPX Interface Timing 5 (Burst Read Cycle, IW = 0000, No External Wait, 64-Bit Bus Width, 32-Byte Data Transfer) Rev.1.00 Jan.
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11. Local Bus State Controller (LBSC) Tm1 Tmd1w Tmd1 Tmd2w Tmd2 Tmd3 Tmd4w Tmd4 CLKOUT RD/FRAME D63 to D0 A D0 D1 D2 D3 CSn R/W RDY BS DACKn In this example, DACKn is active-high. Figure 11.29 MPX Interface Timing 6 (Burst Read Cycle, IW = 0000, External Wait Control, 64-Bit Bus Width, 32-Byte Data Transfer) Rev.1.00 Jan.
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11. Local Bus State Controller (LBSC) Tm1 Tmd1 Tmd2 Tmd3 Tmd4 CLKOUT RD/FRAME D63 to D0 A D0 D1 D2 D3 CSn R/W RDY BS DACKn In this example, DACKn is active-high. Figure 11.30 MPX Interface Timing 7 (Burst Write Cycle, IW = 0000, No External Wait, 64-Bit Width, 32-Byte Data Transfer) Rev.1.00 Jan.
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11. Local Bus State Controller (LBSC) Tm1 Tmd1w Tmd1 Tmd2w Tmd2 Tmd3 Tmd4w Tmd4 CLKOUT RD/FRAME D63 to D0 A D0 D1 D2 D3 CSn R/W RDY BS DACKn In this example, DACKn is active-high. Figure 11.31 MPX Interface Timing 8 (Burst Write Cycle, IW = 0001, External Wait Control, 32-Bit Bus Width, 32-Byte Data Transfer) Rev.1.00 Jan.
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11. Local Bus State Controller (LBSC) Tm1 Tmd1w Tmd1 Tmd2 Tmd3 Tmd4 Tmd5 Tmd6 Tmd7 Tmd8 CLKOUT RD/FRAME D31 to D0 A D1 D2 D3 D4 D5 D6 D7 D8 CSn R/W RDY BS DACKn In this example, DACKn is active-high. Figure 11.32 MPX Interface Timing 9 (Burst Read Cycle, IW = 0000, No External Wait, 32-Bit Bus Width, 32-Byte Data Transfer) Rev.1.00 Jan.
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11. Local Bus State Controller (LBSC) Tm1 Tmd1w Tmd1 Tmd2w Tmd2 Tmd3 Tmd7 Tmd8w Tmd8 CLKOUT RD/FRAME D31 to D0 A D1 D2 D3 D7 CSn R/W RDY BS DACKn In this example, DACKn is active-high. Figure 11.33 MPX Interface Timing 10 (Burst Read Cycle, IW = 0000, External Wait Control, 32-Bit Bus Width, 32-Byte Data Transfer) Rev.1.00 Jan.
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11. Local Bus State Controller (LBSC) Tm1 Tmd1 Tmd2 Tmd3 Tmd4 Tmd5 Tmd6 Tmd7 Tmd8 CLKOUT RD/FRAME D31 to D0 A D1 D2 D3 D4 D5 D6 D7 D8 CSn R/W RDY BS DACKn In this example, DACKn is active-high. Figure 11.34 MPX Interface Timing 11 (Burst Write Cycle, IW = 0000, No External Wait, 32-Bit Bus Width, 32-Byte Data Transfer) Rev.1.00 Jan.
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11. Local Bus State Controller (LBSC) Tm1 Tmd1w Tmd1 Tmd2w Tmd2 Tmd3 Tmd7 Tmd8w Tmd8 CLKOUT RD/FRAME D31 to D0 A D1 D2 D3 D7 D8 CSn R/W RDY BS DACKn In this example, DACKn is active-high. Figure 11.35 MPX Interface Timing 12 (Burst Write Cycle, IW = 0001, External Wait Control, 32-Bit Bus Width, 32-Byte Data Transfer) Rev.1.00 Jan.
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11. Local Bus State Controller (LBSC) 11.5.7 Byte Control SRAM Interface The byte control SRAM interface is a memory interface that outputs a byte-select strobe (WEn) in both read and write bus cycles. This interface has 16-bit data pins and can be connected to SRAM having an upper byte select strobe and lower select strobe functions such as UB and LB. Areas 1 and 4 can be specified as a byte control SRAM interface.
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11. Local Bus State Controller (LBSC) SH7785 A18 to A3 CSn RD R/W 64K × 16 bits SRAM D63 to D48 WE7 WE6 A15 to A0 CS OE WE I/O15 to I/O0 UB LB D47 to D32 WE5 WE4 A15 to A0 CS OE WE I/O15 to I/O0 UB LB D31 to D16 WE3 WE2 A15 to A0 CS OE WE I/O15 to /O0 UB LB D15 to D0 WE1 WE0 A15 to A0 CS OE WE I/O15 to I/O0 UB LB Figure 11.37 Example of Byte Control SRAM with 64-Bit Data Width Rev.1.00 Jan.
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11. Local Bus State Controller (LBSC) T1 T2 CLKOUT A25 to A0 CSn R/W RD D31 to D0 (In reading) WEn BS RDY DACKn In this example, DACKn is active-high. Figure 11.38 Basic Read Cycle of Byte Control SRAM (No Wait) Rev.1.00 Jan.
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11.
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11. Local Bus State Controller (LBSC) T1 Tw Twe T2 CLKOUT A25 to A0 CSn R/W RD D31 to D0 (In reading) WEn BS RDY DACKn In this example, DACKn is active-high. Figure 11.40 Wait State Timing of Byte Control SRAM (One Internal Wait + One External Wait) Rev.1.00 Jan.
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11. Local Bus State Controller (LBSC) 11.5.8 Wait Cycles between Access Cycles When the external memory bus operating frequency is high, the turn-off of the data buffer performed on completion of reading from a low-speed device may not be made in time. This cause a collision with the next access data or a malfunction, which results in lower reliability. To prevent this problem, the data collision prevention function is provided.
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11. Local Bus State Controller (LBSC) T1 T2 Twait T1 T2 Twait T1 T2 CLKOUT A25 to A0 CSm CSn BS R/W RD D31 to D0 Reading area m space Reading area n space CSnBCR.IWRRD=001 Writing area n space CSnBCR.IWRWS=001 Figure 11.41 Wait Cycles between Access Cycles (Access Size Is 4 Bytes) Rev.1.00 Jan.
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11. Local Bus State Controller (LBSC) 11.5.9 Bus Arbitration This LSI is provided with a bus arbitration function that gives the bus to an external device when a request is issued from the device. This bus arbitration supports master mode and slave mode. In master mode the bus is held on a steady state, and is released to another device in response to a bus request. In slave mode, the bus is not held in the steady state.
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11.
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11. Local Bus State Controller (LBSC) 11.5.10 Master Mode The processor in master mode holds the bus itself until it receives a bus request. On receiving an assertion (low level) of the bus request signal (BREQ) from the outside, the master mode processor releases the bus and asserts (drives low) the bus use permission signal (BACK) as soon as the currently executing bus cycle ends.
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11. Local Bus State Controller (LBSC) 11.5.11 Slave Mode In slave mode, usually, the bus is released. Unless the bus control is hold by performing bus arbitration, the external device cannot be accessed. The bus is released at a reset, and the bus arbitration sequence starts from the fetch of the reset vector. To get the bus mastership, the BSREQ signal is asserted (driven low) in synchronous with the rising edge of the clock.
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11. Local Bus State Controller (LBSC) 11.5.14 Mode Pin Settings and General Input Output Port Settings about Data Bus Width Table 11.18 shows the examples of MODE pin settings and port settings (GPIO port control register) related to the selection of the data bus width used in the local bus. Table 11.
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11. Local Bus State Controller (LBSC) Table 11.19 Register Settings for Divided-Up DACKn Output in DMA1 Transfer Using the SRAM/Burst ROM/Byte Control SRAM Interfaces Not Divided Bus Width Access Size in [Bit] DMA Transfer 8 16 32 64 Divided Bus Cycle Number IWRRD, IWRRS, or ADS and ADH in ADS and ADH IWW in CSnBCR CSnWCR.
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11. Local Bus State Controller (LBSC) Table 11.
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11. Local Bus State Controller (LBSC) Table 11.
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11. Local Bus State Controller (LBSC) Table 11.
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12. DDR2-SDRAM Interface (DBSC2) Section 12 DDR2-SDRAM Interface (DBSC2) The DDR2-SDRAM interface (DBSC2) controls the DDR2-SDRAM. 12.
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12.
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12. DDR2-SDRAM Interface (DBSC2) Figure 12.1 shows a block diagram of the DBSC2.
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12. DDR2-SDRAM Interface (DBSC2) 12.2 Input/Output Pins Table 12.1 shows the pin configuration of the DBSC2. Table 12.
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12. DDR2-SDRAM Interface (DBSC2) The frequency of the SDRAM operation clocks MCK0, MCK0, MCK1, and MCK1 is the same as the frequency of the DDR clock. MDQ7 to MDQ0 correspond to MDQS0 and MDM0, MDQ15 to MDQ8 correspond to MDQS1 and MDM1, MDQ23 to MDQ16 correspond to MDQS2 and MDM2, and MDQ31 to MDQ24 correspond to MDQS3 and MDM3. When the external data bus width is 16 bits, MDQ15 to MDQ0 are used. Table 12.
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12. DDR2-SDRAM Interface (DBSC2) Table 12.
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12. DDR2-SDRAM Interface (DBSC2) 3. SDRAM pins should be connected as shown below. Memory #1 Pins SH7785 Pins DQS MDQS3 DQS MDQS3 DM MDM3 DQ7 MDQ31 DQ6 MDQ30 DQ5 MDQ29 DQ4 MDQ28 DQ3 MDQ27 DQ2 MDQ26 DQ1 MDQ25 DQ0 MDQ24 4. SDRAM pins should be connected as shown below. Memory #2 Pins SH7785 Pins DQS MDQS2 DQS MDQS2 DM MDM2 DQ7 MDQ23 DQ6 MDQ22 DQ5 MDQ21 DQ4 MDQ20 DQ3 MDQ19 DQ2 MDQ18 DQ1 MDQ17 DQ0 MDQ16 Rev.1.00 Jan.
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12. DDR2-SDRAM Interface (DBSC2) 5. SDRAM pins should be connected as shown below. Memory #3 Pins SH7785 Pins DQS MDQS1 DQS MDQS1 DM MDM1 DQ7 MDQ15 DQ6 MDQ14 DQ5 MDQ13 DQ4 MDQ12 DQ3 MDQ11 DQ2 MDQ10 DQ1 MDQ9 DQ0 MDQ8 6. SDRAM pins should be connected as shown below. Memory #4 Pins SH7785 Pins DQS MDQS0 DQS MDQS0 DM MDM0 DQ7 MDQ7 DQ6 MDQ6 DQ5 MDQ5 DQ4 MDQ4 DQ3 MDQ3 DQ2 MDQ2 DQ1 MDQ1 DQ0 MDQ0 Rev.1.00 Jan.
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12. DDR2-SDRAM Interface (DBSC2) 12.3 Data Alignment The DBSC2 accesses DDR2-SDRAM with a fixed burst length of 4 (figure 12.2). As shown in table 12.3 and table 12.4, invalid read data is discarded during reading, and data mask signals are used to mask invalid data during writing, according to the access size. The access times in tables 12.3 and 12.4 correspond to the burst times during reading/writing shown in figure 12.2.
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12.
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12. DDR2-SDRAM Interface (DBSC2) Table 12.
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12. DDR2-SDRAM Interface (DBSC2) Table 12.
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12.
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12. DDR2-SDRAM Interface (DBSC2) Table 12.
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12. DDR2-SDRAM Interface (DBSC2) Access Size Address MDQ31 to MDQ24 MDQ23 to MDQ16 MDQ15 to MDQ8 MDQ7 to MDQ0 Quadword Address 0 Data Data Data Data (First access: address 4) 63 to 56 55 to 48 47 to 40 39 to 32 Address 0 Data Data Data Data (Second access: Address 0) 31 to 24 23 to 16 15 to 8 7 to 0 Table 12.
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12.
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12. DDR2-SDRAM Interface (DBSC2) Table 12.
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12.
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12. DDR2-SDRAM Interface (DBSC2) Table 12.
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12.
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12.
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12.
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12. DDR2-SDRAM Interface (DBSC2) 12.4 Register Descriptions Table 12.9 shows the DBSC2 register configuration; Table 12.10 shows register states in the different processing modes. The register bit width is 32 bits, and the longword size (32 bits) should be used for register access. If registers are accessed with sizes other than the longword size, correct operation cannot be guaranteed.
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12. DDR2-SDRAM Interface (DBSC2) Table 12.
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12. DDR2-SDRAM Interface (DBSC2) Table 12.
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12. DDR2-SDRAM Interface (DBSC2) 12.4.1 DBSC2 Status Register (DBSTATE) The DBSC2 status register (DBSTATE) is a read-only register. Writing is invalid. It is initialized only upon power-on reset.
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12. DDR2-SDRAM Interface (DBSC2) 12.4.2 SDRAM Operation Enable Register (DBEN) The SDRAM operation enable register (DBEN) is a readable/writable register. It is initialized only upon power-on reset.
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12. DDR2-SDRAM Interface (DBSC2) 12.4.3 SDRAM Command Control Register (DBCMDCNT) The SDRAM command control register (DBCMDCNT) is a readable/writable register. It is initialized only upon power-on reset. The CMD2 to CMD0 bits in DBCMDCNT are always read as 000.
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12. DDR2-SDRAM Interface (DBSC2) Bit Bit Name 2 to 0 CMD2 to CMD0 Initial Value R/W Description 000 R/W SDRAM Command Issue Bit These bits are used to issue commands necessary to execute the DDR2-SDRAM initialization sequence and self-refresh transition/cancellation. When these bits are written, the command corresponding to the written value is issued once. For example, in order to issue the autorefresh command twice, it would be necessary to write 100 to these bits twice.
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12. DDR2-SDRAM Interface (DBSC2) 12.4.4 SDRAM Configuration Setting Register (DBCONF) The SDRAM configuration setting register (DBCONF) is a readable/writable register. It is initialized only upon power-on reset.
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12. DDR2-SDRAM Interface (DBSC2) Bit Bit Name 15 to 10 ⎯ Initial Value R/W Description All 0 R Reserved These bits are always read as 0. The write value should always be 0. Operation when a value other than 0 is written is not guaranteed. 9, 8 BASFT1 and BASFT0 00 R/W Bank Address Shift Bits These bits select the amount of shifting downward of the bank address. 00: No shift 01: Shift the bank address downward 1 bit. 10: Shift the bank address downward 2 bits.
PAGE 518
12. DDR2-SDRAM Interface (DBSC2) 12.4.5 SDRAM Timing Register 0 (DBTR0) The SDRAM timing register 0 (DBTR0) is a readable/writable register. It is initialized only upon power-on reset.
PAGE 519
12. DDR2-SDRAM Interface (DBSC2) Bit Bit Name 23 to 20 ⎯ Initial Value R/W Description All 0 R Reserved These bits are always read as 0. The write value should always be 0. Operation when a value other than 0 is written is not guaranteed. 19 to 16 TRAS3 to TRAS0 0011 R/W tRAS (ACT-PRE period) Setting Bits These bits set the ACT-PRE minimum period constraint for the same bank. These bits should be set according to the DDR2-SDRAM specifications.
PAGE 520
12. DDR2-SDRAM Interface (DBSC2) Bit Bit Name 14 to 8 TRFC6 to TRFC0 Initial Value R/W Description 000 0101 R/W tRFC (REF-ACT/REF period) Setting Bits These bits set the REF-ACT/REF minimum period constraint These bits should be set according to the DDR2-SDRAM specifications. The number of cycles is the number of DDR clock cycles. 000 0000: Setting prohibit (If specified, correct operation cannot be guaranteed.) : 000 0100: Setting prohibit (If specified, correct operation cannot be guaranteed.
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12. DDR2-SDRAM Interface (DBSC2) Bit Bit Name 2 to 0 TRCD2 to TRCD0 Initial Value R/W Description 001 R/W tRCD (ACT-READ/WRITE period) Setting Bits These bits set the ACT-READ/WRITE minimum period. These bits should be set according to the DDR2SDRAM specifications. The number of cycles is the number of DDR clock cycles. 000: Setting prohibit (If specified, correct operation cannot be guaranteed.
PAGE 522
12. DDR2-SDRAM Interface (DBSC2) 12.4.6 SDRAM Timing Register 1 (DBTR1) The SDRAM timing register 1 (DBTR1) is a readable/writable register. It is initialized only upon power-on reset.
PAGE 523
12. DDR2-SDRAM Interface (DBSC2) Bit Bit Name 15 to 11 ⎯ Initial Value R/W Description All 0 R Reserved These bits are always read as 0. The write value should always be 0. Operation when a value other than 0 is written is not guaranteed. 10 to 8 TRRD2 to TRRD0 000 R/W tRRD (ACT(A)-ACT(B) period) Setting Bits These bits set the ACT-ACT minimum period constraint for the different banks. These bits should be set according to the DDR2-SDRAM specifications.
PAGE 524
12. DDR2-SDRAM Interface (DBSC2) Bit Bit Name 2 to 0 TWR2 to TWR0 Initial Value R/W Description 001 R/W tWR (write recovery period) Setting Bits These bits set the write recovery minimum period constraint. These bits should be set according to the DDR2-SDRAM specifications. The number of cycles is the number of DDR clock cycles. 000: Setting prohibit (If specified, correct operation cannot be guaranteed.
PAGE 525
12. DDR2-SDRAM Interface (DBSC2) 12.4.7 SDRAM Timing Register 2 (DBTR2) The SDRAM timing register 2 (DBTR2) is a readable/writable register. It is initialized only upon power-on reset.
PAGE 526
12. DDR2-SDRAM Interface (DBSC2) Bit Bit Name 20 to 16 TRC4 to TRC0 Initial Value R/W Description 0 0100 R/W tRC (ACT-ACT/REF period) Setting Bits These bits set the constraint for the minimum time from ACT command to ACT command (in the same bank)/ REF command. These bits should be set according to the SDRAM specifications. The number of cycles is the number of DDR clock cycles. 00000: Setting prohibit (If specified, correct operation cannot be guaranteed.
PAGE 527
12. DDR2-SDRAM Interface (DBSC2) Bit Bit Name 11 to 8 RDWR3 to RDWR0 Initial Value R/W Description 0011 R/W READ-WRITE Command Minimum Interval Setting Bits These bits set the READ-WRITE command minimum interval constraint. These bits should be set according to the SDRAM specifications. The number of cycles is the number of DDR clock cycles. 0000: Setting prohibit (If specified, correct operation cannot be guaranteed.) : 0010: Setting prohibit (If specified, correct operation cannot be guaranteed.
PAGE 528
12. DDR2-SDRAM Interface (DBSC2) Bit Bit Name 3 to 0 WRRD3 to WRRD0 Initial Value R/W Description 0011 R/W WRITE-READ Command Minimum Interval Setting Bits These bits set the WRITE-READ command minimum interval constraint. These bits should be set according to the SDRAM specifications. The number of cycles is the number of DDR clock cycles. 0000: Setting prohibit (If specified, correct operation cannot be guaranteed.) : 0010: Setting prohibit (If specified, correct operation cannot be guaranteed.
PAGE 529
12. DDR2-SDRAM Interface (DBSC2) 12.4.8 SDRAM Refresh Control Register 0 (DBRFCNT0) The SDRAM refresh control register 0 (DBRFCNT0) is a readable/writable register. It is initialized only upon power-on reset.
PAGE 530
12. DDR2-SDRAM Interface (DBSC2) Bit Bit Name Initial Value R/W Description 0 SRFEN 0 R/W Self-Refresh Mode Bit Performs transition to or cancellation of self-refresh mode. By writing 1, a transition is made to self-refresh. By writing 0, self-refresh mode is cancelled. For details on transition to or cancellation of self-refresh, refer to section 12.5.4, Self-Refresh Operation. 0: Cancels self-refresh. 1: Makes a transition to self-refresh. 12.4.
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12. DDR2-SDRAM Interface (DBSC2) Initial Value Bit Bit Name R/W 12 to 0 TREFI12 to 0 0010 R/W TREFI0 0000 0000 Description Average Refresh Interval Setting Bits These bits set the average interval for auto-refresh operation. Upon refresh execution, this value is added to the refresh interval count register. The number of cycles is the number of DDR clock cycles. 0 0000 0000 0000: Setting prohibited (If specified, correct operation cannot be guaranteed.
PAGE 532
12. DDR2-SDRAM Interface (DBSC2) 12.4.10 SDRAM Refresh Control Register 2 (DBRFCNT2) The SDRAM refresh control register 2 (DBRFCNT2) is a readable/writable register. It is initialized only upon power-on reset.
PAGE 533
12. DDR2-SDRAM Interface (DBSC2) Bit Bit Name Initial Value R/W Description 15 to 8 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0. Operation when a value other than 0 is written is not guaranteed. 7 to 0 LV0TH7 to LV0TH0 1000 0000 R/W Level 0 Threshold Setting Bits These bits set the threshold cycles for executing autorefresh. The number of cycles is the number of DDR clock cycles.
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12. DDR2-SDRAM Interface (DBSC2) 12.4.11 SDRAM Refresh Status Register (DBRFSTS) The SDRAM refresh status register (DBRFSTS) is a readable/writable register. It is initialized only upon power-on reset.
PAGE 535
12. DDR2-SDRAM Interface (DBSC2) 12.4.12 DDRPAD Frequency Setting Register (DBFREQ) The DDRPAD frequency setting register (DBFREQ) is a readable/writable register. It is initialized only upon power-on reset.
PAGE 536
12. DDR2-SDRAM Interface (DBSC2) Bit Bit Name 2 to 0 FREQ2 to FREQ0 Initial Value R/W Description 000 R/W Frequency Setting Bits These bits set the operating frequency of the data bus in the DDR2-SDRAM. 000: up to 300 MHz (DDR2-600) 001: Reserved 010: 200 MHz (DDR2-400) 100 to 111: Setting prohibited. (If specified, correct operation cannot be guaranteed.) Note: This register is used for initialization, when canceling self-refresh, and when canceling power supply backup.
PAGE 537
12. DDR2-SDRAM Interface (DBSC2) 12.4.13 DDRPAD DIC, ODT, OCD Setting Register (DBDICODTOCD) The SDRAM refresh status register (DBRFSTS) is a readable/writable register. It is initialized only upon power-on reset.
PAGE 538
12. DDR2-SDRAM Interface (DBSC2) Bit Bit Name Initial Value R/W Description 18 DIC_DQ 0 R/W Data Pin Impedance value This bit should be set to the same value as the value set for DIC of EMRS(1) in the DDR2-SDRAM. 0: Normal 1: Weak 17 DIC_CK 0 R/W Clock Pin Impedance value This bit should be set to the same value as the value set for DIC of EMRS(1) in the DDR2-SDRAM.
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12. DDR2-SDRAM Interface (DBSC2) Bit Bit Name 10 ODT_ EARLY Initial Value R/W Description 0 R/W ODT Assertion Period Setting Sets the ODT assertion period. The number of cycles is the number of DDR clock cycles. This setting is valid only when ODTEN is set to 01. In order to extend ODT by 1 cycle using the setting of ODT_EARLY, after setting CL to 5 or higher, the RDWR bits in the DBTR2 register must be set to the value specified in the data sheet for the DDR2-SDRAM, plus 1.
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12. DDR2-SDRAM Interface (DBSC2) 12.4.14 SDRAM Mode Setting Register (DBMRCNT) The SDRAM mode setting register (DBMRCNT) is a write-only register. If it is read, correct operation cannot be guaranteed.
PAGE 541
12. DDR2-SDRAM Interface (DBSC2) By writing to this register, the DDR2-SDRAM address and bank address pins can be directly manipulated to set the mode and extended mode registers. When this register is written, the mode register setting (MRS)/extended mode register setting (EMRS) command is issued for the DDR2SDRAM.
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12. DDR2-SDRAM Interface (DBSC2) 12.5 DBSC2 Operation 12.5.1 Supported SDRAM Commands Table 12.11 lists the SDRAM commands issued by the DBSC2. These commands are issued to the DDR2-SDRAM in synchronously with MCK0, MCK0, MCK1, and MCK1. In the table, n-1 indicates the state of the signal applied to DDR2-SDRAM one cycle before SDRAM command issue; n indicates the state of the signal at the time of command issue. Table 12.
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12. DDR2-SDRAM Interface (DBSC2) 12.5.2 (1) SDRAM Command Issue Basic Access The DBSC2 stores in a queue the requests received via the SuperHyway bus. Request processing is begun around the time of preceding precharge/activate processing, but processing completion is in the order received in the queue. When SDRAM initialization is completed, upon receiving a read/write request, a page miss occurs with all banks in the closed state.
PAGE 544
12.
PAGE 545
12. DDR2-SDRAM Interface (DBSC2) command to be issued at time 2 from the following request queue. From the search results it is seen that advance precharge processing can be executed for the third read (8-byte) request and the fourth read (16-byte) request. Because the DBSC2 gives priority to preceding requests, it decides to perform advance precharge processing for the third read (8-byte) request, and issues a PRE command to the SDRAM.
PAGE 546
12. DDR2-SDRAM Interface (DBSC2) 12.5.3 Initialization Sequence The following shows an example of the initialization sequence. For detailed information such as the power supply and timing parameters, please refer to the datasheet for the DDR2-SDRAM being used. 1. Following the instructions in the datasheet guide for the SDRAM being used, supply the power and the reference voltage. 2.
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12. DDR2-SDRAM Interface (DBSC2) 10. Writing to DBMRCNT issues the MRS command to the SDRAM and sets the various parameters. At this point, the operating mode is set to normal mode, the DLL reset is set to reset, the burst length is set to 4, and the burst type is set to sequential. The additive latency should be set to 0, and CAS latency and write recovery times should be set to match the settings of DBTR0 and DBTR1. 11. Writing to the CMD bits in DBCMDCNT issues the PALL command. 12.
PAGE 548
12. DDR2-SDRAM Interface (DBSC2) Because access is disabled in self-refresh mode, any attempt to access data in the DDR2-SDRAM will be ignored. The following procedure is used to make a transition to self-refresh mode. 1. Check to make sure the DBSC2 is not being accessed. The time required for transition to selfrefresh must not exceed the auto-refresh interval requested by the SDRAM by interrupts or some other causes. 2.
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12. DDR2-SDRAM Interface (DBSC2) 1. Check to make sure the DBSC2 is not being accessed. The time required for transition to selfrefresh must not exceed the auto-refresh interval requested by the SDRAM by interrupts or some other causes. 2. Set the ACEN bit in the SDRAM operation enable register (DBEN) to 0 (access disabled). 3. Set the ARFEN bit in the SDRAM refresh control register 0 (DBRFCNT0) to 0 (automatic issue of auto-refresh disabled). 4.
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12. DDR2-SDRAM Interface (DBSC2) 12.5.5 Auto-Refresh Operation When the auto-refresh enable bit (ARFEN) in the SDRAM refresh control register 0 (DBRFCNT0) is 1, the auto-refresh command is issued periodically. If accessing data in the SDRAM, always make sure this is set. The average refresh interval is set in the TREFI bits in the SDRAM refresh control register 1 (DBRFCNT1).
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12. DDR2-SDRAM Interface (DBSC2) Refresh counter value Max.
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12. DDR2-SDRAM Interface (DBSC2) Table 12.
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12. DDR2-SDRAM Interface (DBSC2) Table 12.
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12. DDR2-SDRAM Interface (DBSC2) Table 12.
PAGE 555
12. DDR2-SDRAM Interface (DBSC2) Table 12.
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12. DDR2-SDRAM Interface (DBSC2) Table 12.
PAGE 557
12. DDR2-SDRAM Interface (DBSC2) Table 12.
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12. DDR2-SDRAM Interface (DBSC2) Table 12.
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12. DDR2-SDRAM Interface (DBSC2) Table 12.
PAGE 560
12. DDR2-SDRAM Interface (DBSC2) 12.5.7 Regarding SDRAM Access and Timing Constraints In this section, waveforms at the various pins during basic DDR2-SDRAM access are explained first and then the relation between DDR2-SDRAM access and the CAS latency (CL), tRAS, tRFC, tRCD, tRP, tRRD, tWR, tRTP, tRC, READ-WRITE minimum interval, WRITE-READ minimum interval set using the SDRAM timing registers 0 to 2 (DBTR0 to DBTR2) is explained.
PAGE 561
12. DDR2-SDRAM Interface (DBSC2) MCK0, MCK1 High level MCKE MCS MRAS MCAS MWE MA[14:11] MA[9:0] Valid Invalid Valid Invalid MA[10] Valid Invalid Valid Invalid MBA[2:0] Valid Invalid Valid Invalid Example of CL = 3 MDQS[3:0] MDM[3:0] Invalid MDQ[31:0] Invalid Invalid Read data SDRAM ACT command bank A READ bank A Figure 12.8 Waveforms for 1/2/4/8/16-Byte Reading (When the Bus Width Is Set to 32 Bits) Figure 12.9 shows waveforms for 32-byte reading when the bus width is set to 32 bits.
PAGE 562
12. DDR2-SDRAM Interface (DBSC2) MCK0, MCK1 High level MCKE MCS MRAS MCAS MWE MA[14:11 ] MA[9:0] Valid Invalid Valid Invalid Valid Invalid MA[10] Valid Invalid Valid Invalid Valid Invalid MBA[2:0] Valid Invalid Valid Invalid Valid Invalid Example of CL = 3 MDQS[3:0] MDM[3:0] Invalid MDQ[31:0] Invalid Invalid Read data SDRAM ACT command bank A READ bank A READ bank A Figure 12.9 Waveforms for 32-Byte Reading (When the Bus Width Is Set to 32 Bits) Figure 12.
PAGE 563
12. DDR2-SDRAM Interface (DBSC2) MCK0, MCK1 High level MCKE MCS MRAS MCAS MWE MA[14:11] MA[9:0] Valid Invalid Valid Invalid MA[10] Valid Invalid Valid Invalid MBA[2:0] Valid Invalid Valid Invalid Example of CL = 3 MDQS[3:0] MDM[3:0] Invalid Invalid MDQ[31:0] Invalid Invalid Write data SDRAM ACT command bank A WRITE bank A Figure 12.10 Waveforms for 1/2/4/8/16-Byte Writing (When the Bus Width Is Set to 32 Bits) Figure 12.
PAGE 564
12. DDR2-SDRAM Interface (DBSC2) MCK0, MCK1 High level MCKE MCS MRAS MCAS MWE MA[14:11] MA[9:0] Valid Invalid Valid Invalid Valid Invalid MA[10] Valid Invalid Valid Invalid Valid Invalid MBA[2:0] Valid Invalid Valid Invalid Valid Invalid Example of CL = 3 MDQS[3:0] MDM[3:0] Invalid MDQ[31:0] Invalid Invalid Invalid Write data SDRAM ACT command bank A WRITE bank A WRITE bank A Figure 12.11 Waveforms for 32-Byte Writing (When the Bus Width Is Set to 32 Bits) Figure 12.
PAGE 565
12. DDR2-SDRAM Interface (DBSC2) MCK0, MCK1 High level MCKE MCS MRAS MCAS MWE MA[14:11] MA[9:0] MA[10] Invalid Invalid Invalid MBA[2:0] Invalid MDQS[3:0] MDM[3:0] Invalid MDQ[31:0] Invalid SDRAM command PALL REF Figure 12.12 Auto-Refresh Operation Figure 12.13 shows the self-refresh operation. In order to perform self-refresh operation, the sequence must be observed. For details, refer to section 12.5.4, Self-Refresh Operation.
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12. DDR2-SDRAM Interface (DBSC2) example is shown in section 12.5.11, Method for Securing Time Required for Initialization, SelfRefresh Cancellation, etc. MCK0, MCK1 MCKE MCS MRAS MCAS MWE MA[14:11] MA[9:0] MA[10] Invalid Invalid Invalid MBA[2:0] Invalid Self-refresh in progress tXSNR MDQS[3:0] MDM[3:0] Invalid MDQ[31:0] Invalid SDRAM command REF PALL SLFRSH SLF RSHX REF Figure 12.13 Self-Refresh Operation (2) Regarding Timing Constraints Figure 12.
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12. DDR2-SDRAM Interface (DBSC2) command, the constraint tRCD between the ACT command and READ command, and the constraint tRAS between the ACT command and the PRE command are involved. The DBSC2 waits to issue commands until each of the constraints is satisfied.
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12.
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12. DDR2-SDRAM Interface (DBSC2) MCK0, MCK1 High level MCKE MCS MRAS MCAS MWE MA[14:11] MA[9:0] Valid MA[10] Valid Invalid MBA[2:0] Valid Invalid Valid Invalid Valid Invalid Valid Invalid Valid Invalid Valid Invalid Valid Invalid Valid Example of CL = 3 tWR = 3 cycles MDQS[3:0] MDM[3:0] Invalid MDQ[31:0] Invalid Invalid Invalid Write data SDRAM WRITE command bank A PRE bank A ACT bank A WRITE bank A Figure 12.16 tWR Figure 12.
PAGE 570
12. DDR2-SDRAM Interface (DBSC2) MCK0, MCK1 High level MCKE MCS MRAS MCAS MWE MA[14:11] MA[9:0] Valid Invalid Valid MA[10] Valid Invalid Valid MBA[2:0] Valid Invalid Valid Invalid Invalid Invalid Invalid tRP = 3 cycles tRAS = 9 cycles tRC = 12 cycles Example of CL = 3 MDQS[3:0] MDM[3:0] Invalid MDQ[31:0] Invalid Invalid Read data SDRAM ACT command bank A READ bank A PALL REF Figure 12.17 tRC Figure 12.
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12. DDR2-SDRAM Interface (DBSC2) MCK0, MCK1 High level MCKE MCS MRAS MCAS MWE MA[14:11] MA[9:0] Valid Invalid Valid Invalid MA[10] Valid Invalid Valid Invalid MBA[2:0] Valid Invalid Valid Invalid RDWR = 4 cycles Example of CL = 3 MDQS[3:0] MDM[3:0] Invalid MDQ[31:0] Invalid Invalid Read data SDRAM READ command any bank Invalid Invalid Write data WRITE any bank Figure 12.18 READ-WRITE Minimum Time Figure 12.
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12. DDR2-SDRAM Interface (DBSC2) MCK0, MCK1 High level MCKE MCS MRAS MCAS MWE MA[14:11] MA[9:0] Valid Invalid Valid Invalid MA[10] Valid Invalid Valid Invalid MBA[2:0] Valid Invalid Valid Invalid Example of CL= 3 WRRD = 7 cycles MDQS[3:0] MDM[3:0] Invalid MDQ[31:0] Invalid Invalid Invalid Write data SDRAM WRITE command any bank Read data READ any bank Figure 12.19 WRITE-READ Minimum Time Figure 12.
PAGE 573
12. DDR2-SDRAM Interface (DBSC2) MCK0, MCK1 MCKE High level MCS MRAS MCAS MWE MA[14:11] MA[9:0] Invalid Valid Invalid Valid Invalid MA[10] Invalid Valid Invalid Valid Invalid MBA[2:0] Invalid Valid Invalid Valid Invalid tRFC = 6 cycles MDQS[3:0] MDM[3:0] Invalid MDQ[31:0] Invalid SDRAM REF command ACT any bank READ any bank Figure 12.20 tRFC Figure 12.20 is an example of a case in which, after issuing a REF command, a READ request is issued.
PAGE 574
12. DDR2-SDRAM Interface (DBSC2) 12.5.8 Important Information Regarding Use of 8-Bank DDR2-SDRAM Products The DDR2-SDRAM specifications limit the number of banks in an 8-bank product which can be activated simultaneously. Control must be executed so that the number of activated banks never exceeds four banks. Hence the DBSC2 handles (BA2,BA1,BA0) = (1,X,Y) and (0,X,Y) as access to the same banks. Through this handling, no more than four banks can be activated simultaneously.
PAGE 575
12. DDR2-SDRAM Interface (DBSC2) MCK High level MCKE Command write 3 cycles for product with CL = 4 Data tAOFD = 2.5 cycles MODT tAOND = 2 cycles Terminating resistor in SDRAM Resistor ON As shown in the above figure, when CL is 4, the effective ODT control signal (MODT) to the SDRAM can be asserted at the same timing as the issue of the WRITE command. If CL is 5 or greater, MODT is asserted after the issue of the WRITE command.
PAGE 576
12. DDR2-SDRAM Interface (DBSC2) MCK Command High level 4 -> 5 cycles MCKE read 5 cycles for product with CL = 5 write 4 cycles for product with CL = 5 Data If the interval from the READ command to the WRITE command is 4 cycles, read data exists on the data bus when Rtt is turned on. Therefore, the interval should be 5 cycles. tAOFD = 2.5 cycles MODT tAOND = 2 cycles Terminating Resistor ON Extended for 1 cycle resistor in SDRAM The above figure shows an example when a product with CL = 5 is used.
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12. DDR2-SDRAM Interface (DBSC2) Normal operation When SDRAM power supply backup function is used This LSI This LSI DBSC2 Data is retained in self-refresh state DBSC2 SDRAM IO cell Internal CKE MCKE Normal operation Internal CKE 1.8-V power on External High level device input Status signal 1.0-V power off Data retained MCKE Low level output MBKPRST 1.0-V power on SDRAM IO cell 1.
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12. DDR2-SDRAM Interface (DBSC2) MCKE to high level, upon power-on reset the data within the SDRAM is destroyed. Hence if the state signal is not set in advance to a state other than power supply backup state, there is the danger that the destroyed data may be treated as the correct data.) In this way, procedures are used to make a transition to and cancel SDRAM power supply backup mode; if these procedures are not followed, the data in the SDRAM may be destroyed. These procedures are explained below.
PAGE 579
12. DDR2-SDRAM Interface (DBSC2) 5. The SDRAM configuration setting register (DBCONF), SDRAM timing register 0 (DBTR0), SDRAM timing register 1 (DBTR1), and SDRAM timing register 2 (DBTR2) should be set. 6. By writing to the DDRPAD frequency setting register DBFREQ, DLL settings are made. A. Set DLLRST = 0. B. Set the FREQ bits to the DDRPAD frequency. C. After setting DLLRST = 1, the software waits for the DLL stabilization time of 100 μs or more required by DDRPAD. 7.
PAGE 580
12. DDR2-SDRAM Interface (DBSC2) 12.5.13 Regarding MCKE Signal Operation The MCKE signal operation is explained using figure 12.24. Here, the explanation assumes that MBKPRST is high-level input. Prior to power-on reset the MCKE signal is indefinite, but upon power-on reset is output at low level. After release of power-on reset, by writing 011 to the CMD bits in the SDRAM command control register (DBCMDCNT), the MCKE signal output is at high level, corresponding to the enable state.
PAGE 581
13. PCI Controller (PCIC) Section 13 PCI Controller (PCIC) The PCI controller (PCIC) controls the PCI bus and enables data transfers between memory connected to an external bus and a PCI device connected to the PCI bus. The PCIC facilitates the system design using the PCI bus and enables short and fast data transfer. The PCIC operates as a bus bridge which links the PCI bus to the internal bus (SuperHyway bus).
PAGE 582
13. PCI Controller (PCIC) • Cache snoop functions are supported when the PCIC is a target (cache coherency can be supported by sacrificing performance). • Supports four external interrupt inputs (INTA, INTB, INTC, and INTD) in host mode • Supports one external interrupt output (INTA) in normal mode • Both big endian and little endian are supported in SH7785 (the PCI bus operates in little endian mode). Note: The following PCI functions are not supported.
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13. PCI Controller (PCIC) Figure 13.1 shows a block diagram of the PCIC.
PAGE 584
13. PCI Controller (PCIC) 13.2 Input/Output Pins Table 13.1 shows the pin configuration of the PCIC. Table 13.1 Signal Descriptions Signal Name PCI Standard Signal I/O Description D32/AD0/DR0 to AD[31:0] D37/AD5/DR5, D38/AD6/DG0 to D43/AD11/DG5, D44/AD12/DB0 to D49/AD17/DB5, D50/AD18 to D63/AD31 TRI PCI Address/Data Bus Address and data buses are multiplexed. In each bus transaction, an address phase is followed by one or more data phases.
PAGE 585
13. PCI Controller (PCIC) Signal Name PCI Standard Signal I/O LOCK/ODDF LOCK STRI PCI Lock Exclusive access (the target resource is locked) is accepted when the PCIC is a target IDSEL IDSEL IN PCI Configuration Device Select Description This signal is input to select the PCIC in configuration cycles (only in normal mode). DEVSEL/ DCLKOUT DEVSEL SCIF0_CTS/ INTD INTD DREQ3/INTC INTC STRI PCI Device Select Indicates the PCIC has decoded the address of the PCI device as the target.
PAGE 586
13. PCI Controller (PCIC) Signal Name MODE12 MODE11 PCI Standard Signal I/O Description — PCI Operating Mode Select IN 00: PCI host mode, or PCI host bridge operation by PCICLK 01: PCI normal mode, or non-PCI host bridge operation by PCICLK 10: Local bus 64-bit mode (the PCI disabled) 11: DU mode (the PCI disabled) Legend: TRI: Tri-state STRI: Sustained tri-state OD: Open Drain IN: Only input OUT: Only output Rev.1.00 Jan.
PAGE 587
13. PCI Controller (PCIC) 13.3 Register Descriptions Table 13.2 shows a list of PCIC registers. The addresses and offsets of PCI configuration registers are the values used when the PCIC is in little endian mode. The access size is the maximum access size in each register. The registers in the PCI configuration register space can be accessed with 32-, 16-, or 8-bit access sizes. Table 13.
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13.
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13.
PAGE 590
13. PCI Controller (PCIC) Table 13.
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13.
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13. PCI Controller (PCIC) 13.3.1 PCIC Enable Control Register (PCIECR) PCIECR is a register that specifies whether the PCIC is valid or invalid.
PAGE 593
13. PCI Controller (PCIC) 13.3.2 Configuration Registers The configuration registers define the programming model and usage rules of the configuration register space in a PCI compliant device. For details, see section 6, Configuration Space, in the PCI Local Bus Specification Revision 2.2. (1) PCI Vender ID Register (PCIVID) This field defines the PCI vendor ID.
PAGE 594
13. PCI Controller (PCIC) (3) PCI Command Register (PCICMD) PCICMD controls the basic functions of the PCIC to generate and respond to PCI cycles. When 0 is written to this register, this register ignores access commands from the external PCI device, other than configuration access.
PAGE 595
13. PCI Controller (PCIC) Bit Bit Name Initial Value 6 PER 0 SH: R/W Parity Error Response PCI: R/W Controls the response of the device when the PCIC detects a parity error or receives a parity error. When this bit is set to 1, the PERR signal is asserted.
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13. PCI Controller (PCIC) (4) PCI Status Register (PCISTATUS) PCISTATUS is used to record status information for events related to the PCI bus. The reserved bits are read-only bits that are read as 0. Reading from this register is normally performed. During writing, the write clear bit can be reset, but it cannot be set (R/WC in the figure below). Write 1 to the bit to be cleared. For example, to clear bit 14 so that other bits will not be affected, write the B'0100 0000 0000 0000 to this register.
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13. PCI Controller (PCIC) Bit Bit Name Initial Value R/W 12 RTA 0 SH: R/WC Target Abort Receive Status Description PCI: R/WC This bit indicates that a transaction was completed by target abort when the PCIC is a master. 0: Transaction is not completed with target abort 1: The bus master detected completion of transaction with target abort. 11 STA 0 SH: R/WC Target Abort Execution Status PCI: R/WC This bit indicates that a transaction was completed by target abort when the PCIC is a target.
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13. PCI Controller (PCIC) Bit Bit Name Initial Value R/W Description 6 ⎯ 0 SH: R/W Reserved PCI: R These bits are always read as 0. The write value should always be 0. SH: R/W 66MHz-Operation Capable Status PCI: R Indicates whether the PCIC can operate at 66MHz. 5 66C 0 0: PCIC operates at 33 MHz 1: PCIC operates at 66 MHz 4 CL 1 SH: R PCI Power Management (extended function) PCI: R Indicates whether the PCI power management is supported.
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13. PCI Controller (PCIC) (6) PCI Program Interface Register (PCIPIF) This field is the programming interface for the class code of the IDE controller. For details of the code value, see appendix D in PCI Local Bus Specification Revision 2.2.
PAGE 600
13. PCI Controller (PCIC) Bit Bit Name Initial Value R/W Description 0 OMP 0 SH: R/W PCI Operating Mode (Primary) PCI: R If this bit is written during register initialization (PCICR.CFINT = 0) in the PCIC, the value of this bit is updated. The value is not updated after initialization (PCICR.CFINT = 1). (7) PCI Sub Class Code Register (PCISUB) This field defines the sub class code. For details of the code value, see appendix D in PCI Local Bus Specification Revision 2.2.
PAGE 601
13. PCI Controller (PCIC) (8) PCI Base Class Code Register (PCIBCC) This field defines the base class code. For details of the class code, see appendix D in PCI Local Bus Specification Revision 2.2. Bit: 7 6 5 4 3 2 1 0 BCC Initial value: SH R/W: PCI R/W: x R/W x R/W x R/W x R/W x R/W x R/W x R/W x R/W R R R R R R R R Bit Bit Name Initial Value R/W Description 7 to 0 BCC H'xx SH: R/W Base Class Code PCI: R These bits indicate the base class code.
PAGE 602
13. PCI Controller (PCIC) (10) PCI Latency Timer Register (PCILTM) Bit: 7 6 5 4 3 2 1 0 LTM Initial value: SH R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W PCI R/W: R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 7 to 0 LTM H'00 SH: R/W Latency Timer Register PCI: R/W These bits specify the maximum time that the PCI bus is occupied with the clock cycle when the PCIC is a master.
PAGE 603
13. PCI Controller (PCIC) (12) PCI BIST Register (PCIBIST) 7 6 5 4 3 2 1 0 BISTC — — — — — — — Initial value: SH R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R PCI R/W: R R R R R R R R Bit: Bit Bit Name Initial Value R/W Description 7 BISTC 0 SH: R This bit is used for the BIST function control and status. PCI: R 0: Function not available 1: Function available (not supported) 6 to 0 ⎯ All 0 SH: R Reserved PCI: R These bits are always read as 0.
PAGE 604
13. PCI Controller (PCIC) (13) PCI I/O Base Address Register (PCIIBAR) This register is the I/O space base address register of the PCI configuration register space header that is defined in PCI local bus specification. This register specifies the base address in the I/O space of the PCIC. See section 13.4.4 (2), Accessing PCIC I/O Space.
PAGE 605
13. PCI Controller (PCIC) (14) PCI Memory Base Address Register 0 (PCIMBAR0) This register is the memory base address register of the PCI configuration register space header that is defined in PCI local bus specification. PCIMBAR0 specifies the memory space 0 (local address space 0) in this LSI internal bus (SuperHyway bus). See section 13.4.4 (1), Accessing Memory Space in This LSI.
PAGE 606
13. PCI Controller (PCIC) Bit Bit Name Initial Value 19 to 4 MBA2 H'0000 SH: R 3 LAP 0 R/W Description Memory Space 0 Base Address (lower 16 bits) PCI: R These bits are fixed to H'0000 by hardware. SH: R Prefetch Control PCI: R Indicates whether prefetch can be performed in local address space 0. 0: Prefetch disabled 1: Prefetch enabled (not supported) 2, 1 LAT 00 SH: R Memory Type PCI: R These bits indicate the memory type of local address space 0.
PAGE 607
13. PCI Controller (PCIC) (15) PCI Memory Base Address Register 1 (PCIMBAR1) This register is the memory base address register of the PCI configuration register space header that is defined in PCI local bus specification. PCIMBAR1 specifies the memory space 1 (local address space 1) in this LSI internal bus (SuperHyway bus). See section 13.4.4 (1), Accessing Memory Space in This LSI.
PAGE 608
13. PCI Controller (PCIC) Bit Bit Name Initial Value 19 to 4 MBA2 H'0000 SH: R 3 LAP 0 R/W Description Memory Space 1 Base Address (lower 16 bits) PCI: R These bits are fixed to H'0000 by hardware. SH: R Prefetch Control PCI: R Indicates whether prefetch can be performed in local address space 1. 0: Prefetch disabled 1: Prefetch enabled (not supported) 2, 1 LAT 00 SH: R Memory Type PCI: R These bits indicate the memory type of local address space 1.
PAGE 609
13. PCI Controller (PCIC) (16) PCI Subsystem Vender ID Register (PCISVID) See the description of each register in PCI Local Bus Specification Revision 2.2.
PAGE 610
13. PCI Controller (PCIC) (18) PCI Capability Pointer Register (PCICP) This register is the extension function pointer register of the PCI configuration register that is defined in the PCI Power Management Specification.
PAGE 611
13. PCI Controller (PCIC) (20) PCI Interrupt Pin Register (PCIINTPIN) 7 Bit: 6 5 4 3 2 1 0 INTPIN Initial value: SH R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 1 R/W R R R R R R R R PCI R/W: Bit Bit Name Initial Value 7 to 0 INTPIN H'01 R/W Description SH: R/W PCI: R Interrupt Pin Select These bits specify which interrupt pin is used as connection destination when the PCIC outputs interrupt requests. The initial value is H'01.
PAGE 612
13. PCI Controller (PCIC) (22) Maximum Latency Register (PCIMAXLAT) This register is not programmable. Bit: 7 6 5 4 3 2 1 0 MAXLAT Initial value: SH R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R PCI R/W: R R R R R R R R Bit Bit Name Initial Value R/W Description 7 to 0 MAXLAT H'00 SH: R Maximum Latency Specification (MILAT7 to MILAT0) PCI: R These bits specify the maximum time from requesting the bus mastership by the PCI master device to acquiring bus (not supported).
PAGE 613
13. PCI Controller (PCIC) (24) PCI Next Item Pointer Register (PCINIP) PCINIP indicates the location of the next item in the list of extension function. Bit: 7 6 5 4 3 2 1 0 NIP Initial value: SH R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R PCI R/W: R R R R R R R R Bit Bit Name Initial Value R/W Description 7 to 0 NIP H'00 SH: R Next Item Pointer PCI: R H'00: Indicates that power management function is listed as the last item. Rev.1.00 Jan.
PAGE 614
13. PCI Controller (PCIC) (25) PCI Power Management Register (PCIPMC) PCIPMC is a 16-bit register that provides information on the functions related to power management. For details, see section 3, PCI Power Management Interface in PCI Bus Power Management Interface Specification Revision 1.1. This register is not cleared by a power-on reset. This register must be set during initialization of register initialization in the PCIC (CFINIT = 0 in PCICR).
PAGE 615
13. PCI Controller (PCIC) Bit Bit Name Initial Value R/W Description 8 to 6 ⎯ All 0 SH: R Reserved PCI: R These bits are always read as 0. The write value should always be 0. SH: R DSI PCI: R The write value should always be 0. 5 DSI 0 0: Indicates that the proper initialization is not required 4 3 ⎯ PMEC 0 1 SH: R Reserved PCI: R These bits are always read as 0. The write value should always be 0.
PAGE 616
13. PCI Controller (PCIC) (26) PCI Power Management Control/Status Register (PCIPMCSR) This register manages power management events (PME) of the PCI function. For details, see section 3, PCI Power Management Interface in PCI Bus Power Management Interface Specification Revision 1.1.
PAGE 617
13. PCI Controller (PCIC) Bit Bit Name Initial Value R/W Description 1, 0 PS 00 SH: R/W Power State PCI: R/W These bits specify the power state. If an unsupported state is specified, a state transition is not made. However, the register is written normally and no error is indicated. 00: D0 state 01: D1 state 10: D2 state 11: D3 hot state Rev.1.00 Jan.
PAGE 618
13. PCI Controller (PCIC) (27) PCIPMCSR Bridge Support Extension Register (PCIPMCSRBSE) This register supports the functions specific to the PCI bridge and is required for all PCI-to-PCI bridges.
PAGE 619
13. PCI Controller (PCIC) (28) PCI Power Consumption/Radiation Register (PCIPCDD) The data register is an 8-bit optional register (read-only from the PCI bus) that notifies operation data such as power consumption depending on the state and heat dissipation. For details, see section 3, PCI Power Management Interface in PCI Bus Power Management Interface Specification Revision 1.1.
PAGE 620
13. PCI Controller (PCIC) 13.3.3 (1) PCI Local Registers PCI Control Register (PCICR) PCICR is a 32-bit register which controls the operation of the PCIC in this LSI. Writing to this register is valid only when the value of bits 31 to 24 are H'A5.
PAGE 621
13. PCI Controller (PCIC) Bit Bit Name Initial Value R/W 10 FTO 0 SH: R/W PCI TRDY/Control Enable PCI: R Description Specifies the function that negates TRDY within 5 cycles before disconnection in a target access. 0: Disabled 1: Enabled 9 PFE 0 SH: R/W PCI Pre-Fetch Enable PCI: R Specifies whether pre-fetch is performed when a target memory access is performed by an external PCI device.
PAGE 622
13. PCI Controller (PCIC) Bit Bit Name Initial Value R/W 2 IOCS 0 SH: R/W INTA Output PCI: R Description Controls the INTA output by software. This bit is valid only when the PCIC operates in normal mode. 0: The INTA pin is in the high-impedance state (driven high by an on-chip pull-up resistor) 1: Asserts INTA (output at low level) 1 RSTCTL 0 SH: R/W PCIRST Output PCI: R Controls the PCIRST pin state by setting this bit to 1. The PCIRST pin is output at low level at a power-on reset.
PAGE 623
13. PCI Controller (PCIC) (2) PCI Local Space Register 0 (PCILSR0) See section 13.4.4 (1), Accessing Memory Space in This LSI.
PAGE 624
13. PCI Controller (PCIC) Bit Bit Name Initial Value R/W Description 19 to 1 ⎯ All 0 SH: R Reserved PCI: R These bits are always read as 0. The write value should always be 0. SH: R/W PCI Memory Base Address Register 0 Enable PCI: R Enables accesses to the local address space 0 by setting this bit to 1. 0 MBARE 0 0: MBAR0 disabled 1: MBAR0 enabled (3) PCI Local Space Register 1 (PCILSR1) See section 13.4.4 (1), Accessing Memory Space in This LSI.
PAGE 625
13. PCI Controller (PCIC) Bit Bit Name 28 to 20 LSR Initial Value R/W 0 0000 SH: R/W 0000 PCI: R Description Capacity of Local Address Spaces 1 (9 bits) These bits specify the size of the local address space 1 (address space for this LSI internal bus) in byte units. (Specified size (Mbytes) − 1) should be set to these bits. When all bits are set to 0, 1-Mbyte space is secured (initial value).
PAGE 626
13. PCI Controller (PCIC) (4) PCI Local Address Register 0 (PCILAR0) See section 13.4.3 (2), Accessing PCI Memory Space.
PAGE 627
13. PCI Controller (PCIC) (5) PCI Local Address Register 1 (PCILAR1) See section 13.4.3 (2), Accessing PCI Memory Space.
PAGE 628
13. PCI Controller (PCIC) (6) PCI Interrupt Register (PCIIR) PCIIR records interrupt sources. When an interrupt occurs, the corresponding bit is set to 1. When multiple interrupts occur, only the first source is registered. When an interrupt is disabled, 1 is written to the corresponding bit by the interrupt source, and no interrupt occurs.
PAGE 629
13. PCI Controller (PCIC) Bit Bit Name Initial Value R/W Description 9 TMTOI 0 SH: R/WC Target Memory Read Retry Timeout Interrupt PCI: R Indicates that the master did not perform retry processing within 215 clocks in PCICLK when the PCIC is a target. This bit is detected only for memory read transfers.
PAGE 630
13. PCI Controller (PCIC) Bit Bit Name Initial Value R/W Description 6 SDI 0 SH: R/WC SERR Detection Interrupt PCI: R Indicates that the assertion of SERR was detected when the PCIC is a host. 0: A SERR detection interrupt was not generated 1: A SERR detection interrupt was generated When TTADI bit is write to 0, target target-abort interrupt is cleared. When write to 1, it is not available.
PAGE 631
13. PCI Controller (PCIC) Bit Bit Name Initial Value R/W Description 3 TADIM 0 SH: R/WC Target Abort Detection Interrupt for Master PCI: R Indicates that transaction was terminated by a target abort when the PCIC is a master. 0: A target abort interrupt was not generated when the PCIC is a master 1: A target abort interrupt was generated when the PCIC is a master When TTADI bit is write to 0, target target-abort interrupt is cleared. When write to 1, it is not available.
PAGE 632
13. PCI Controller (PCIC) Bit Bit Name Initial Value R/W Description 0 MRDPEI 0 SH: R/WC Master Read Data Parity Error Interrupt PCI: R Indicates that the PCIC detected a parity error during data read from the target when the PCIC is a master. Note: A master read data parity error is detected only when bit 6 (PER) in PCICMD is set to 1.
PAGE 633
13. PCI Controller (PCIC) (7) PCI Interrupt Mask Register (PCIIMR) This register is the mask register for PCIIR.
PAGE 634
13.
PAGE 635
13. PCI Controller (PCIC) (8) PCI Error Address Information Register (PCIAIR) This register records PCI address information when an error is detected. The value of this register is undefined until an interrupt is detected. Regardless of the information on mask registers, etc, the value is retained when an interrupt is detected.
PAGE 636
13. PCI Controller (PCIC) (9) PCI Error Command Information Register (PCICIR) This register records the PCI command information when an error is detected. The value of this register is undefined until an interrupt is detected. Regardless of the information on mask registers, etc, the value is retained when an interrupt is detected.
PAGE 637
13. PCI Controller (PCIC) (10) PCI Arbiter Interrupt Register (PCIAINT) In host mode, this register records interrupt sources. When multiple interrupts occur, only the first source is registered. When an interrupt is disabled, the source is written to the corresponding bit in this register, and, no interrupt occurs.
PAGE 638
13. PCI Controller (PCIC) Bit Bit Name Initial Value R/W 11 MBTOI 0 SH: R/WC Master Bus Time-Out Interrupt PCI: R Description An interrupt is detected when IRDY is not asserted within 8 clock cycles during data transfer. 0: A master bus timeout interrupt was not generated 1: A master bus timeout interrupt was generated 10 to 4 3 ⎯ TAI All 0 0 SH: R Reserved PCI: R These bits are always read as 0. The write value should always be 0.
PAGE 639
13. PCI Controller (PCIC) (11) PCI Arbiter Interrupt Mask Register (PCIAINTM) This register is the mask register for PCIAINT.
PAGE 640
13.
PAGE 641
13. PCI Controller (PCIC) Bit Bit Name Initial Value 31 to 5 ⎯ All 0 4 R/W Description SH: R PCI: R Reserved These bits are always read as 0. The write value should always be 0.
PAGE 642
13. PCI Controller (PCIC) (13) PCI PIO Address Register (PCIPAR) Setting this register generates configuration cycles on the PCI bus. For details, see section 13.4.5 (2), Configuration Space Access.
PAGE 643
13. PCI Controller (PCIC) Bit Bit Name 15 to 11 DN Initial Value R/W xxxxx SH: R/W Device Number PCI: ⎯ Description These bits specify a device number for the configuration access target. A device number is represented by a 5-bit value in the range from 0 to 31. Corresponding to the device number specified in this field, one of the ADn (n = 31 to 16) signals is driven high instead of IDSEL (other bits are all low). The following shows the correspondence between the device number and IDSEL.
PAGE 644
13. PCI Controller (PCIC) (14) PCI Power Management Interrupt Register (PCIPINT) This register registers power management interrupt sources.
PAGE 645
13. PCI Controller (PCIC) Bit Initial Bit Name Value R/W 0 PMD0 SH: R/WC PCI Power Management D0 Status Transition Interrupt 0 Description PCI: ⎯ Indicates that an interrupt to request a transition to the PCI bus power-down mode was generated. 0: No D0 status transition interrupt was generated 1: A D0 status transition interrupt was generated (15) PCI Power Management Interrupt Mask Register (PCIPINTM) This register is the mask register for PCIPINT.
PAGE 646
13.
PAGE 647
13. PCI Controller (PCIC) (17) PCI Memory Bank Mask Register 0 (PCIMBMR0) This register is the mask register for PCIMBR0. This register specifies the memory space size on the PCI bus for a memory read or write to the PCI memory space 0 by the CPU or DMAC. See section 13.4.3 (2), Accessing PCI Memory Space.
PAGE 648
13. PCI Controller (PCIC) (18) PCI Memory Bank Register 1 (PCIMBR1) This register specifies the upper 14 bits of the memory space address on the PCI bus for a memory read or write to the PCI memory space 1 by the CPU or DMAC. See section 13.4.3 (2), Accessing PCI Memory Space.
PAGE 649
13. PCI Controller (PCIC) (19) PCI Memory Bank Mask Register 1 (PCIMBMR1) This register is the mask register for PCIMBR1. This register specifies the memory space size on the PCI bus for a memory read or write to the PCI memory space 1 by the CPU or DMAC. See section 13.4.3 (2), Accessing PCI Memory Space.
PAGE 650
13. PCI Controller (PCIC) (20) PCI Memory Bank Register 2 (PCIMBR2) This register specifies the upper 14 bits of the memory space address on the PCI bus for a memory read or write to the PCI memory space 2 by the CPU or DMAC. See section 13.4.3 (2), Accessing PCI Memory Space.
PAGE 651
13. PCI Controller (PCIC) (21) PCI Memory Bank Mask Register 2 (PCIMBMR2) This register is the mask register for PCIMBR2. This register specifies the memory space size on the PCI bus for a memory read or write to the PCI memory space 2 by the CPU or DMAC. See section 13.4.3 (2), Accessing PCI Memory Space.
PAGE 652
13. PCI Controller (PCIC) (22) PCI I/O Bank Register (PCIIOBR) This register specifies the upper 14 bits of the I/O space address on the PCI bus for an I/O-read or I/O-write to the PCI I/O space by the CPU or DMAC. See section 13.4.3 (3), Accessing PCI I/O Space.
PAGE 653
13. PCI Controller (PCIC) (23) PCI I/O Bank Mask Register (PCIIOBMR) This register is the mask register for PCIIOBR. This register specifies the I/O space size on the PCI bus for an I/O-read or I/O-write to the PCI I/O space by the CPU or DMAC. See section 13.4.3 (3), Accessing PCI I/O Space.
PAGE 654
13. PCI Controller (PCIC) (24) PCI Cache Snoop Control Register 0 (PCICSCR0) An external PCI device can access memory of this LSI via the PCIC. When an PCI device accesses a cacheable area, the PCIC can issue cache snoop commands to the on-chip caches. This register can specify the function that uses PCICSAR0. For details, see section 13.4.4 (7), Cache Coherency.
PAGE 655
13. PCI Controller (PCIC) Bit Bit Name Initial Value R/W Description 1, 0 SNPMD All 0 SH: R/W Snoop Mode for PCICSAR0 PCI: — These bits specify whether PCICSAR0 is compared with the SuperHyway bus address requested by an external device, or not. When PCICSAR0 is specified to be compared, a condition to issue snoop commands can be specified. 00: PCICSAR0 is not compared 01: Reserved (setting prohibited) 10: PCICSAR0 is compared.
PAGE 656
13. PCI Controller (PCIC) Bit Bit Name Initial Value R/W Description 31 to 5 ⎯ All 0 SH: R Reserved PCI: — These bits are always read as 0. The write value should always be 0. SH: R/W Address Range to be Compared PCI: — These bits specify the address range of PCICSAR1 to be compared. 4 to 2 RANGE All 0 000: Compared with PCICSAR1.CADR[31:12] (4 kbytes) 001: Compared with PCICSAR1.CADR[31:16] (64 kbytes) 010: Compared with PCICSAR1.CADR[31:20] (1 Mbyte) 011: Compared with PCICSAR1.
PAGE 657
13. PCI Controller (PCIC) (26) PCI Cache Snoop Address Register 0 (PCICSAR0) This register specifies the address to be compared with the PCI address requested by an external PCI device to the PCIC. For details, see section 13.4.4 (7), Cache Coherency.
PAGE 658
13. PCI Controller (PCIC) (27) PCI Cache Snoop Address Register 1 (PCICSAR1) This register specifies the address to be compared with the PCI address requested by an external PCI device to the PCIC. For details, see section 13.4.4 (7), Cache Coherency.
PAGE 659
13. PCI Controller (PCIC) (28) PCI PIO Data Register (PCIPDR) By reading or writing to this register, a configuration cycle is generated on the PCI bus. For details, see section 13.4.5 (2), Configuration Space Access.
PAGE 660
13. PCI Controller (PCIC) 13.4 Operation 13.4.1 Supported PCI Commands Table 13.
PAGE 661
13. PCI Controller (PCIC) 13.4.2 PCIC Initialization After a power-on reset, the ENBL bit in PCIECR and the CFINIT bit in PCICR are cleared. At this time, if the PCIC operates as the PCI bus host (host mode), device arbitration is not performed on the PCI bus, and the bus mastership is always granted to the PCIC. When the PCIC does not operate as host (normal mode), access from an external PCI device connected to the PCI bus is not accepted, and retries are returned to the PCI bus.
PAGE 662
13. PCI Controller (PCIC) 13.4.3 Master Access This section describes how software controls the PCI when the PCIC is a bus master. This section describes the cases where the PCIC is used in both host mode and normal mode. (1) Address Map Table 13.5 shows the PCIC address map. Table 13.
PAGE 663
13. PCI Controller (PCIC) (2) Accessing PCI Memory Space Figure 13.2 shows the memory map from the SuperHyway bus to the PCI bus. SHwy bus address space (4 GB) H'0000 0000 H'1000 0000 PCI address space (4 GB) 16 MB PCI memory space 1 64 MB H'C000 0000 64 MB 512 MB PCI memory space 2 512 MB H'FD00 0000 H'FE00 0000 H'FE20 0000 PCI memory space 0 16 MB Register space 2 MB PCI I/O space 2 MB Figure 13.2 Memory Map from SuperHyway Bus to PCI Bus To access the PCI memory space, use PCIMBR and PCIMBMR.
PAGE 664
13. PCI Controller (PCIC) For PCI memory space 0, the middle six bits ([23:18]) are controlled by PCIMBMR0. • PCIMBMR0 [23:18] B'1111 11: PCI address [23:18] = SuperHyway bus address [23:18] • PCIMBMR0 [23:18] B'0000 00: PCI address [23:18] = PCIMBR0 [23:18] The upper eight bits ([31:24]) of a SuperHyway bus address are replaced with bits 31 to 24 in PCIMBR0.
PAGE 665
13. PCI Controller (PCIC) For PCI memory space 2 accesses, the middle eleven bits ([28:18]) are controlled by PCIMBMR2. • PCIMBMR2 [28:18] B'1 1111 1111 11: PCI address [28:18] = SuperHyway bus address [28:18] • PCIMBMR2 [28:18] B'0 0000 0000 00: PCI address [28:18] = PCIMBR2 [28:18] The upper three bits ([31:29]) of a SuperHyway bus address are replaced with bits 31 to 29 in PCIMBR2.
PAGE 666
13. PCI Controller (PCIC) (3) Accessing PCI I/O Space Burst transfers are not supported in I/O transfers. Access within the size of 4-byte. The PCI I/O address space is allocated from H'FD20 0000 to H'FE3F FFFF (2 Mbytes). Address translation from SuperHyway bus to PCI local bus is shown below. The lower 15 bits ([17:3]) of a SuperHyway bus address are sent without translation. The middle bits ([20:18]) of a SuperHyway bus address are controlled by PCIIOBMR.
PAGE 667
13. PCI Controller (PCIC) 1. Little endian SHwy data Buffer data MSB LSB A' B' C' D' A B C D A' B' C' D' A B C D PCI_Addr[2] = 1 PCI_Addr[2] = 0 PCI bus data A B C D 31 0 2. Big endian SHwy data Buffer data MSB LSB A B C D A' B' C' D' A B C D A' B' C' D' PCI_Addr[2] = 0 PCI_Addr[2] = 1 PCI bus data A B C D 31 0 Note: PCIAddr[2]: PCI bus AD[2] Figure 13.7 Endian Conversion from SuperHyway Bus to PCI Bus (Non-Byte Swapping: TBS = 0) Rev.1.00 Jan.
PAGE 668
13. PCI Controller (PCIC) 1. Little endian SHwy data MSB LSB A' B' C' D' A B C D A' B' C' D' A B C D Buffer data PCI_Addr[2] = 1 PCI_Addr[2] = 0 PCI bus data A B C D 31 0 2. Big endian SHwy data MSB LSB D C B A D' C' B' A' A B C D A' B' C' D' Buffer data PCI_Addr[2] = 1 PCI_Addr[2] = 0 PCI bus data A B C D 31 0 Note: PCIAddr[2]: PCI bus AD[2] Figure 13.8 Endian Conversion from SuperHyway Bus to PCI Local Bus (Byte Swapping: TBS = 1) Rev.1.00 Jan.
PAGE 669
13. PCI Controller (PCIC) PCI bus SHwy bus Big-endian CPU Size Address Data 31 4n + 0 0 A 4n + 1 Little-endian CPU Data (without swapping) Data (with swapping) 31 0 31 0 A B A B 31 0 A B B Byte 4n + 2 C 4n + 3 4n + 0 C D A B C D A C D D B B A A B Word 4n + 2 longword 4n + 0 A B C D C D A B C D D C C D D C B A A B C D C D Figure 13.9 Data Alignments for SuperHyway Bus and PCI Bus Rev.1.00 Jan.
PAGE 670
13. PCI Controller (PCIC) 13.4.4 Target Access This section describes how the PCIC in this LSI is accessed by an external PCI local bus master when the PCIC is used in both the host mode and normal mode. (1) Accessing Memory Space in This LSI Accesses to the PCIC in this LSI by an external PCI bus master are described below.
PAGE 671
13. PCI Controller (PCIC) To access the address space in this LSI, use PCIMBAR0/1, PCILSR0/1, and PCILAR0/1. PCI addresses can be allocated to by software. The PCIC has two types of registers for memory mapping, Local Address Space 0 (base 0) and Local Address Space 1 (base 1). By setting these two registers, two types of spaces (bases) can be allocated. The size of these address spaces are selectable from 1 Mbyte to 512 Mbytes by PCILSR0/1.
PAGE 672
13. PCI Controller (PCIC) 31 29 28 20 19 0 31 29 28 20 19 0 31 29 28 20 19 0 SHwy bus address PCI address Compare PCILAR0/1 31 29 28 20 19 29 28 20 19 0 PCIMBAR0/1 31 0 MBARE PCILSR0/1 Figure 13.11 PCI Bus to SuperHyway Bus Address Translation (2) Accessing PCIC I/O Space The PCI I/O address space should be allocated as 256 bytes. The lower eight bits ([7:0]) are sent to the internal bus without translation.
PAGE 673
13. PCI Controller (PCIC) (3) Accessing PCIC Registers Configuration Registers: Configuration registers should be read or written with (offset from configuration register space base address) by configuration accesses. A burst transfer is cut off and terminated. Local Registers: Local registers should be accessed with (PCI address + offset) using I/O read or write commands. Only a single longword access is supported. A burst transfer is cut off and terminated.
PAGE 674
13. PCI Controller (PCIC) (6) Endian This LSI supports both the big and little endian formats. Since the PCI local bus is inherently little endian, the PCIC supports both byte swapping and non-byte swapping. The endian format is specified by the TBS bit in PCICR. 1. Little endian PCI bus data 31 0 A B C D PCI_Addr[2] = 0 PCI_Addr[2] = 1 A' B' C' D' A B C D Buffer data MSB SHwy data LSB A' B' C' D' A B C D 2.
PAGE 675
13. PCI Controller (PCIC) 1. Little endian PCI bus data 31 0 A B C D PCI_Addr[2] = 0 PCI_Addr[2] = 1 A' B' C' D' A B C D Buffer data MSB SHwy data LSB A' B' C' D' A B C D 2. Big endian PCI bus data 31 0 A B C D PCI_Addr[2] = 1 PCI_Addr[2] = 0 D C B A D' C' B' A' Buffer data MSB SHwy data LSB D C B A D' C' B' A' Note: PCIAddr[2]: PCI bus AD[2] Figure 13.14 Endian Conversion from PCI Bus to SuperHyway Bus (Byte Swapping: TBS = 1) Rev.1.00 Jan.
PAGE 676
13. PCI Controller (PCIC) SHwy bus PCI bus Big-endian CPU Size Address Data 31 4n + 0 0 A 4n + 1 Little-endian CPU Data (without swapping) Data (with swapping) 31 0 31 0 A B A B 31 0 A B B Byte 4n + 2 C 4n + 3 4n + 0 C D A B C D A C D D B B A A B Word 4n + 2 Longword 4n + 0 A B C D C D A B C D D C C D D C B A A Figure 13.15 Data Alignments for SuperHyway Bus and PCI Bus Rev.1.00 Jan.
PAGE 677
13. PCI Controller (PCIC) (7) Cache Coherency The PCIC supports cache coherency function. When the PCIC functions as a target device, cache coherency is guaranteed on the PCI bus for accesses from a master device both in host mode and normal mode. When a cacheable area of this LSI is accessed, PCICSCR0/1 and PCICSAR0/1 should be set. The following shows the usage notes for this function. • Up to two conditions can be set for the snoop address. These two conditions are logical ORed for address comparison.
PAGE 678
13. PCI Controller (PCIC) 13.4.5 (1) Host Mode Operation in Host Mode The PCI interface of this LSI supports a subset of the PCI version 2.2 and can be connected to a device with a PCI bus interface. According to the PCIC mode, host mode or normal mode, operation differs in two points: (1) the PCIC unconditionally performs bus parking or not, and (2) the PCI bus arbitration function is enabled or disabled.
PAGE 679
13. PCI Controller (PCIC) 3130 2423 Configuration address Reserved Bus No. register Enable bit 0: Disabled 1: Enabled PCI bus address 1110 8 7 1615 210 Device No. Function Register No. 0 0 No. Only one bit is set to 1. 31 00 1110 87 210 Figure 13.17 Address Generation for Type 0 Configuration Access In configuration accesses, no interrupt is generated by a PCI master abort (no device connected). A configuration write will end normally. A configuration read will return a value of 0.
PAGE 680
13.
PAGE 681
13. PCI Controller (PCIC) The PCIC can retain error information on the PCI bus. When an error occurs, the error address is stored in PCIAIR and the transfer type and command information are stored in PCICIR. When the PCIC is in host mode, the bus master information at the error occurrence is stored in PCIBMIR. The PCIC can retain only one error information. Therefore, when multiple errors occur, only the first error information is retained and subsequent error information is not retained.
PAGE 682
13. PCI Controller (PCIC) D0 (Nomal state) D2 (Clock stopped) D1 (Bus idle) D3 (Power-down) Figure 13.18 Power Down State Transitions on PCI Bus When the PCIC detects that the power state (PS) bit in PCIPMCSR changes (PS is written by an external PCI device), it issues a power management interrupt. PCIPINT and PCIPINTM are used to control the power management interrupts.
PAGE 683
13. PCI Controller (PCIC) 13.4.8 PCI Local Bus Basic Interface The PCI interface of this LSI supports subsets in the PCI bus version 2.2 and it can be connected to a device with a PCI bus interface. The following figures show the timing in each operating mode. (1) Master Read/Write Cycle Timing Figure 13.19 shows an example of a single-write cycle in host mode. Figure 13.20 shows an example of a single-read cycle in host mode. Figure 13.21 shows an example of a burst-write cycle in normal mode.
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13. PCI Controller (PCIC) PCICLK Addr AD[31:0] D0 DP0 AP PAR Com C/BE[3:0] BE0 PCIFRAME IRDY DEVSEL TRDY LOCK IDSEL REQ GNT Legend: Addr: PCI space address Dn: nth data AP: Address parity DPn: nth data parity Com: Command BEn: nth data byte enable Figure 13.20 Master Read Cycle in Host Mode (Single) Rev.1.00 Jan.
PAGE 685
13. PCI Controller (PCIC) PCICLK Addr AD[31:0] PAR Com C/BE[3:0] D0 D1 Dn AP DP0 DPn-1 BE0 BE1 BEn DPn PCIFRAME IRDY DEVSEL TRDY LOCK IDSEL REQOUT GNTIN Legend: Addr: PCI space address Dn: nth data AP: Address parity DPn: nth data parity Com: Command BEn: nth data byte enable Figure 13.21 Master Write Cycle in Normal Mode (Burst) Rev.1.00 Jan.
PAGE 686
13. PCI Controller (PCIC) PCICLK D0 Addr AD[31:0] AP PAR Com C/BE[3:0] BE0 D1 Dn DP0 DPn-1 DPn BE1 BEn PCIFRAME IRDY DEVSEL TRDY LOCK IDSEL REQOUT GNTIN Legend: Addr: PCI space address Dn: nth data AP: Address parity DPn: nth data parity Com: Command BEn: nth data byte enable Figure 13.22 Master Read Cycle in Normal Mode (Burst) Rev.1.00 Jan.
PAGE 687
13. PCI Controller (PCIC) (2) Target Read/Write Cycle Timing The PCIC returns retries to target memory read accesses from an external master until 8 longword (32-bit) data are prepared in the PCIC internal FIFO. That is, the first target read is always responded by a retry. When a target memory write access is performed for the PCIC, the PCIC returns retries to all subsequent target memory accesses until the write data is completely written to local memory.
PAGE 688
13. PCI Controller (PCIC) PCICLK Addr AD[31:0] D0 AP PAR Com C/BE[3:0] DP0 BE0 PCIFRAME IRDY DEVSEL TRDY STOP Disconnect LOCK Lock IDSEL Configuration space access REQOUT GNTIN Legend: Addr: PCI space address Dn: nth data AP: Address parity DPn: nth data parity Com: Command BEn: nth data byte enable Figure 13.23 Target Read Cycle in Normal Mode (Single) Rev.1.00 Jan.
PAGE 689
13. PCI Controller (PCIC) PCICLK AD[31:0] Addr D0 AP PAR C/BE[3:0] Com DP0 BE0 PCIFRAME IRDY DEVSEL TRDY STOP Disconnect LOCK Lock IDSEL Configuration space access REQOUT GNTIN Legend: Addr: PCI space address Dn: nth data AP: Address parity DPn: nth data parity Com: Command BEn: nth data byte enable Figure 13.24 Target Write Cycle in Normal Mode (Single) Rev.1.00 Jan.
PAGE 690
13. PCI Controller (PCIC) PCICLK AD[31:0] Addr D0 AP PAR C/BE[3:0] Com D1 DP0 BE0 BE1 Dn DPn-1 DPn BEn PCIFRAME IRDY DEVSEL TRDY STOP Disconnect Lock LOCK IDSEL REQ GNT Legend: Addr: PCI space address Dn: nth data AP: Address parity DPn: nth data parity Com: Command BEn: nth data byte enable Figure 13.25 Target Memory Read Cycle in Host Mode (Burst) Rev.1.00 Jan.
PAGE 691
13. PCI Controller (PCIC) PCICLK AD[31:0] Addr D0 AP PAR C/BE[3:0] Com D1 DPn-1 DPn DP0 BE0 Dn BE1 BEn PCIFRAME IRDY DEVSEL TRDY STOP Disconnect Lock LOCK IDSEL REQ GNT Legend: Addr: PCI space address Dn: nth data AP: Address parity DPn: nth data parity Com: Command BEn: nth data byte enable Figure 13.26 Target Memory Write Cycle in Host Mode (Burst) Rev.1.00 Jan.
PAGE 692
13. PCI Controller (PCIC) (3) Address/Data Stepping Timing By writing 1 to the SC bit in PCICMD, a wait (stepping) of one clock can be inserted when the PCIC is driving the AD bus. As a result, the PCIC drives the AD bus with 2 clocks. This function can be used when the PCI bus load is heavy and the AD bus does not achieve the stipulated logic level in one clock. It is recommended to use this function when the PCIC issues configuration transfers in host mode. Figure 13.
PAGE 693
13. PCI Controller (PCIC) PCICLK AD[31:0] Addr D0 AP PAR C/BE[3:0] Com D1 DP0 BE0 BE1 Dn DPn-1 DPn BEn PCIFRAME IRDY DEVSEL TRDY Legend: Addr: PCI space address Dn: nth data AP: Address parity DPn: nth data parity Com: Command BEn: nth data byte enable Figure 13.28 Target Memory Read Cycle in Host Bus Bridge Mode (Burst, with Stepping) Rev.1.00 Jan.
PAGE 694
13. PCI Controller (PCIC) Rev.1.00 Jan.
PAGE 695
14. Direct Memory Access Controller (DMAC) Section 14 Direct Memory Access Controller (DMAC) This LSI includes an on-chip direct memory access controller (DMAC). Instead of the CPU, the DMAC can be used to perform data transfers among external devices equipped with DACK (transfer request acceptance signal), external memory, on-chip memory, memory-mapped external devices, and on-chip peripheral modules. 14.
PAGE 696
14. Direct Memory Access Controller (DMAC) Figure 14.1 shows a block diagram of the DMAC.
PAGE 697
14. Direct Memory Access Controller (DMAC) 14.2 Input/Output Pins The DMAC-related external pins are shown below. Table 14.1 shows the configuration of the pins that are connected to external device. The DMAC has pins for four channels (channels 0 to 3) used in the external bus. Table 14.
PAGE 698
14. Direct Memory Access Controller (DMAC) 14.3 Register Descriptions Table 14.2 shows the register configuration. Table 14.2 Register Configuration of the DMAC (1) Area 7 Access Sync Channel Name Abbrev.
PAGE 699
14. Direct Memory Access Controller (DMAC) Area 7 Access Sync Channel Name Abbrev.
PAGE 700
14. Direct Memory Access Controller (DMAC) Channel Name Abbrev.
PAGE 701
14. Direct Memory Access Controller (DMAC) Table 14.2 Register Configuration of the DMAC (2) Power-on Manual Reset Reset by PRESET by Deep Sleep Sleep by SLEEP instruction Module Pin/WDT/ WDT/Multiple by SLEEP Abbrev.
PAGE 702
14. Direct Memory Access Controller (DMAC) Power-on Manual Reset Reset by PRESET by Deep Sleep Sleep Pin/WDT/ WDT/Multiple by SLEEP by SLEEP instruction Module Channel Name Abbrev.
PAGE 703
14. Direct Memory Access Controller (DMAC) Power-on Manual Reset Reset by PRESET by Deep Sleep Sleep Pin/WDT/ WDT/Multiple by SLEEP by SLEEP instruction Module Channel Name Abbrev.
PAGE 704
14. Direct Memory Access Controller (DMAC) Power-on Manual Reset Reset by PRESET by Deep Sleep Sleep Pin/WDT/ WDT/Multiple by SLEEP by SLEEP instruction Module Channel Name Abbrev.
PAGE 705
14. Direct Memory Access Controller (DMAC) 14.3.1 DMA Source Address Registers 0 to 11 (SAR0 to SAR11) SAR are 32-bit readable/writable registers that specify the source address of a DMA transfer. During a DMA transfer, these registers indicate the source address of the next transfer. A word or longword boundary address should be specified when a word or longword transfer is performed respectively.
PAGE 706
14. Direct Memory Access Controller (DMAC) 14.3.2 DMA Source Address Registers B0 to B3, B6 to B9 (SARB0 to SARB3, SARB6 to SARB9) SARB are 32-bit readable/writable registers that specify the source address of a DMA transfer that is set in SAR again in repeat/reload mode. The data written to SAR by the CPU is also written to SARB. To set the address that is different from SAR address, write data to SAR, then, to SARB.
PAGE 707
14. Direct Memory Access Controller (DMAC) 14.3.3 DMA Destination Address Registers 0 to 11 (DAR0 to DAR11) DAR are 32-bit readable/writable registers that specify the destination address of a DMA transfer. During a DMA transfer, these registers indicate the destination address of the next transfer. A word or longword boundary address should be specified when a word or longword transfer is performed respectively.
PAGE 708
14. Direct Memory Access Controller (DMAC) 14.3.4 DMA Destination Address Registers B0 to B3, B6 to B9 (DARB0 to DARB3, DARB6 to DARB9) DARB are 32-bit readable/writable registers that specify the destination address of a DMA transfer that is set in DAR again in repeat/reload mode. The data written to DAR by the CPU is also written to DARB. To set the address that is different from DAR address, write data to DAR, then, to DARB.
PAGE 709
14. Direct Memory Access Controller (DMAC) 14.3.5 DMA Transfer Count Registers 0 to 11 (TCR0 to TCR11) TCR are 32-bit readable/writable registers that specify the DMA transfer count. When the value is set to H'00000001, H'00FFFFFF, H'00000000, the transfer count is 1, 16,777,215, and 16,777,216 (the maximum) respectively. During a DMA transfer, these registers indicate the remaining transfer count. The upper eight bits in TCR (bits 31 to 24) are always read as 0. The write value should always be 0.
PAGE 710
14. Direct Memory Access Controller (DMAC) 14.3.6 DMA Transfer Count Registers B0 to B3, B6 to B9 (TCRB0 to TCRB3, TCRB6 to TCRB9) TCRB are 32-bit readable/writable registers. The data written to TCR by the CPU is also written to TCRB. While the half end function is being used, TCRB are used as the initial value retain registers to detect half end. Also, TCRB specify the number of DMA transfers which are set in TCR again in repeat mode.
PAGE 711
14. Direct Memory Access Controller (DMAC) 14.3.7 DMA Channel Control Registers 0 to 11 (CHCR0 to CHCR11) CHCR are 32-bit readable/writable registers that control the DMA transfer mode.
PAGE 712
14. Direct Memory Access Controller (DMAC) Bit Bit Name Initial Value R/W Descriptions 27 to 25 RPT[2:0] 000 R/W DMA Setting Update Specification These bits are valid in only CHCR0 to CHCR3, and CHCR6 to CHCR9.
PAGE 713
14. Direct Memory Access Controller (DMAC) Bit Bit Name Initial Value R/W Descriptions 21 ⎯ 0 R Reserved This bit is always read as 0. The write value should always be 0. 20 TS2 0 R/W DMA Transfer Size Specification Specifies the DMA transfer size with TS1 and TS0. When the transfer source or transfer destination is a register in an on-chip peripheral module register that the access size is specified, the transfer data size for the register should be the same as the access size.
PAGE 714
14. Direct Memory Access Controller (DMAC) Bit Bit Name Initial Value R/W 19 HE 0 R/(W)* Half End Flag Descriptions After HIE (bit 18) is set to 1 and the number of transfers is half of TCR (one bit shift to right) which is set before transfer, HE is 1.
PAGE 715
14. Direct Memory Access Controller (DMAC) Bit Bit Name Initial Value R/W Descriptions 17 AM 0 R/W Acknowledge Mode Selects whether DACK is output in a data read cycle or in a data write cycle. DACK is output only for LBSC space transfers. This bit is valid in only CHCR0 to CHCR3. 0: DACK output in a read cycle (DACK is output only when the DMA transfer source is LBSC space.) 1: DACK output in a write cycle (DACK is output only when the DMA transfer destination is LBSC space.
PAGE 716
14. Direct Memory Access Controller (DMAC) Bit Bit Name Initial Value R/W Descriptions 15, 14 DM[1:0] 00 R/W Destination Address Mode 1, 0 Specify whether the DMA destination address is incremented or decremented.
PAGE 717
14. Direct Memory Access Controller (DMAC) Bit Bit Name Initial Value R/W Descriptions 11 to 8 RS[3:0] 0000 R/W Resource Select 3 to 0 Specify the transfer request source. To change the transfer request source, the DMA enable (DE) bit should be cleared to 0.
PAGE 718
14. Direct Memory Access Controller (DMAC) Bit Bit Name Initial Value R/W Descriptions 2 IE 0 R/W Interrupt Enable Specifies whether an interrupt request is generated to the CPU at the end of the final DMA transfer. Setting this bit to 1 generates an interrupt request (DMINT) to the CPU when the TE bit is set to 1 and a read cycle of the final DMA transfer has ended. To confirm that the final transfer has ended, execute a dummy read of the destination space after issuing the SYNCO instruction.
PAGE 719
14. Direct Memory Access Controller (DMAC) 14.3.8 DMA Operation Register 0, 1 (DMAOR0 and DMAOR1) DMAOR are 16-bit readable/writable registers that specify the priority of channels in DMA transfer. Also, these registers show the DMA transfer status. DMAOR 0 is a register common to channels 0 to 5, and DMAOR1 is a register common to channels 6 to11.
PAGE 720
14. Direct Memory Access Controller (DMAC) Bit Bit Name Initial Value R/W Descriptions 11, 10 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0. 9, 8 PR[1:0] 00 R/W Priority Mode 1, 0 Determine the priority between channels when there are transfer requests for multiple channels simultaneously.
PAGE 721
14. Direct Memory Access Controller (DMAC) Bit Bit Name Initial Value R/W 2 AE 0 R/(W)* Address Error Flag Descriptions Indicates that an address error occurred during DMA transfer. This bit is set under following conditions. • The value set in SAR or DAR does not match to the transfer size boundary. • The transfer source or transfer destination is undefined space on the address map.
PAGE 722
14. Direct Memory Access Controller (DMAC) Bit Bit Name Initial Value R/W Descriptions 0 DME 0 R/W DMA Master Enable Enables or disables DMA transfers on all channels (channels 0 to 5) corresponding to DMAOR0, and all channels (channels 6 to 11) corresponding to DMAOR1. If the DME bit, and the DE bit in CHCR are set to 1, transfer is enabled. All of the TE bit in CHCR in the channel that executes transfer, NMIF, and AE in DMAOR corresponding to channels should be 0.
PAGE 723
14. Direct Memory Access Controller (DMAC) 14.3.9 DMA Extended Resource Selectors 0 to 5 (DMARS0 to DMARS5) DMARS are 16-bit readable/writable registers. DMARS0, DMARS1, DMARS2, DMARS3, DMARS4, and DMARS5 specify DMA transfer request source from peripheral modules for channels 0 and 1, channels 2 and 3, channels 4 and 5, channels 6 and 7, channels 8 and 9, and channels 10 and 11 respectively.
PAGE 724
14.
PAGE 725
14. Direct Memory Access Controller (DMAC) • DMARS1 Bit Bit Name Initial Value R/W Descriptions 15 C3MID5 0 R/W 14 C3MID4 0 R/W Transfer request source module ID5 to ID0 for DMA channel 3 (MID) 13 C3MID3 0 R/W See table 14.3. 12 C3MID2 0 R/W 11 C3MID1 0 R/W 10 C3MID0 0 R/W 9 C3RID1 0 R/W 8 C3RID0 0 R/W Transfer request source register ID1 and ID0 for DMA channel 3 (RID) See table 14.3.
PAGE 726
14. Direct Memory Access Controller (DMAC) • DMARS2 Bit Bit Name Initial Value R/W Descriptions 15 C5MID5 0 R/W 14 C5MID4 0 R/W Transfer request source module ID5 to ID0 for DMA channel 5 (MID) 13 C5MID3 0 R/W See table 14.3. 12 C5MID2 0 R/W 11 C5MID1 0 R/W 10 C5MID0 0 R/W 9 C5RID1 0 R/W 8 C5RID0 0 R/W Transfer request source register ID1 and ID0 for DMA channel 5 (RID) See table 14.3.
PAGE 727
14. Direct Memory Access Controller (DMAC) • DMARS3 Bit Bit Name Initial Value R/W Descriptions 15 C7MID5 0 R/W 14 C7MID4 0 R/W Transfer request source module ID5 to ID0 for DMA channel 7 (MID) 13 C7MID3 0 R/W See table 14.3. 12 C7MID2 0 R/W 11 C7MID1 0 R/W 10 C7MID0 0 R/W 9 C7RID1 0 R/W 8 C7RID0 0 R/W Transfer request source register ID1 and ID0 for DMA channel 7 (RID) See table 14.3.
PAGE 728
14. Direct Memory Access Controller (DMAC) • DMARS4 Bit Bit Name Initial Value R/W Descriptions 15 C9MID5 0 R/W 14 C9MID4 0 R/W Transfer request source module ID5 to ID0 for DMA channel 9 (MID) 13 C9MID3 0 R/W See table 14.3. 12 C9MID2 0 R/W 11 C9MID1 0 R/W 10 C9MID0 0 R/W 9 C9RID1 0 R/W 8 C9RID0 0 R/W Transfer request source register ID1 and ID0 for DMA channel 9 (RID) See table 14.3.
PAGE 729
14. Direct Memory Access Controller (DMAC) • DMARS5 Bit Bit Name Initial Value R/W Descriptions 15 C11MID5 0 R/W 14 C11MID4 0 R/W Transfer request source module ID5 to ID0 for DMA channel 11 (MID) 13 C11MID3 0 R/W See table 14.3. 12 C11MID2 0 R/W 11 C11MID1 0 R/W 10 C11MID0 0 R/W 9 C11RID1 0 R/W 8 C11RID0 0 R/W Transfer request source register ID1 and ID0 for DMA channel 11 (RID) See table 14.3.
PAGE 730
14. Direct Memory Access Controller (DMAC) Table 14.
PAGE 731
14. Direct Memory Access Controller (DMAC) 14.4 Operation When DMA transfer is requested, the DMAC starts transfer according to the determined channel priority. When the transfer end conditions are satisfied, the DMAC ends transfer. Transfer requests have three modes: auto-request mode, external request mode, and on-chip peripheral module request mode. Bus modes can be chosen from burst mode or cycle steal mode. 14.4.
PAGE 732
14. Direct Memory Access Controller (DMAC) Choose whether DREQ is detected by edge or level with the DREQ level (DL) bit and DREQ select (DS) bit in CHCR0 to CHCR3 shown in table 14.5. The source of the transfer request does not have to be the transfer source or transfer destination. Table 14.
PAGE 733
14. Direct Memory Access Controller (DMAC) (3) On-Chip Peripheral Module Request Mode On-chip peripheral module request mode is a mode that performs transfer by DMA transfer request signal from an on-chip peripheral module. DMA transfer request signals include a transmit data empty transfer request and receive data full transfer request that are from the SCIF0 to SCIF5, HAC0, HAC1, HSPI, SIOF, SSI0, SSI1, and MMCIF set in DMARS0 to DMARS5, and a transfer request from the FLCTL.
PAGE 734
14. Direct Memory Access Controller (DMAC) Table 14.8 List of On-Chip Peripheral Module Request Modes CHCR DMARS RS[3:0] MID 1000 DMA Transfer RID Request Source DMA Transfer Request Signal Source 000000 11 000001 11 001000 01 10 001001 01 10 001010 01 10 001011 01 10 001100 01 10 Bus Destination Mode SSI0 transmitter Transmit data empty request Any (In transmit mode, the DMRQ bit in the SSISR0 register is 1.
PAGE 735
14.
PAGE 736
14. Direct Memory Access Controller (DMAC) 14.4.2 Channel Priority When the DMAC receives transfer requests on two or more channels simultaneously, it transfers data according to a determined priority. Modes are chosen from among fixed mode and roundrobin mode. Modes are selected by bits PR1 and PR0 in DMAOR0 (channels 0 to 5) and DMAOR1 (channels 6 to 11). The relationship between channels 0 to 5 and channels 6 to 11 is round-robin. The priority immediately after reset is CH0 to CH5 > CH6 to CH11.
PAGE 737
14. Direct Memory Access Controller (DMAC) (1) When channel 0 transfers Initial priority order CH0 > CH1 > CH2 > CH3 > CH4 > CH5 Priority order after transfer Channel 0 becomes bottom priority CH1 > CH2 > CH3 > CH4 > CH5 > CH0 (2) When channel 1 transfers Initial priority order Channel 1 becomes bottom priority. The priority of channel 0, which was higher than channel 1, is also shifted.
PAGE 738
14. Direct Memory Access Controller (DMAC) Figure 14.3 shows how the priority changes when channel 0 and channel 3 transfers are requested simultaneously and a channel 1 transfer is requested during the channel 0 transfer. The DMAC operates as follows: 1. Transfer requests are generated simultaneously to channels 0 and 3. 2. As channel 0 has a higher priority, the channel 0 transfer starts (channel 3 is waiting for transfer). 3.
PAGE 739
14. Direct Memory Access Controller (DMAC) 14.4.3 DMA Transfer Types Tables 14.9 and 14.10 show the transfer directions that can be supported by the DMAC. DMA transfer type supports dual address mode. A data transfer timing depends on the bus mode. Bus modes include cycle steal mode and burst mode. Table 14.
PAGE 740
14. Direct Memory Access Controller (DMAC) Table 14.10 DMA Transfer Directions for On-Chip Peripheral Module Request*2*3 Transfer Destination PCIC Space On-Chip Peripheral Module*1 L or U Memory N N Y N N N N Y N PCIC Space N N N Y N On-Chip Peripheral Module*1 Y Y Y Y Y L or U Memory N N N Y N Transfer Source LBSC Space DBSC Space LBSC Space N DBSC Space Legend: Y: Transfer is enabled. N: Transfer is disabled. Notes: 1.
PAGE 741
14. Direct Memory Access Controller (DMAC) (1) Dual Address Mode In dual address mode, both the transfer source and transfer destination are accessed by address. The source and destination can be specified externally or internally. Data is read from the transfer source in a data read cycle and written to the transfer destination in a data write cycle, and two bus cycles are required to execute DMA transfer. At this time, transfer data is temporarily stored in the DMAC.
PAGE 742
14. Direct Memory Access Controller (DMAC) CLKOUT A25 to A0 Transfer source address Transfer destination address CSn D31 to D0 RD WEn DACKn (Active-low) Figure 14.5 Example of DMA Transfer Timing in Dual Address Mode (Source: SRAM, Destination: DDR-SDRAM) Rev.1.00 Jan.
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14. Direct Memory Access Controller (DMAC) (2) Bus Modes Bus modes include cycle steal mode and burst mode. The modes are chosen by the TB and LCKN bits in CHCR. (a) Cycle Steal Mode • Normal mode 1 (CHCR.LCKN = 0, CHCR.TB = 0) In cycle steal normal mode 1, the DMAC gives the SuperHyway bus mastership to another bus master after a one-transfer unit (byte, word, longword, 16-byte, or 32-byte unit).
PAGE 744
14. Direct Memory Access Controller (DMAC) • Intermittent mode 16 (DMAOR. CMS = 10, CHCR.LCKN = 0 or 1, CHCR.TB = 0) • Intermittent mode 64 (DMAOR. CMS = 11, CHCR.LCKN = 0 or 1, CHCR.TB = 0) In intermittent mode of cycle steal, the DMAC gives the SuperHyway bus mastership to other bus master whenever a one-transfer unit (byte, word, longword, or 16-byte or 32-byte unit) is completed.
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14. Direct Memory Access Controller (DMAC) DREQ SuperHyway bus cycle CPU CPU CPU DMAC DMAC DMAC DMAC DMAC DMAC Read Write Read Write Read Write CPU Figure 14.9 DMA Transfer Timing Example in Burst Mode (DREQ Low Level Detection) (3) Bus Mode and Channel Priority Figure 14.10 shows the bus modes and channel priority in priority fixed mode.
PAGE 746
14.
PAGE 747
14. Direct Memory Access Controller (DMAC) 14.4.4 DMA Transfer Flow After intended transfer conditions are set to SAR, DAR, TCR, CHCR, DMAOR, and DMARS, the DMAC transfers data according to the following procedure. 1. Checks if transfer is enabled (DE = 1, DME = 1, TE = 0, AE = 0, NMIF = 0) 2. When a transfer request occurs while transfer is enabled, the DMAC transfers one transfer unit of data (depending on the settings of TS0, TS1, and TS2).
PAGE 748
14.
PAGE 749
14. Direct Memory Access Controller (DMAC) 14.4.5 Repeat Mode Transfer A repeat mode transfer of the DMAC enables a DMA transfer to repeat without specifying the transfer settings before a transfer. Using a repeat mode transfer with the half end function can execute a double buffer transfer virtually. This function can execute the following procedures efficiently. As an example, the operation in receiving voice data from the VOICE CODEC and compressing the data is described.
PAGE 750
14. Direct Memory Access Controller (DMAC) This function enables sequential voice compression by switching a storing buffer for data received consequentially and a data buffer for processing signals alternately. 14.4.6 Reload Mode Transfer In a reload mode transfer, according to the settings of bits RPT in CHCR, the value set in SARB/DARB is reloaded to SAR/DAR at each transfer set in bits 23 to 16 and bits 7 to 0 in TCRB, and the transfer is repeated until TCR is 0 without specifying the transfer again.
PAGE 751
14. Direct Memory Access Controller (DMAC) 14.4.7 DREQ Pin Sampling Timing Figures 14.13 to 14.22 show the timing that the DREQ input is sampled in each bus mode. Figures 14.13, 14.16, and 14.20 show the timing that the DREQ input is sampled when byte transfer is performed in 8-, 16-, 32-, or 64-bit bus width, word transfer is performed in 16-, 32-, or 64-bit bus width, or longword transfer is performed in 32- or 64-bit bus width. DACK is output once in DMA1 transfer. Figures 14.14, 14.17, and 14.
PAGE 752
14. Direct Memory Access Controller (DMAC) CLKOUT Bus cycle CPU 1st acceptance DMAC CPU 2nd acceptance DREQ (Rising edge) DRAK (High-active) DACK (High-active) : Non-sensitive period Acceptance started Accepted after one cycle of CLKOUT at the first rising edge of the divided-up DACK Figure 14.
PAGE 753
14. Direct Memory Access Controller (DMAC) CLKOUT Bus cycle CPU DMAC 1st acceptance CPU 2nd acceptance DREQ (Overrun 0, High level) DRAK (High-active) DACK (High-active) Acceptance started Accepted after one cycle of CLKOUT at the falling edge of DACK CLKOUT Bus cycle CPU 1st acceptance DMAC CPU 2nd acceptance DREQ (Overrun 1, High level) DRAK (High-active) DACK (High-active) : Non-sensitive period Acceptance started Accepted after one cycle of CLKOUT at the rising edge of DACK Figure 14.
PAGE 754
14.
PAGE 755
14.
PAGE 756
14. Direct Memory Access Controller (DMAC) CLKOUT Bus cycle CPU DMAC 1st acceptance 2nd acceptance DREQ (Overrun 0, High level) DRAK (High-active) DACK (High-active) Acceptance started Accepted after one cycle of CLKOUT at the falling edge of DACK CLKOUT Bus cycle CPU 1st acceptance DMAC 2nd acceptance DREQ (Overrun 1, High level) DRAK (High-active) DACK (High-active) : Non-sensitive period Acceptance started Accepted after one cycle of CLKOUT at the rising edge of DACK Figure 14.
PAGE 757
14.
PAGE 758
14.
PAGE 759
14. Direct Memory Access Controller (DMAC) 14.5 DMAC Interrupt Sources In the DMAC, each channel has 14 interrupt sources: a DMA transfer end/half-end interrupts request (DMINT0 to DMINT11), a DMA address error interrupt request (DMAE0) common to channels 0 to 5, and a DMA address error interrupt request (DMAE1) common to channels 6 to 11. Table 14.11 shows each interrupt source. Each interrupt source is independently sent to the interrupt controller. Table 14.
PAGE 760
14. Direct Memory Access Controller (DMAC) 14.6 Usage Notes Note the following things in using this DMAC. 14.6.1 Stopping Modules and Changing Frequency When the DMAC is operating, it is prohibited to set or clear the corresponding bit of MSTPCR1 that controls H-UDI, UBC, DMAC and GDTA modules operation, and also prohibited to change any frequencies regarding the operation of this LSI. Operation is not guaranteed if these are performed.
PAGE 761
14. Direct Memory Access Controller (DMAC) 14.6.6 DACK/DREQ Setting If the IWRRD, IWRRS, and IWW bits in CSnBCR are set to B'000 (no idle cycles), DACK of two or more DMA transfers may be connected. If DACK of two or more DMA transfers is connected, operation is not guaranteed under the following conditions. In these cases, set the IWRRD, IWRRS, and IWW bits to B'001 to B'111 to insert a minimum of one idle cycle between DMA transfers. 1.
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14. Direct Memory Access Controller (DMAC) Rev.1.00 Jan.
PAGE 763
15. Clock Pulse Generator (CPG) Section 15 Clock Pulse Generator (CPG) The CPG generates clocks provided to the internal and external bus interfaces of the SH7785, and controls power-down mode. The CPG consists of a crystal oscillator circuit, PLLs, dividers, and the control unit. 15.1 Features The CPG has the following features.
PAGE 764
15.
PAGE 765
15. Clock Pulse Generator (CPG) The function of each block in the CPG is as follows. • PLL circuit 1 PLL circuit 1 multiplies the input clock frequency on the PLL circuit by 36 or 72. • PLL circuit 2 PLL circuit 2 matches the phases of the bus clock (Bck) and the clock of the CLKOUT pin that is used in the local bus. • Crystal oscillator circuit The crystal oscillator circuit is used when a crystal resonator is connected to the XTAL and EXTAL pins.
PAGE 766
15. Clock Pulse Generator (CPG) 15.2 Input/Output Pins Table 15.1 shows the CPG pin configuration. Table 15.1 CPG Pin Configuration Pin Name Function I/O Description MODE0, MODE1, MODE2, MODE3, 1 and MODE4* Mode Pins 0,1,2,3,4 Input Select the clock operating mode These pins are multiplexed with the following pins.
PAGE 767
15. Clock Pulse Generator (CPG) 15.3 Clock Operating Modes Table 15.2 shows the relationship between setting of the mode pins (MODE0 to MODE4) and the clock operating modes. Table 15.
PAGE 768
15. Clock Pulse Generator (CPG) Table 15.
PAGE 769
15. Clock Pulse Generator (CPG) 15.4 Register Descriptions Table 15.5 lists the registers. Table 15.6 shows the register states in each processing mode. Table 15.
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15. Clock Pulse Generator (CPG) Table 15.
PAGE 771
15. Clock Pulse Generator (CPG) 15.4.1 Frequency Control Register 0 (FRQCR0) FRQCR0 is a 32-bit readable and partially writable register that executes a sequence for changing the frequency of each clock. After the sequence is executed, FRQCR0 is automatically cleared to 0. FRQCR0 can only be accessed in longwords. To write to FRQCR0, set the code value (H'CF) in the upper byte and use the longword. No other code values can be written. The code value is always read as 0.
PAGE 772
15. Clock Pulse Generator (CPG) 15.4.2 Frequency Control Register 1 (FRQCR1) FRQCR1 is a 32-bit readable/writable register that can select the division ratio of divider 2 for the CPU clock (lck), the SuperHyway clock (SHck), the peripheral clock (Pck), the DDR clock (DDRck), the bus clock (Bck), the GDTA clock (GAck), the DU clock (DUck), and the RAM clock (Uck). To check the division ratio of divider 2 for each clock, read FRQMR1. FRQCR1 can only be accessed in longwords.
PAGE 773
15.
PAGE 774
15.
PAGE 775
15. Clock Pulse Generator (CPG) 15.4.3 Frequency Display Register 1 (FRQMR1) FRQMR1 is a 32-bit readable register that reads the division ratio of divider 2 for the CPU clock (lck), the SuperHyway clock (SHck), the peripheral clock (Pck), the DDR clock (DDRck),the bus clock (Bck), the GDTA clock (GAck), the DU clock (DUck), and the RAM clock (Uck). FRQMR1 can only be accessed in longwords. This register is initialized by only a power-on reset via the PRESET pin or a WDT overflow.
PAGE 776
15.
PAGE 777
15. Clock Pulse Generator (CPG) 15.4.4 PLL Control Register (PLLCR) PLLCR is a 32-bit readable/writable register that controls the clock output on the CLKOUT pin. This register can only be accessed in longwords.
PAGE 778
15. Clock Pulse Generator (CPG) 15.5 Calculating the Frequency Table 15.7 shows the relationship between the division ratio of divider 2 described for frequency control register FRQCR1 and frequency display register FRQMR1, and the EXTAL input. Table 15.
PAGE 779
15. Clock Pulse Generator (CPG) 15.6 How to Change the Frequency To change the frequency of the internal clock and the local bus clock (CLKOUT) with software, set frequency control registers FRQCR0 and FRQCR1 according to the following procedure. Tables 15.8 to 15.11 list the selectable combinations of frequencies. 15.6.1 Changing the Frequency of Clocks Other than the Bus Clock When changing the frequency of a clock except the bus clock, disable counting-up by the WDT.
PAGE 780
15. Clock Pulse Generator (CPG) 4. Set H'CF000001 in FRQCR0 to enable execution of the sequence that changes the frequency. The sequence that changes the frequency starts. 5. The CLKOUTENB pin output changes to low level. After ten cycles of the peripheral clock (Pck), an unstable clock is output to the CLKOUT pin. 6. When the oscillation of PLL circuit 2 is stable, wait for ten cycles of the peripheral clock (Pck). Then output a high level signal to the CLKOUTENB pin. 7.
PAGE 781
15. Clock Pulse Generator (CPG) Table 15.
PAGE 782
15.
PAGE 783
15.
PAGE 784
15. Clock Pulse Generator (CPG) Table 15.
PAGE 785
15. Clock Pulse Generator (CPG) Table 15.
PAGE 786
15. Clock Pulse Generator (CPG) 15.7 Notes on Designing Board 1. Note on Using a Crystal Resonator Place the crystal resonator and capacitors close to the EXTAL and XTAL pins as much as possible. No other signal lines should cross the signal line of these pins. Induction may prevent correct oscillation.
PAGE 787
15. Clock Pulse Generator (CPG) RCB1 CB1 SH7785 VDD-PLL1 CPB1 VSS-PLL1 RCB2 CB2 VDDA-PLL1 CPB2 VSSA-PLL1 RCB3 CB3 VDDQ-PLL1 CPB3 VSSQ-PLL1 RCB4 CB4 VDD-PLL2 Power supply 1 CPB4 VSS-PLL2 RCB5 VDDQ-PLL2 CB5 Power supply 2 CPB5 VSSQ-PLL2 Recommended values: RCB1 = RCB2 = RCB3 = RCB4 = RCB5 = 10 Ω CPB1 = CPB2 = CPB3 = CPB4 = CPB5 = 10 μF (Tantalum capacitor) CB1 = CB2 = CB3 = CB4 = CB5 = 0.1 μF Figure 15.5 Note on Using a PLL Oscillator Circuit Rev.1.00 Jan.
PAGE 788
15. Clock Pulse Generator (CPG) Rev.1.00 Jan.
PAGE 789
16. Watchdog Timer and Reset (WDT) Section 16 Watchdog Timer and Reset (WDT) The watchdog timer and reset module (WDT) comprises a reset control unit and a watchdog timer control unit, and controls the power-on reset sequence and internal reset of the LSI. The WDT is a single-channel timer that can be used either as a watchdog timer or interval timer. 16.1 Features • The watchdog timer unit monitors for system runaway using a timer counting at regular time intervals.
PAGE 790
16. Watchdog Timer and Reset (WDT) Figure 16.1 is a block diagram of the WDT.
PAGE 791
16. Watchdog Timer and Reset (WDT) 16.2 Input/Output Pins Table 16.1 shows the pin configuration of the WDT module. Table 16.1 Pin Configuration Pin name Function I/O Description PRESET Power-on reset input Input A low level input to this pin places the LSI in the power-on reset state. MRESETOUT Manual reset output Output Low level is output during manual reset execution. This pin is multiplexed with the IRQOUT (INTC) pin.
PAGE 792
16. Watchdog Timer and Reset (WDT) 16.3 Register Descriptions Table 16.2 shows the registers of the WDT module. Table 16.3 shows the register states in each operating mode. Table 16.
PAGE 793
16. Watchdog Timer and Reset (WDT) 16.3.1 Watchdog Timer Stop Time Register (WDTST) WDTST is a 32-bit readable/writable register that specifies the time until watchdog timer counter WDTCNT overflows. The time until WDTCNT overflows becomes minimum when H'5A00 0001 is set, and maximum when H'5A00 0000 is set. WDTST should be written as a longword unit, with H'5A in the most significant byte. The value read from this byte is always H'00. WDTST is only rest by a power-on reset caused by the PRESET pin.
PAGE 794
16. Watchdog Timer and Reset (WDT) 16.3.2 Watchdog Timer Control/Status Register (WDTCSR) WDTCSR is a 32-bit readable/writable register comprising timer mode-selecting bits and overflow flags. WDTCSR should be written to as a longword unit, with H'A5 in the most significant byte. The value read from this byte is always H'00. WDTCSR is only rest by a power-on reset caused by the PRESET pin.
PAGE 795
16. Watchdog Timer and Reset (WDT) Bit Bit Name Initial Value R/W Description 5 RSTS 0 R/W Reset Select Specifies the type of reset on WDTCNT overflow in watchdog timer mode. This setting is ignored in interval timer mode. 0: Power-on reset 1: Manual reset 4 WOVF 0 R/W Watchdog Timer Overflow Flag Indicates that WDTCNT has overflowed in watchdog timer mode. This flag is not set in interval timer mode. 0: WDTCNT has not overflowed. 1: WDTCNT has overflowed.
PAGE 796
16. Watchdog Timer and Reset (WDT) 16.3.3 Watchdog Timer Base Stop Time Register (WDTBST) WDTBST is a 32-bit readable/writable register that specifies the time until counter WDTBCNT overflows when the bus clock frequency has been changed. The time until WDTBCNT overflows becomes minimum when H'5500 0001 is set, and maximum when H'5500 0000 is set. WDTBST should be written to as a longword unit, with H'55 in the most significant byte. The value read from this byte is always H'00.
PAGE 797
16. Watchdog Timer and Reset (WDT) 16.3.4 Watchdog Timer Counter (WDTCNT) WDTCNT is a 32-bit read-only register comprising a 12-bit counter that is incremented by the WDTBCNT overflow signal. When WDTCNT overflows, a reset of the selected type is initiated in watchdog timer mode, or an interrupt is generated in interval timer mode. WDTCNT is only reset by a power-on reset. Writing to this register is invalid.
PAGE 798
16. Watchdog Timer and Reset (WDT) 16.3.5 Watchdog Timer Base Counter (WDTBCNT) WDTBCNT is a 32-bit read-only register comprising an 18-bit counter that is incremented by the peripheral clock (Pck). When WDTBCNT overflows, WDTCNT is incremented and WDTBCNT is cleared to H'0000 0000. WDTBCNT is only reset by a power-on reset. Writing to this register is invalid.
PAGE 799
16. Watchdog Timer and Reset (WDT) 16.4 Operation 16.4.1 Reset Request Power-on reset and manual reset are available. Their requesting sources are described below. (1) Power-On Reset • Requesting sources ⎯ A low level input on the PRESET pin ⎯ WDTCNT overflow when the WT/IT bit is 1 and the RSTS bit is 0 in WDTCSR ⎯ The H-UDI reset (For details, see section 30, User Debugging Interface (H-UDI)) • Branch address: H'A000 0000 • Operation until branching The exception code H'000 is set in EXPEVT.
PAGE 800
16. Watchdog Timer and Reset (WDT) (2) Manual Reset • Requesting sources ⎯ A general exception other than a user break while the BL bit in SR is set to 1. ⎯ WDTCNT overflow when both the WT/IT and RSTS bits in WDTCSR are set to 1 • Branch address: H'A000 0000 • Operation until branching The exception code H'020 is set in EXPEVT. After initializing VBR and SR, the processing branches by setting PC = H'A000 0000. During initialization, the VBR register is rest to H'0000 0000.
PAGE 801
16. Watchdog Timer and Reset (WDT) 16.4.2 Using Watchdog Timer Mode 1. 2. 3. 4. Set the WDTCNT overflow time in WDTST. Set the WT/IT bit in WDTCSR to 1, and select the type of reset with the RSTS bit. When the TME bit in WDTCSR is set to 1, the WDT counter starts. In watchdog timer mode, clear the WDTCNT or WDTBCNT periodically so that WDTCNT does not overflow. See section 16.4.5, Clearing WDT Counters, for how to clear the WDT counter. 5.
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16. Watchdog Timer and Reset (WDT) 16.4.4 Time until WDT Counters Overflow The relationship between WDTCNT and WDTBCNT is shown in figure 16.2. The example shown in the figure is the operation in interval timer mode, where WDTCNT restarts counting after it has overflowed. In watchdog timer mode, WDTCNT and WDTBCNT are cleared to 0 after the reset state is exited and start counting up again.
PAGE 803
16. Watchdog Timer and Reset (WDT) WDTBCNT is an 18-bit counter that is incremented by the peripheral clock. If the period of peripheral clock Pck is represented as tPck (ns), the overflow time of WDTBCNT is expressed as follows. 218 [bit] × tPck [ns] = 0.262 × tPck [ms] WDTCNT is a 12-bit counter that is incremented each time WDTBCNT overflows. The time until WDTCNT overflows becomes maximum when 0 is written to all the bits in WDTST.
PAGE 804
16. Watchdog Timer and Reset (WDT) 16.5 Status Pin Change Timing during Reset 16.5.1 Power-On Reset by PRESET Pin Since the PLL circuit is initialized when the LSI enters the power-on reset state, the PLL oscillation settling time needs to be ensured. This means that a high level must not be input to the PRESET pin during the PLL oscillation settling time. The PLL oscillation settling time is the sum of the settling times for PLL1 and PLL2.
PAGE 805
16. Watchdog Timer and Reset (WDT) (2) Power-On Reset Caused by PRESET Input during Normal Operation It is necessary to ensure the PLL oscillation settling time when a power-on reset is initiated by low level input on the PRESET pin during normal operation. The timing of reset state indication on the STATUS[1:0] pins is asynchronous.
PAGE 806
16. Watchdog Timer and Reset (WDT) (3) Power-On Reset Caused by PRESET Input in Sleep Mode It is necessary to ensure the PLL oscillation settling time when a power-on reset is initiated by a low level input on the PRESET pin during sleep mode. The timing of reset state indication on the STATUS[1:0] pins is asynchronous. The timing of indicating normal operation is synchronous with the peripheral clock (Pck), and is therefore asynchronous with the clocks input from the EXTAL pin and the CLKOUT pin.
PAGE 807
16. Watchdog Timer and Reset (WDT) 16.5.2 Power-On Reset by Watchdog Timer Overflow The time period taken by power-on reset on watchdog timer overflow (WDT reset holding time) is equal to or more than 40 cycles of the peripheral clock (Pck). The transition time from watchdog timer overflow to the power-on reset state (WDT reset setup time) is equal to or more than 40 cycles of the peripheral clock (Pck).
PAGE 808
16. Watchdog Timer and Reset (WDT) (2) Power-On Reset Caused by Watchdog Timer Overflow in Sleep Mode The timing of indicating the reset state or normal operation on the STATUS[1:0] pins is synchronous with the peripheral clock (Pck), and is therefore asynchronous with the clocks input from the EXTAL pin and the CLKOUT pin.
PAGE 809
16. Watchdog Timer and Reset (WDT) 16.5.3 Manual Reset by Watchdog Timer Overflow The time period taken by manual reset on watchdog timer overflow (WDT manual reset holding time) is equal to or more than 30 cycles of the peripheral clock (Pck). The transition time from watchdog timer overflow to the manual reset state (WDT reset setup time) is equal to or more than eight cycles of the peripheral clock (Pck).
PAGE 810
16. Watchdog Timer and Reset (WDT) (2) Manual Reset Caused by Watchdog Timer Overflow in Sleep Mode The timing of indicating the reset state or normal operation on the STATUS[1:0] pins is synchronous with the peripheral clock (Pck), and is therefore asynchronous with the clocks input from the EXTAL pin and the CLKOUT pin.
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17. Power-Down Mode Section 17 Power-Down Mode In power-down mode, some of the on-chip modules and the CPU are stopped. This enables to reduce power consumption. 17.1 Features • Supports sleep mode, deep sleep mode, and module standby mode • Supports DDR2-SDRAM power supply backup mode that turns off the power supplies the 1.8V power supply 17.1.1 Types of Power-Down Modes Power-down modes have the following modes and functions.
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17. Power-Down Mode Table 17.1 States of Power-Down Modes State PowerDown On-Chip Conditions of Mode Transition CPG Sleep mode SLEEP instruction executed (see section 17.4) Operate Memory CPU Stopped Retained (contents of registers retained) On-Chip Peripheral Module Releasing DMAC GDTA Others Pin DDR2-SDRAM Methods Operate Operate Operate Operation retained Auto-refresh or self-refresh*3 1. Interrupt 2. Power-on reset 3.
PAGE 813
17. Power-Down Mode 17.2 Input/Output Pins Table 17.2 shows the pins related to power-down mode. Table 17.2 Pin Configuration Pin name Function I/O Description STATUS1 Processing state 1 Output Indicate the operating states of this LSI STATUS0 Processing state 2 STATUS1 STATUS0 Operating states H H Reset H L Sleep mode L L Normal operation The STATUS1 pin is multiplexed with the DRAK1 (DMAC) and PK6 (GPIO) pins.
PAGE 814
17. Power-Down Mode Table 17.4 Register States of CPG in Each Processing Mode Register Name Abbreviation Standby control register 0*1 MSTPCR0 1 Standby control register 1* MSTPCR1 Standby display register MSTPMR Power-on Reset Sleep/ Manual Reset Deep Sleep By PRESET Pin/WDT/H-UDI By WDT By SLEEP Instruction H'0000 0000 Retained Retained Retained Retained Retained Retained H'0000 0000 2 H'00x0 0000∗ Notes: 1. For details of MSTPCR0 and MSTPCR1, see figure 15.1. 2.
PAGE 815
17. Power-Down Mode 17.3.1 Sleep Control Register (SLPCR) SLPCR is a 32-bit readable/writable register that can specify transition to deep sleep mode. SLPCR can be accessed only in longword. This register is initialized by a power-on reset by the PRESET pin or power-on reset by WDT overflow, or H-UDI reset.
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17. Power-Down Mode 17.3.2 Standby Control Register 0 (MSTPCR0) MSTPCR0 is a 32-bit readable/writable register that can specify whether each peripheral module operates or is stopped. MSTPCR can be accessed only in longword. This register is initialized by a power-on reset by the PRESET pin or power-on reset by WDT overflow, or H-UDI reset.
PAGE 817
17. Power-Down Mode Bit Bit Name Initial Value R/W Description 21, 20 MSTP[21:20] All 0 R/W Module Stop Bit [21:20] Specify that the clock supply to the module of the corresponding bit is stopped [21]: SSI channel 1, [20]: SSI channel 0 0: The corresponding module operates 1: The clock to the corresponding module is stopped 19, 18 ⎯ All 0 R/W Reserved These bits are always read as 0. The write value should always be 0.
PAGE 818
17. Power-Down Mode Bit Bit Name Initial Value R/W Description 9, 8 MSTP[9:8] All 0 R/W Module Stop Bit [9:8] Specify that the clock supply to the module of the corresponding bit is stopped [9]: TMU channels 3 to 5 [8]: TMU channels 2 to 0 0: The corresponding module operates 1: The clock to the corresponding module is stopped 7 to 4 ⎯ All 0 R/W Reserved These bits are always read as 0. The write value should always be 0.
PAGE 819
17. Power-Down Mode 17.3.3 Standby Control Register 1 (MSTPCR1) MSTPCR1 is a 32-bit readable/writable register that each module of H-UDI, UBC, DMAC, and GDTA operates or is stopped. MSTPCR1 can be accessed only in longword. This register is initialized by a power-on reset by the PRESET pin or power-on reset by WDT overflow, or H-UDI reset.
PAGE 820
17. Power-Down Mode Bit Bit Name Initial Value R/W Description 16 to 6 ⎯ All 0 R/W Reserved These bits are always read as 0. The write value should always be 0. 5, 4 MSTP [105:104] All 0 R/W Module Stop Bit [105:104] Specifies that the clock supply to the DMAC channels of the corresponding bit is stopped MSTP105: DMAC channels 11 to 6, MSTP104: DMAC channels 5 to 0 0: DMAC operates 1: DMAC stopped ⎯ 3 to 1 All 0 R/W Reserved These bits are always read as 0.
PAGE 821
17. Power-Down Mode 17.3.4 Standby Display Register (MSTPMR) MSTPMR is a 32-bit readable register that indicates whether the PCIC/display unit (DU)/DMAC/GDTA modules are in the module standby state. MSTPMR can be accessed only in longword. This register is initialized by a power-on reset by the PRESET pin, power-on reset by WDT overflow, or H-UDI reset.
PAGE 822
17. Power-Down Mode Bit Bit Name 5, 4 MSTPS105 MSTPS104 Initial Value R/W Description All 0 R Module Stop Display Bit 105, 104 Indicates the state of clock supply to the DMAC channels of the corresponding bit MSTPS105: DMAC channels 11 to 6 MSTPS104: DMAC channels 5 to 0 0: The DMAC channels operate 1: The DMAC channels stopped 3 to 1 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0.
PAGE 823
17. Power-Down Mode 17.4 Sleep Mode 17.4.1 Transition to Sleep Mode When the SLEEP instruction is executed, the state is changed from the program execution state to sleep mode. Although the CPU is stopped after the instruction is executed, the contents of the CPU register are retained. On-chip modules other than the CPU continue to operate. The clock is output to the CLKOUT pin. In sleep mode, a high level signal is output to the STATUS1 pin, and a low level signal is output to the STATUS0 pin.
PAGE 824
17. Power-Down Mode 17.5 Deep Sleep Mode 17.5.1 Transition to Deep Sleep Mode If a SLEEP instruction is executed when the DSLP bit in SLPCR is set to 1, the chip switches from the program execution state to deep sleep mode. The procedure for a transition to deep sleep mode is as follows: 1. Make each modules stop by setting standby control registers MSTPCR0 and MSTPCR1 except the H-UDI module, i.e. write H’3F33 330C to MSTPCR0 and write H’0002 0031 to MSTPCR1.
PAGE 825
17. Power-Down Mode 17.5.2 Releasing Deep Sleep Mode Deep sleep mode is released by means of an interrupt (NMI, IRL, IRQ, GPIO, WDT interval timer, or H-UDI) or a reset. In deep sleep mode, an interrupt request is accepted even if the BL bit in SR is set to 1. The SPC, SSR and other related contents should be saved before execute a SLEEP instruction if necessary.
PAGE 826
17. Power-Down Mode 17.6 Module Standby Functions This LSI supports the module standby state, where the clock supplied to on-chip modules is stopped. 17.6.1 Transition to Module Standby Mode By setting the MSTP bits in MSPTCR, the clock supply can be stopped to the corresponding module*. In each module that is in the module standby state, the state right before transition to module standby state is retained. After register setting, the state right before stop is retained.
PAGE 827
17. Power-Down Mode 17.7 Timing of the Changes on the STATUS Pins 17.7.1 Reset For details, see section 16.5, Status Pin Change Timing during Reset. 17.7.2 (1) Releasing Sleep Mode When Sleep Mode Is Released by an Interrupt Figure 17.1 shows the timing of the changes in the STATUS pin. Interrupt request CLKOUT IRQOUT output STATUS[1:0] output LL (Normal) HL (Sleep) LL (Normal) Figure 17.1 Status Pins Output when an Interrupt Occurs in Sleep Mode 17.
PAGE 828
17. Power-Down Mode Rev.1.00 Jan.
PAGE 829
18. Timer Unit (TMU) Section 18 Timer Unit (TMU) This LSI includes an on-chip 32-bit timer unit (TMU), which has six channels (channels 0 to 5). 18.1 Features The TMU has the following features.
PAGE 830
18. Timer Unit (TMU) Figure 18.1 shows a block diagram of the TMU.
PAGE 831
18. Timer Unit (TMU) 18.2 Input/Output Pins Table 18.1 shows the TMU pin configuration. Table 18.1 Pin Configuration Pin Name Abbrev. I/O Description Clock input TCLK Input External clock input pin for channels 0, 1 and 2 /input capture control input pin for channel 2 Rev.1.00 Jan.
PAGE 832
18. Timer Unit (TMU) 18.3 Register Descriptions Tables 18.2 and 18.3 show the TMU register configuration. Table 18.2 Register Configuration (1) Register Name Abbrev.
PAGE 833
18. Timer Unit (TMU) Table 18.3 Register Configuration (2) Channel Register Name Abbrev.
PAGE 834
18. Timer Unit (TMU) 18.3.1 Timer Start Registers (TSTRn) (n = 0, 1) The TSTR registers are 8-bit readable/writable registers that specifies whether TCNT of the corresponding channel is operated or stopped. • TSTR0 BIt: Initial value: R/W: 7 6 5 4 3 — — — — — 0 R 0 R 0 R 0 R 0 R Bit Bit Name Initial Value R/W 7 to 3 — All 0 R 2 1 0 STR2 STR1 STR0 0 R/W 0 R/W 0 R/W Description Reserved These bits are always read as 0. The write value should always be 0.
PAGE 835
18. Timer Unit (TMU) • TSTR1 BIt: Initial value: R/W: 7 6 5 4 3 — — — — — 0 R 0 R 0 R 0 R 0 R Bit Bit Name Initial Value R/W 7 to 3 — All 0 R 2 1 0 STR5 STR4 STR3 0 R/W 0 R/W 0 R/W Description Reserved These bits are always read as 0. The write value should always be 0. 2 STR5 0 R/W Counter Start 5 Specifies whether TCNT5 is operated or stopped.
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18. Timer Unit (TMU) 18.3.2 Timer Constant Registers (TCORn) (n = 0 to 5) The TCOR registers are 32-bit readable/writable registers. When a TCNT counter underflows while counting down, the TCOR value is set in that TCNT, which continues counting down from the set value. BIt: Initial value: R/W: BIt: Initial value: R/W: 18.3.
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18. Timer Unit (TMU) 18.3.4 Timer Control Registers (TCRn) (n = 0 to 5) The TCR registers are 16-bit readable/writable registers. Each TCR selects the count clock, specifies the edge when an external clock is selected, and controls interrupt generation when the flag indicating TCNT underflow is set to 1. TCR2 is also used for input capture control and control of interrupt generation in the event of input capture.
PAGE 838
18. Timer Unit (TMU) Bit 7 6 Initial Value R/W Description 1 0 R/W Input Capture Control 1 0 R/W These bits, provided in channel 2 only, specify whether the input capture function is used, and control enabling or disabling of interrupt generation when the function is used. Bit Name ICPE1* ICPE0* The CKEG bits specify whether the rising edge or falling edge of the TCLK pin is used to set the TCNT2 value in TCPR2. The TCNT2 value is set in TCPR2 only when the ICPF bit in TCR2 is 0.
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18. Timer Unit (TMU) Bit Bit Name Initial Value R/W Description 2 TPSC2 0 R/W Timer Prescaler 2 to 0 1 TPSC1 0 R/W These bits select the TCNT count clock. 0 TPSC0 0 R/W 000: Counts on Pck/4 001: Counts on Pck/16 010: Counts on Pck/64 011: Counts on Pck/256 100: Counts on Pck/1024 101, 110: Setting prohibited 111: Counts on external clock (TCLK) *3 Legend: X: Don't care Notes: 1. Reserved bit in channels 0 to 5 (initial value is 0, and can only be read). 2.
PAGE 840
18. Timer Unit (TMU) 18.4 Operation Each channel has a 32-bit timer counter (TCNT) and a 32-bit timer constant register (TCOR). Each TCNT performs count-down operation. The channels have an auto-reload function that allows cyclic count operations, and can also perform external event counting. Channel 2 also has an input capture function. 18.4.1 Counter Operation When one of bits STR0 to STR2 in TSTR is set to 1, the TCNT for the corresponding channel starts counting.
PAGE 841
18. Timer Unit (TMU) (2) Auto-Reload Count Operation Figure 18.3 shows the TCNT auto-reload operation. TCNT value TCOR value is set in TCNT on underflow TCOR H'0000 0000 Time STR0 to STR5 UNF Figure 18.3 TCNT Auto-Reload Operation Rev.1.00 Jan.
PAGE 842
18. Timer Unit (TMU) (3) TCNT Count Timing • Operating on internal clock Any of five internal count clocks (Pck/4, Pck/16, Pck/64, Pck/256, or Pck/1024) scaled from the peripheral clock can be selected as the count clock by means of the TPSC2 to TPSC0 bits in TCR. Figure 18.4 shows the timing in this case. Pck Internal clock TCNT N+1 N N–1 Figure 18.
PAGE 843
18. Timer Unit (TMU) 18.4.2 Input Capture Function Channel 2 has an input capture function. The procedure for using the input capture function is as follows: 1. Use bits TPSC2 to TPSC0 in TCR2 to set an internal clock as the timer operating clock. 2. Use bits IPCE1 and IPCE0 in TCR2 to specify use of the input capture function, and whether interrupts are to be generated when this function is used. 3.
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18. Timer Unit (TMU) 18.5 Interrupts There are seven TMU interrupt sources: underflow interrupts and the input capture interrupt when the input capture function is used. Underflow interrupts are generated on each of the channels, and input capture interrupts on channel 2 only. An underflow interrupt request is generated (for each channel) when both the UNF bit and the interrupt enable bit (UNIE) for that channel are set to 1.
PAGE 845
18. Timer Unit (TMU) 18.6 Usage Notes 18.6.1 Register Writes When writing to a TMU register, timer count operation must be stopped by clearing the start bit (STR5 to STR0) for the relevant channel in TSTR. Note that TSTR can be written to, and the UNF and ICPF bits in TCR can be cleared while the count is in progress. When the flags (UNF and ICPF) are cleared while the count is in progress, make sure not to change the values of bits other than those being cleared. 18.6.
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18. Timer Unit (TMU) Rev.1.00 Jan.
PAGE 847
19. Display Unit (DU) Section 19 Display Unit (DU) 19.1 Features The display unit (DU) has the following features. Plane: The display surfaces normally called the foreground, background, and cursor, are called planes in this section. Parameters for each plane can be set independently through the settings of an internal register. The internal register settings can also be used to set the display priority order.
PAGE 848
19. Display Unit (DU) CRT Scan Mode (CRT Scan Method): Internal register settings can be used to select from among three scan modes. • Non-interlaced mode • Interlaced sync mode • Interlaced sync & video mode YC→RGB Colorspace Conversion Functions: Image data stored in YC format can be converted into the RGB colorspace and displayed in a window. (However, when multiple planes are specified for YC → RGB conversion, the YC → RGB conversion can be performed only for pixels in the uppermost plane.
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SHwy clock area SHck 1 pixel division Transparent color determination 1 pixel division Transparent color determination 1 pixel division Transparent color determination Buffer-4 (128B x 3) Buffer-5 (128B x 3) SHwy interface Buffer-6 (128B x 3) Color palette contention determination Display data format selection Display timing generation YC to RGB conversion Color palette 4 (26b x 256w) Color palette 3 (26b x 256w) Color palette 2 (26b x 256w) Color palette 1 (26b x 256w) 16 bit/pixel (no convers
PAGE 850
19. Display Unit (DU) 19.2 Input/Output Pins Table 19.1 shows the pin configuration of the display unit (DU). Table 19.
PAGE 851
19. Display Unit (DU) Pin Name Number I/O DG5 1 Output Digital green 5 DB0 1 Output Digital blue 0 DB1 1 Output Digital blue 1 DB2 1 Output Digital blue 2 DB3 1 Output Digital blue 3 DB4 1 Output Digital blue 4 DB5 1 Output Digital blue 5 Signal Name Used in This Section Function Note: In this section, unless otherwise noted, "dot clock" refers to the output dot clock. 19.3 Register Descriptions Register update methods include external update and internal update.
PAGE 852
19.
PAGE 853
19. Display Unit (DU) Table 19.2 Register Configuration Register Name Abbr.
PAGE 854
19. Display Unit (DU) Register Name Abbr.
PAGE 855
19. Display Unit (DU) Register Name Abbr.
PAGE 856
19. Display Unit (DU) Register Name Abbr.
PAGE 857
19. Display Unit (DU) Register Name Abbr.
PAGE 858
19. Display Unit (DU) Register Name Abbr.
PAGE 859
19. Display Unit (DU) Register Name Abbr.
PAGE 860
19. Display Unit (DU) Table 19.3 Status of Registers in Each Processing Mode Register Name Abbr.
PAGE 861
19. Display Unit (DU) Register Name Abbr.
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19. Display Unit (DU) Register Name Abbr.
PAGE 863
19. Display Unit (DU) Register Name Abbr.
PAGE 864
19. Display Unit (DU) Register Name Abbr.
PAGE 865
19. Display Unit (DU) Register Name Abbr.
PAGE 866
19.
PAGE 867
19. Display Unit (DU) Register Name Abbr.
PAGE 868
19. Display Unit (DU) Register Name Abbr.
PAGE 869
19. Display Unit (DU) Register Name Abbr.
PAGE 870
19. Display Unit (DU) Register Name Abbr.
PAGE 871
19. Display Unit (DU) 19.3.1 Display Unit System Control Register The display unit system control register (DSYSR) sets the system operation for the display unit (DU).
PAGE 872
19. Display Unit (DU) Bit Bit Name Initial Value R/W Internal Update Description 16 IUPD 0 R/W Yes Internal Updating Disable When DRES = 1, internal update is performed regardless of this bit. For details of internal update, see (2) Internal Update in section 19.3, Register Descriptions. 0: Internal update is performed upon each vertical sync signal (VSYNC) assertion 1: By setting this bit to 1, internal updates can be prohibited.
PAGE 873
19. Display Unit (DU) Bit Bit Name Initial Value R/W Internal Update Description 9 DRES 1 R/W None Display Reset 8 DEN 0 R/W Yes Display Enable 00: Starts display synchronization operation. In the case of a register not yet set, unexpected operation may occur; hence DRES should be set to 0 after setting all the registers in the display unit (DU). When DEN = 0, the display data is the value set in the display-off output register (DOOR). 01: Starts display synchronization operation.
PAGE 874
19. Display Unit (DU) Bit Bit Name Initial Value R/W Internal Update Description 7, 6 TVM 10 R/W None TV Synchronization Mode 00: Master mode HSYNC, VSYNC, CSYNC are output 01: Synchronization method switching mode When switching from TV sync mode to master mode, or from master mode to TV sync mode, is necessary, the switching should pass through this mode. In this mode, operation of the display system is forcibly halted, and DISP outputs a low level signal.
PAGE 875
19. Display Unit (DU) 19.3.2 Display Mode Register (DSMR) The display mode register (DSMR) sets the display operation of the display unit.
PAGE 876
19. Display Unit (DU) Bit Bit Name Initial Value R/W Internal Update Description 24 CSPM 0 R/W * CSYNC Pin Mode Settings in DSYSR are given priority over settings in this register. 0: CSYNC signal is output to the HSYNC pin 1: HSYNC signal is output to the HSYNC pin 23 to 20 ⎯ All 0 R ⎯ Reserved These bits are always read as 0. The write value should always be 0.
PAGE 877
19.
PAGE 878
19. Display Unit (DU) Bit Bit Name Initial Value R/W Internal Update Description 7, 6 CSY 00 R/W None CSYNC Mode For details of CSYNC waveform, refer to section 19.5.2, CSYNC. 00: The relation among VSYNC, HSYNC, and CSYNC is as follows.
PAGE 879
19. Display Unit (DU) 19.3.3 Display Status Register (DSSR) The display status register (DSSR) is a register used to read, from outside, the internal state of the display unit (DU).
PAGE 880
19.
PAGE 881
19.
PAGE 882
19. Display Unit (DU) Bit Bit Name Initial Value R/W Internal Update Description 13, 12 ⎯ All 0 R ⎯ Reserved These bits are always read as 0. The write value should always be 0. 11 VBK 0 R None Vertical Blanking Flag 0: Indicates the interval to the next display end after clearing to 0 the VBK bit using either the DRES bit in DSYSR or the VBCL bit in DSRCR.
PAGE 883
19. Display Unit (DU) 19.3.4 Display Unit Status Register Clear Register (DSRCR) The display unit status register clear register (DSRCR) is a register which clears the various flags in DSSR.
PAGE 884
19. Display Unit (DU) Bit Bit Name 9 RICL Initial Value R/W Undefined W Internal Update Description None Vertical Blanking Flag Clear 0: The RINT flag in DSSR is not changed. 1: The RINT flag in DSSR is cleared to 0. 8 HBCL Undefined W None Vertical Blanking Flag Clear 0: The HBK flag in DSSR is not changed. 1: The HBK flag in DSSR is cleared to 0. 7 to 0 ⎯ All 0 ⎯ R Reserved These bits are always read as 0. The write value should always be 0. 19.3.
PAGE 885
19. Display Unit (DU) Bit Bit Name 31 to 16 ⎯ Initial Value R/W Internal Update Description All 0 R ⎯ Reserved These bits are always read as 0. The write value should always be 0.
PAGE 886
19. Display Unit (DU) The following are conditions, based on DSSR and this register, for issuing an interrupt to the CPU from the display unit (DU).
PAGE 887
19. Display Unit (DU) 19.3.6 Color Palette Control Register (CPCR) The color palette control register (CPCR) is a register which enables switching of the color palette. For information on color palette switching, refer to section 19.4.8, Color Palettes.
PAGE 888
19. Display Unit (DU) Bit Bit Name Initial Value R/W Internal Update Description 18 CP3CE 0 R/W Yes Color Palette 3 Change Enable 0: Switching of color palette 3 is not performed. 1: Switching of color palette 3 is performed. Switching is performed when the DRES bit in DSYSR is changed from 1 to 0, or with the timing of an internal update. This bit can only be set to 1; an operation to set the bit to 0 is invalid. After switching of the color palette 3, the bit is cleared to 0.
PAGE 889
19. Display Unit (DU) 19.3.7 Display Plane Priority Register (DPPR) The display plane priority register (DPPR) sets the priority order for combining planes and turns the display on and off.
PAGE 890
19.
PAGE 891
19.
PAGE 892
19. Display Unit (DU) 19.3.8 Display Unit Extensional Function Enable Register (DEFR) The display unit extensional function enable register (DEFR) enables extension functions. DEFR should be set during display reset (the DRES bit and DEN bit in DSYSR should be set to 1 and to 0 respectively) for external updates. If update is performed during display, the display may flicker.
PAGE 893
19. Display Unit (DU) Bit Bit Name Initial Value R/W Internal Update Description 4 ABRE 0 R/W None Alpha Blend Ratio Enable 0: The 31 to 24 bits in the color palette registers 1 to 4 and the PnBRSL bits in the plane n blend ratio registers (PnALPHAR) are disabled. The alpha blend ratio is set only by the PnALPHA bits PnALPHAR. 1: The 31 to 24 bits in the color palette registers 1 to 4 and the PnBRSL bits in PnALPHAR are enabled. • The following can be selected as the alpha blend ratio.
PAGE 894
19. Display Unit (DU) 19.3.9 Horizontal Display Start Register (HDSR) The horizontal display start register (HDSR) sets the horizontal display start position. The value is retained during power-on reset and manual reset.
PAGE 895
19. Display Unit (DU) 19.3.10 Horizontal Display End Register (HDER) The horizontal display end register (HDER) sets the horizontal display end position. The value is retained during power-on reset and manual reset.
PAGE 896
19. Display Unit (DU) 19.3.11 Vertical Display Start Register (VDSR) The vertical display start register (VDSR) sets the vertical display start position. The value is retained during power-on reset and manual reset.
PAGE 897
19. Display Unit (DU) 19.3.12 Vertical Display End Register (VDER) The vertical display end register (VDER) sets the vertical display end position. The value is retained during power-on reset and manual reset.
PAGE 898
19. Display Unit (DU) 19.3.13 Horizontal Cycle Register (HCR) The horizontal cycle register (HCR) sets the horizontal scan cycle.(period). The value is retained during power-on reset and manual reset.
PAGE 899
19. Display Unit (DU) 19.3.14 Horizontal Sync Width Register (HSWR) The horizontal sync width register (HSWR) sets the low-level pulse width of the horizontal sync signal. The value is retained during power-on reset and manual reset.
PAGE 900
19. Display Unit (DU) 19.3.15 Vertical Cycle Register (VCR) The vertical cycle register (VCR) sets the vertical scan interval. The value is retained during power-on reset and manual reset.
PAGE 901
19. Display Unit (DU) 19.3.16 Vertical Sync Point Register (VSPR) The vertical sync point register (VSPR) sets the start position of the vertical sync signal in raster line units. The value is retained during power-on reset and manual reset.
PAGE 902
19. Display Unit (DU) 19.3.17 Equal Pulse Width Register (EQWR) The equal pulse width register (EQWR) sets the low-level pulse width of a pulse equivalent to the CSYNC signal. The value is retained during power-on reset and manual reset.
PAGE 903
19. Display Unit (DU) 19.3.18 Separation Width Register (SPWR) The separation width register (SPWR) sets the low-level pulse width of the separation pulse for the CSYNC signal. The value is retained during power-on reset and manual reset.
PAGE 904
19. Display Unit (DU) 19.3.19 CLAMP Signal Start Register (CLAMPSR) The CLAMP signal start register (CLAMPSR) sets the rising edge position of the CLAMP signal. For timing charts for the CLAMP signal and the DE signal, refer to section 19.5.6, CLAMP Signal and DE Signal. The value is retained during power-on reset and manual reset.
PAGE 905
19. Display Unit (DU) 19.3.20 CLAMP Signal Width Register (CLAMPWR) The CLAMP signal width register (CLAMPWR) sets the high-level width of the CLAMP signal. The value is retained during power-on reset and manual reset.
PAGE 906
19. Display Unit (DU) 19.3.21 DE Signal Start Register (DESR) The DE signal start register (DESR) sets the rising edge position of the DE signal. The value is retained during power-on reset and manual reset.
PAGE 907
19. Display Unit (DU) 19.3.22 DE Signal Width Register (DEWR) The DE signal width register (DEWR) sets the high-level width of the DE signal. The value is retained during power-on reset and manual reset.
PAGE 908
19. Display Unit (DU) 19.3.23 Color Palette 1 Transparent Color Register (CP1TR) The color palette 1 transparent color register (CP1TR) specifies the transparent color for color palette 1.
PAGE 909
19. Display Unit (DU) Bit Bit Name Initial Value R/W Internal Update Description 12 CP1IC 0 R/W Yes Color Palette 1 Index C 0: The color with index C in color palette 1 is not set to the transparent color. 1: The color with index C in color palette 1 is set to the transparent color. 11 CP1IB 0 R/W Yes Color Palette 1 Index B 0: The color with index B in color palette 1 is not set to the transparent color. 1: The color with index B in color palette 1 is set to the transparent color.
PAGE 910
19. Display Unit (DU) Bit Bit Name Initial Value R/W Internal Update Description 5 CP1I5 0 R/W Yes Color Palette 1 Index 5 0: The color with index 5 in color palette 1 is not set to the transparent color. 1: The color with index 5 in color palette 1 is set to the transparent color. 4 CP1I4 0 R/W Yes Color Palette 1 Index 4 0: The color with index 4 in color palette 1 is not set to the transparent color. 1: The color with index 4 in color palette 1 is set to the transparent color.
PAGE 911
19. Display Unit (DU) 19.3.24 Color Palette 2 Transparent Color Register (CP2TR) The color palette 2 transparent color register (CP2TR) specifies the transparent color of color palette 2.
PAGE 912
19. Display Unit (DU) Bit Bit Name Initial Value R/W Internal Update Description 12 CP2IC 0 R/W Yes Color Palette 2 Index C 0: The color with index C in color palette 2 is not set to the transparent color. 1: The color with index C in color palette 2 is set to the transparent color. 11 CP2IB 0 R/W Yes Color Palette 2 Index B 0: The color with index B in color palette 2 is not set to the transparent color. 1: The color with index B in color palette 2 is set to the transparent color.
PAGE 913
19. Display Unit (DU) Bit Bit Name Initial Value R/W Internal Update Description 5 CP2I5 0 R/W Yes Color Palette 2 Index 5 0: The color with index 5 in color palette 2 is not set to the transparent color. 1: The color with index 5 in color palette 2 is set to the transparent color. 4 CP2I4 0 R/W Yes Color Palette 2 Index 4 0: The color with index 4 in color palette 2 is not set to the transparent color. 1: The color with index 4 in color palette 2 is set to the transparent color.
PAGE 914
19. Display Unit (DU) 19.3.25 Color Palette 3 Transparent Color Register (CP3TR) The color palette 3 transparent color register (CP3TR) specifies the transparent color of color palette 3.
PAGE 915
19. Display Unit (DU) Bit Bit Name Initial Value R/W Internal Update Description 12 CP3IC 0 R/W Yes Color Palette 3 Index C 0: The color with index C in color palette 3 is not set to the transparent color. 1: The color with index C in color palette 3 is set to the transparent color. 11 CP3IB 0 R/W Yes Color Palette 3 Index B 0: The color with index B in color palette 3 is not set to the transparent color. 1: The color with index B in color palette 3 is set to the transparent color.
PAGE 916
19. Display Unit (DU) Bit Bit Name Initial Value R/W Internal Update Description 5 CP3I5 0 R/W Yes Color Palette 3 Index 5 0: The color with index 5 in color palette 3 is not set to the transparent color. 1: The color with index 5 in color palette 3 is set to the transparent color. 4 CP3I4 0 R/W Yes Color Palette 3 Index 4 0: The color with index 4 in color palette 3 is not set to the transparent color. 1: The color with index 4 in color palette 3 is set to the transparent color.
PAGE 917
19. Display Unit (DU) 19.3.26 Color Palette 4 Transparent Color Register (CP4TR) The color palette 4 transparent color register (CP4TR) specifies the transparent color of color palette 4.
PAGE 918
19. Display Unit (DU) Bit Bit Name Initial Value R/W Internal Update Description 12 CP4IC 0 R/W Yes Color Palette 4 Index C 0: The color with index C in color palette 4 is not set to the transparent color. 1: The color with index C in color palette 4 is set to the transparent color. 11 CP4IB 0 R/W Yes Color Palette 4 Index B 0: The color with index B in color palette 4 is not set to the transparent color. 1: The color with index B in color palette 4 is set to the transparent color.
PAGE 919
19. Display Unit (DU) Bit Bit Name Initial Value R/W Internal Update Description 5 CP4I5 0 R/W Yes Color Palette 4 Index 5 0: The color with index 5 in color palette 4 is not set to the transparent color. 1: The color with index 5 in color palette 4 is set to the transparent color. 4 CP4I4 0 R/W Yes Color Palette 4 Index 4 0: The color with index 4 in color palette 4 is not set to the transparent color. 1: The color with index 4 in color palette 4 is set to the transparent color.
PAGE 920
19. Display Unit (DU) 19.3.27 Display Off Mode Output Register (DOOR) The display off mode output register (DOOR) sets the display data output when the display is turned off. The value is retained during power-on reset and manual reset.
PAGE 921
19. Display Unit (DU) 19.3.28 Color Detection Register (CDER) The color detection register (CDER) sets the color for color detection. When the display output data match the settings of this register, high level is output from the CDE pin. For information on the output color data format, please refer to section 19.4.6, Output Data Format. The value is held during power-on reset and manual reset.
PAGE 922
19. Display Unit (DU) Bit Bit Name 1, 0 ⎯ Initial Value All 0 R/W Internal Update Description R ⎯ Reserved These bits are always read as 0. The write value should always be 0. 19.3.29 Background Plane Output Register (BPOR) The background plane output register (BPOR) sets the color for display when there is no plane for display, due to the display size or to a transparent color, etc. For detailed conditions, refer to section 19.4.2, Display On/Off.
PAGE 923
19. Display Unit (DU) Bit Initial Bit Name Value R/W Internal Update Description 9, 8 ⎯ R ⎯ All 0 Reserved These bits are always read as 0. The write value should always be 0. 7 to 2 BPOB Undefined R/W Yes Background Plane Output Blue The blue-color display data to be output when there is no plane for display should be set. 1, 0 ⎯ All 0 R ⎯ Reserved These bits are always read as 0. The write value should always be 0. Rev.1.00 Jan.
PAGE 924
19. Display Unit (DU) 19.3.30 Raster Interrupt Offset Register (RINTOFSR) The raster interrupt offset register (RINTOFSR) sets the raster offset value for raster interrupts. The value is retained during power-on reset and manual reset.
PAGE 925
19. Display Unit (DU) 19.3.31 Plane n Mode Register (PnMR) (n = 1 to 6) The plane n mode registers (PnMR, n = 1 to 6) set the display operation for plane n.
PAGE 926
19. Display Unit (DU) Bit Bit Name 14 to 12 PnSPIM Initial Value R/W Internal Update Description 0 R/W Yes Plane n Super Impose Mode 000: Transparent color processing is performed for plane n. When plane n is in the transparent color, the lower plane is displayed. 001: Blending of plane n and the lower plane is performed. When plane n is the transparent color blending is not performed, and the lower plane is displayed. 010: An EOR operation is performed on plane n and the lower plane.
PAGE 927
19. Display Unit (DU) Bit Bit Name Initial Value R/W Internal Update Description 9, 8 PnCPSL 0 R/W Yes Plane n Color Palette Select When the PnDDF bit is set to 8 bits/pixel, specifies the color palette to be used. 00: Selects the color palette 1 01: Selects the color palette 2 10: Selects the color palette 3 11: Selects the color palette 4 7 PnDC 0 R/W Yes Plane n Display Area Change Controls switching of the frame buffer in manual display change mode.
PAGE 928
19. Display Unit (DU) 19.3.32 Plane n Memory Width Register (PnMWR) (n = 1 to 6) The plane n memory width registers (PnMWR, n = 1 to 6) set the memory width for plane n. The value is retained during power-on reset and manual reset.
PAGE 929
19. Display Unit (DU) 19.3.33 Plane n Blending Ratio Register (PnALPHAR) (n = 1 to 6) The plane n blending ratio registers (PnALPHAR, n = 1 to 6) set the blend ratios and blend ratio selection for plane n.
PAGE 930
19. Display Unit (DU) Bit Initial Bit Name Value Internal R/W Update Description 9, 8 PnBRSL R/W Yes 0 Plane n Blending Ratio Select This bit is valid when the following two conditions are satisfied. • When the PnSPIM bit in PnMR specifies blending. • When the ABRE bit in DEFR is set to 1. 00: The PnALPHA bits in this register are taken to be the blend ratio. 01: Setting prohibited 10: Bits 31 to 24 of the color palette register specified by the PnCPSL bit in PnMR are taken to be the blend ratio.
PAGE 931
19. Display Unit (DU) Bit Initial Bit Name Value 7 to 0 PnALPHA R/W Undefined R/W Internal Update Description Yes Plane n Blending Ratio The alpha value (α) which is the blend ratio for plane n should be set. Blending result = (α × plane n + (H'100 − α) × lower plane)/ H'100 Note: Blending result, α, plane n, and lower plane in the above formula are all 8-bit data. 19.3.
PAGE 932
19. Display Unit (DU) 19.3.35 Plane n Display Size Y Register (PnDSYR) (n = 1 to 6) The plane n display size Y registers (PnDSYR, n = 1 to 6) set the display size in the vertical direction for plane n. The value is retained during power-on reset and manual reset.
PAGE 933
19. Display Unit (DU) 19.3.36 Plane n Display Position X Register (PnDPXR) (n = 1 to 6) The plane n display position X registers (PnDPXR, n = 1 to 6) set the horizontal start positions on the display monitor for plane n. The value is retained during power-on reset and manual reset.
PAGE 934
19. Display Unit (DU) 19.3.37 Plane n Display Position Y Register (PnDPYR) (n = 1 to 6) The plane n display position Y registers (PnDPYR, n = 1 to 6) set the vertical start position on the display monitor of plane n. The value is retained during power-on reset and manual reset.
PAGE 935
19. Display Unit (DU) 19.3.38 Plane n Display Area Start Address 0 Register (PnDSA0R) (n = 1 to 6) The plane n display area start address 0 registers (PnDSA0R, n = 1 to 6) set the memory area in frame buffer 0 for plane n. The value is retained during power-on reset and manual reset.
PAGE 936
19. Display Unit (DU) 19.3.39 Plane n Display Area Start Address 1 Register (PnDSA1R) (n = 1 to 6) The plane n display area start address 1 registers (PnDSA1R, n = 1 to 6) set the memory area in frame buffer 1 for plane n. The value is retained during power-on reset and manual reset.
PAGE 937
19. Display Unit (DU) 19.3.40 Plane n Start Position X Register (PnSPXR) (n = 1 to 6) The plane n start position X registers (PnSPXR, n = 1 to 6) set the horizontal start position of plane n in memory. The value is retained during power-on reset and manual reset.
PAGE 938
19. Display Unit (DU) 19.3.41 Plane n Start Position Y Register (PnSPYR) (n = 1 to 6) The plane n start position Y registers (PnSPYR, n = 1 to 6) set the vertical start position of plane n in memory. The value is retained during power-on reset and manual reset.
PAGE 939
19. Display Unit (DU) 19.3.42 Plane n Wrap Around Start Position Register (PnWASPR) (n = 1 to 6) The plane n wrap-around start position registers (PnWASPR, n = 1 to 6) set the Y direction start position of one wrap-around area of plane n. The value is retained during power-on reset and manual reset.
PAGE 940
19. Display Unit (DU) 19.3.43 Plane n Wrap Around Memory Width Register (PnWAMWR) (n = 1 to 6) The plane n wrap-around memory width registers (PnWAMWR, n = 1 to 6) set the wrap-around Y-direction memory width for plane n. The value is retained during power-on reset and manual reset.
PAGE 941
19. Display Unit (DU) 19.3.44 Plane n Blinking Time Register (PnBTR) (n = 1 to 6) The plane n blinking time registers (PnBTR, n = 1 to 6) set the display interval length for plane n. When the PnBM bit in PnMR is set to the auto display change mode (blinking mode), by setting, in this register, the length of the interval of display of PnDSA0R and PnDSA1R, blinking operation is performed using PnDSA0R and PnDSA1R. When 1 is set, PnDSA0R and PnDSA1R are switched for each field.
PAGE 942
19. Display Unit (DU) 19.3.45 Plane n Transparent Color 1 Register (PnTC1R) (n = 1 to 6) The plane n transparent color 1 registers (PnTC1R, n = 1 to 6) set a transparent color for plane n, in 8 bits/pixel data format. The value is retained during power-on reset and manual reset.
PAGE 943
19. Display Unit (DU) 19.3.46 Plane n Transparent Color 2 Register (PnTC2R) (n = 1 to 6) The plane n transparent color 2 registers (PnTC2R, n = 1 to 6) set a transparent color for plane n in the 16 bits/pixel, ARGB data format. The value is retained during power-on reset and manual reset.
PAGE 944
19. Display Unit (DU) 19.3.47 Plane n Memory Length Register (PnMLR) (n = 1 to 6) The plane n memory length registers (PnMLR, n = 1 to 6) set the memory length (Y-direction memory area) for plane n.
PAGE 945
19. Display Unit (DU) 19.3.48 Color Palette 1 Register 000 to 255 (CP1_000R to CP1_255R) The color palette 1 registers 000 to 255 (CP1_000R to CP1_255R) are a group of 256 registers which set six bits for each of the RGB components of a color, and are used as a color palette capable of displaying 256 colors among 260,000 possible colors. Bits 31 to 24 are used as a blend ratio. The values are valid for 8 bits/pixel data display. For details of color palette operation, refer to section 19.4.
PAGE 946
19. Display Unit (DU) Bit Bit Name Initial Value R/W Internal Update Description 9, 8 ⎯ All 0 R ⎯ Reserved These bits are always read as 0. The write value should always be 0. 7 to 2 Undefined R/W CP1_000B to Yes Color Palette 1_000 to 255 Blue CP1_255B 1, 0 Blue-color data of color palette 1 should be set. ⎯ All 0 ⎯ R Reserved These bits are always read as 0. The write value should always be 0. 19.3.
PAGE 947
19. Display Unit (DU) Bit Bit Name Initial Value 31 to 24 CP2_000A to Undefined R/W R/W Internal Update Description Yes CP2_255A Color Palette 2_000 to 255 Blending Ratio To enable this bit, the ABRE bit in DEFR should be set to 1. In the initial state, this bit is not enabled. When the PnBRSL bits in PnALPHAR are 10, the value is the alpha value, which is the blend ratio.
PAGE 948
19. Display Unit (DU) 19.3.50 Color Palette 3 Register 000 to 255 (CP3_000R to CP3_255R) The color palette 3 registers 000 to 255 (CP3_000R to CP3_255R) are a group of 256 registers which set six bits for each of the RGB components of a color, and are used as a color palette capable of displaying 256 colors among 260,000 possible colors. Bits 31 to 24 are used as a blend ratio. The values are valid for 8 bits/pixel data display. For details of color palette operation, refer to section 19.4.
PAGE 949
19. Display Unit (DU) Bit Bit Name Initial Value R/W Internal Update Description 9, 8 ⎯ All 0 R ⎯ Reserved These bits are always read as 0. The write value should always be 0. 7 to 2 Undefined R/W CP3_000B to Yes Color Palette 3_000 to 255 Blue CP3_255B 1, 0 Blue-color data of color palette 3 should be set. ⎯ All 0 ⎯ R Reserved These bits are always read as 0. The write value should always be 0. 19.3.
PAGE 950
19. Display Unit (DU) Bit Bit Name Initial Value 31 to 24 CP4_000A to Undefined R/W R/W Internal Update Description Yes CP4_255A Color Palette 4_000 to 255 Blending Ratio To enable this bit, the ABRE bit in DEFR should be set to 1. In the initial state, this bit is not enabled. When the PnBRSL bits in PnALPHAR are 10, the value is the alpha value, which is the blend ratio.
PAGE 951
19. Display Unit (DU) 19.3.52 External Synchronization Control Register (ESCR) The external synchronization control register (ESCR) controls the dot clock.
PAGE 952
19. Display Unit (DU) Bit Initial Bit Name Value 4 to 0 FRQSEL 0 Internal R/W Update Description R/W None Frequency Select To enable this bit, the DCKE bit in DEFR should be set to 1. In the initial state, bit 4 is fixed at 0, and the frequency division ratio is up to 16. 00000: Frequency division of the input dot clock (clock for division) is not performed.
PAGE 953
19. Display Unit (DU) 19.3.53 Output Signal Timing Adjustment Register (OTAR) The output signal timing adjustment register (OTAR) selects the timing for the output signal. For information on adjustment timing, refer to section 19.5.5, Output Signal Timing Adjustment.
PAGE 954
19. Display Unit (DU) Bit Initial Bit Name Value 30 to 28 DEA 0 R/W Internal Update Description R/W None DE Output Timing Adjustment 000: Adjustment of output timing is not performed. The DE signal is output at the rising edge of the dot clock, with the reference timing. 001: The DE signal is output at the rising edge, delayed one dot clock cycle relative to the reference timing. 010: The DE signal is output at the rising edge, delayed two dot clock cycles relative to the reference timing.
PAGE 955
19. Display Unit (DU) Bit Initial Bit Name Value 26 to 24 CLAMPA 0 R/W Internal Update Description R/W None CLAMP Output Timing Adjustment 000: Adjustment of output timing is not performed. The CLAMP signal is output at the rising edge of the dot clock, with the reference timing. 001: The CLAMP signal is output at the rising edge, delayed one dot clock cycle relative to the reference timing.
PAGE 956
19. Display Unit (DU) Bit Initial Bit Name Value 22 to 20 DRGBA 0 R/W Internal Update Description R/W None Digital IRGV Output Timing Adjustment 000: Adjustment of output timing is not performed. The RGB signal is output at the rising edge of the dot clock, with the reference timing. 001: The RGB signal is output at the rising edge, delayed one dot clock cycle relative to the reference timing.
PAGE 957
19. Display Unit (DU) Bit Initial Bit Name Value R/W Internal Update Description 10 to 8 CDEA R/W None 0 CDE Output Timing Adjustment 000: Adjustment of output timing is not performed. The CDE signal is output at the rising edge of the dot clock, with the reference timing. 001: The CDE signal is output at the rising edge, delayed one dot clock cycle relative to the reference timing. 010: The CDE signal is output at the rising edge, delayed two dot clock cycles relative to the reference timing.
PAGE 958
19. Display Unit (DU) Bit Initial Bit Name Value R/W Internal Update Description 6 to 4 DISPA R/W None 0 DISP Output Timing Adjustment 000: Adjustment of output timing is not performed. The DISP signal is output at the rising edge of the dot clock, with the reference timing. 001: The DISP signal is output at the rising edge, delayed one dot clock cycle relative to the reference timing. 010: The DISP signal is output at the rising edge, delayed two dot clock cycles relative to the reference timing.
PAGE 959
19. Display Unit (DU) Bit Initial Bit Name Value R/W Internal Update Description 2 to 0 SYNCA R/W None 0 SYNC* Output Timing Adjustment 000: Adjustment of output timing is not performed. The SYNC* signal is output at the rising edge of the dot clock, with the reference timing. 001: The SYNC* signal is output at the rising edge, delayed one dot clock cycle relative to the reference timing.
PAGE 960
19. Display Unit (DU) 19.4 Operation 19.4.1 Configuration of Output Screen The display unit (DU) executes window displays with up to a maximum of six window layers. Each of these windows is called a "plane", and the order of stacking of the planes can be set arbitrarily. For each plane, display can be turned on and off, and the display data format (8 bits/pixel, 16 bits/pixel, ARGB, YC), blending functions, and other settings can be changed independently.
PAGE 961
19. Display Unit (DU) Table 19.
PAGE 962
19. Display Unit (DU) Frame buffer 4 Output planes are combined and displayed according to the superpositioning order and blending mode for each plane. Frame buffer 2 Background color can be specified. Frame buffer 1 Display side The superpositioning order can be specified arbitrarily. Frame buffer 1 Frame buffer 2 Frame buffer 4 Frame buffer 3 A double-buffer function is used to switch the frame buffer between drawing side and display side Figure 19.
PAGE 963
19. Display Unit (DU) 19.4.2 Display On/Off All plane display can be turned on and off using the DEN bit in DSYSR. When the DEN bit is 0, the display data set in DOOR is displayed. Display is turned on and off for planes 1 to 6 using DPPR. Under the following display conditions, display data set in BPOR is displayed. 1. When display of all planes 1 to 6 is turned off 2. In an area with no plane for display, due to the display size and display position 3.
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19. Display Unit (DU) 19.4.3 Plane Parameter For each plane, a display area start position, memory width, display start position, and display size are set using registers. The followings are the schematic diagram of start positions and sizes related to planes and the registers used for setting start positions and sizes. 2. DSA 1. MWX Monitor origin (upper left) 6. SPY 3. WASPY 10. DPY 9. DPX 8. DSY 5. SPX 8. DSY 4. WAMWY 7. DSX 7. DSX Monitor parameters 11. MLY Memory parameters Figure 19.
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19. Display Unit (DU) Table 19.6 Memory Parameter/ Monitor Parameter Setting Registers Names Used in the No. Figure Setting Registers 1 MWX (Plane memory width) PnMWR The plane X-direction memory width is set between 16 and 4096 pixels, in 16 pixel units. 2 DSA (Display area start address) PnDSA0R and PnDSA1R The start address in memory area is set for plane n.
PAGE 966
19. Display Unit (DU) 19.4.4 Memory Allocation A display start address for the display screen can be set individually for each plane. Leading addresses for the memory areas used are set in each of the display area start address registers. In the display unit (DU), the display area start addresses 0 and 1 are used for each plane to perform double-buffer control and display each plane. Below is a list of display area start address registers used for each of the planes. Table 19.
PAGE 967
19. Display Unit (DU) 19.4.5 Input Display Data Format The following format is used for input color data used in display. • 8 bit/pixel A color palette index is used. The color palette is used to convert and display image data into RGB data with 6 bits for each RGB color (RGB666). The arrangement of data in memory is as follows.
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19. Display Unit (DU) • 16 bit/pixel: ARGB The ARGB levels are represented using A:1, R:5, G:5, B:5 bits (ARGB555). In addition to the RGB values, an alpha value is set. Blending control using the A value is valid when the PnSPIM bit in PnMR is set to perform blending; when A = 1, blending is performed. When the PnSPIM bit is not set to perform blending, blending is not performed even when A = 1.
PAGE 969
19.
PAGE 970
19. Display Unit (DU) 19.4.6 Output Data Format When outputting digital RGB data from the display unit (DU), the display data format is expanded into the RGB666 format before output. The format at the time of output is as indicated in the following table. Table 19.
PAGE 971
19. Display Unit (DU) Endian conversion in each of the units indicated below is shown in figure 19.4.
PAGE 972
19. Display Unit (DU) 19.4.8 Color Palettes 8 bits/pixel data employs color palettes. Four color palettes can be used; these are called color palette 1, color palette 2, color palette 3, and color palette 4. The color palette used in each plane can be set to any among color palette 1, color palette 2, color palette 3, and color palette 4 using the PnCPSL bits in PnMR. Each of the color palettes consists of two alternate buffers; one serves as a display buffer, and the other is for CPU access.
PAGE 973
19. Display Unit (DU) 19.4.9 Superpositioning of Planes For each plane, three types of combined superpositioning are possible: α blending, transparent colors, and EOR operations. By setting the PnSPIM bits in PnMR, the superpositioned display type can be selected. However, α blending and EOR operation cannot be performed simultaneously on the same plane. α blending and EOR operations are performed after expanding the display data format into RGB888 format.
PAGE 974
19. Display Unit (DU) Table 19.
PAGE 975
19. Display Unit (DU) When the PnDDF bit in PnMR is set to ARGB, and moreover the PnSPIM bit in PnMR is set to perform blending, α blending is performed according to the A value of the input ARGB data format. Transparent Colors: For each plane, transparent color processing can be performed between the specified plane and the lower plane by setting PnSPIM bit in PnMR to 0. However, in YC format transparent color processing cannot be performed.
PAGE 976
19. Display Unit (DU) Table 19.12 Transparent Color Specification Registers Data Format Transparent Color Specification Bit Color Palette Select Bit Transparent Color Specification Register ⎯ (PnMR) /PnTC (PnMR) /PnCPSL ⎯ 8 bits/pixel 0 ⎯ PnTC1R 1 00 CP1TR 1 01 CP2TR 1 10 CP3TR 1 11 CP4TR 16 bits/pixel ⎯ ⎯ PnTC2R ARGB ⎯ ⎯ PnTC2R EOR Operation: EOR operation of the specified plane with the lower plane is performed. Rev.1.00 Jan.
PAGE 977
19. Display Unit (DU) 19.4.10 Display Contention Color Palette Contention: When performing α blending and EOR operations, if the same color palette is selected for both planes with the input display data format at 8 bits/pixel, color palette contention may occur. This is because contention decisions occur not in plane units, but in pixel units. Figure 19.
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19. Display Unit (DU) Color palette selection Δ: Same color palette selected; X: Different color palette selected P1 Δ Δ Δ X X P1 P2 P2 Δ Δ X Δ X P3 Δ X Δ Δ X P1 P1 P1 P1 P1 P1αP3 P1 P1αP2 P1αP2 P1 P1αP2 P1αP2 P1(P2⊕P3) P1αP2 P1αP3 P2⊕P3 P2 P3 P2⊕P3 P2 P3 P3 P2 P2 P3 BPOR BPOR BPOR BPOR P3 P1 P2 P2 P1 P1αP3 P1 P1 P2⊕P3 P2 P3 BPOR Transparent color Non-transparent color Figure 19.
PAGE 979
19. Display Unit (DU) Plane Priority Order: The display priority order for planes is set using DPPR; if one plane is set in two or more places in the priority order, the place with highest priority is selected. For example, if the setting in DPPR is H'00CBD888, then the results of the priority order and display on/off settings are as follows.
PAGE 980
19. Display Unit (DU) 19.4.12 Scroll Display By setting display area and display screen sizes and start positions independently for each plane, smooth scroll processing can be performed independently for each plane. The display can be scrolled by cyclically setting the plane n display start position X, Y values (coordinates specified by PnSPXR and PnSPYR), taking as the origin the leading address in memory specified by PnDSA0R and PnDSA1R for each plane. Figure 19.9 summarizes display scrolling.
PAGE 981
19. Display Unit (DU) 19.4.13 Wraparound Display In addition to display scrolling, wrap-around display, which can be used in spherical scrolling, is possible for each plane. When enabling wrap-around display, the PnWAE bit in PnMR is set.
PAGE 982
19. Display Unit (DU) 19.4.14 Upper-Left Overflow Display For each plane, a display start position in memory (PnSPXR, PnSPYR) and display size (PnDSXR, PnDSYR) can be set arbitrarily, so that by combining and using these registers, areas overflowing the upper-left relative to the monitor origin (upper-left corner) can be displayed without overwriting display data in memory.
PAGE 983
19. Display Unit (DU) 19.4.15 Double Buffer Control The double buffer control of the display unit (DU) includes two types of functions, which are a manual display change mode in which display switching is all controlled by software, and an auto display change mode to realize blinking. In the case of manual display change mode, the display change is performed in frame units for non-interlaced and interlaced sync display, and in field units for interlaced sync & video display.
PAGE 984
19. Display Unit (DU) 19.4.16 Sync Mode In order to facilitate synchronization with external equipment, in addition to master mode, a TV synchronization function is provided. Selection of master mode and TV sync mode is performed using the TVM bit in DSYSR. Regardless of the synchronization method, the position of the falling edge of the vertical sync signal (VSYNC) set by VSPR is detected and is reflected in the FRM bit and VBK bit in DSSR.
PAGE 985
19. Display Unit (DU) TV (sync signal generation circuit): Master Clock HSYNC VSYNC Field signal R,G,B Display Input 2 DCLKIN HSYNC VSYNC ODDF This LSI: Slave Output DR5-DR0 DG5-DG0 DB5-DB0 CDE Input 1 Switching between master (input 2) and slave (input 1) by CDE. Figure 19.12 Signal Flow in TV Sync Mode Sync Method Switching Mode: When switching from master mode into TV sync mode, or from TV sync mode into master mode, when necessary this mode should be switched into first.
PAGE 986
19. Display Unit (DU) 19.5 Display Control 19.5.1 Display Timing Generation In the display unit (DU), display timing is generated for the horizontal direction and vertical direction of the display screen. Display timing is set by using display timing generation registers. Figure 19.13 shows the display timing in non-interlaced mode. Here, the display screen is defined in terms of the variables of Table 19.13. hc hsw xs VSYNC HSYNC xw ys vc yw Display area vsw Figure 19.
PAGE 987
19. Display Unit (DU) Table 19.
PAGE 988
19. Display Unit (DU) Table 19.
PAGE 989
19. Display Unit (DU) 19.5.2 CSYNC When in master mode, a CSYNC (composite sync) signal is output. EQWR is used to set the lowlevel pulse width of the CSYNC equal pulse. SPWR is used to set the low-level pulse width of the CSYNC separation pulse. The CSYNC waveform is selected using the CSY bit in DSMR. HC HSW HSYNC VSYNC CSYNC (CSY = 00) EQW SPW (CSY = 10) Equivalent pulse: 3 rasters Separation pulse: 3 rasters Equivalent pulse: 3 rasters (CSY = 11) 1/2HC Equivalent pulse: 2.
PAGE 990
19. Display Unit (DU) HC HSW HSYNC VSYNC CSYNC (CSY = 00) 1/2HC EQW SPW (CSY = 10) Equivalent pulse: 3 rasters Separation pulse: 3 rasters Equivalent pulse: 3 rasters (CSY = 11) 1/2HC Equivalent pulse: 2.5 rasters Separation pulse: 2.5 rasters Equivalent pulse: 2.5 rasters When HC is odd, it is rounded to an even value. Figure 19.15 CSYNC Timing Chart (Last Half of Interlace Frame) Rev.1.00 Jan.
PAGE 991
19. Display Unit (DU) 19.5.3 Scan Method The scan method can be selected from among non-interlaced mode, interlaced sync mode, and interlaced sync & video mode. The mode is selected using the SCM bit in DSYSR. • Non-interlaced mode In this scan method, one frame consists of a single field. • Interlaced sync mode In this scan method, one frame consists of two fields. The two fields are an even field and an odd field, displaying the same data.
PAGE 992
19. Display Unit (DU) 00 00 00 01 01 01 02 02 02 03 03 03 04 04 04 05 05 05 06 06 06 07 07 07 08 08 08 09 09 Non-interlaced mode 00 09 Interlaced sync mode 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E Raster scanned in an odd field Raster scanned in an even field 0F 10 11 12 13 Interlaced sync & video mode Figure 19.16 Example of Display in Each Scan Mode Rev.1.00 Jan.
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19. Display Unit (DU) • Example of vertical scan period Non-interlaced mode: 1/60 second/field, 1/30 second/field Interlaced mode: 1/30 second/frame Interlaced sync & video mode: 1/30 second/frame • Display in non-interlaced method In this method, all lines are displayed at once without providing intervals between input video signals. This input method is for monitors capable of high-resolution display. Display in non-interlaced mode The ODEV and ODDF pins are not used.
PAGE 994
19. Display Unit (DU) • Display in interlaced method At every scan period VC of the input video signal, even lines and odd lines are switched and displayed in alternation, and a single screen (one frame) is combined and displayed (with the afterimage of the preceding VC) with a period of 2VC. This is the normal TV input method. 1. Display in interlaced sync mode When one frame is configured as shown below, clear the ODEV bit to 0.
PAGE 995
19. Display Unit (DU) 19.5.4 Color Detection When output display data matches a color set in CDER, high level is output from the CDE pin. The CDEM bit in DSMR can be used to fix the level outside display intervals. Also, the CDEL bit in DSMR can be used to select the polarity of the output level. Table 19.
PAGE 996
19. Display Unit (DU) 19.5.5 Output Signal Timing Adjustment The display unit (DU) enables selection of output timing, with respect to the output dot clock, of the various output signals (the four sync signals HSYNC, VSYNC, CSYNC, ODDF, as well as DISP, CDE, CLAMP, DE, digital RGB signals). Timing is selected by setting OTAR. Table 19.
PAGE 997
19. Display Unit (DU) 19.5.6 CLAMP Signal and DE Signal The display unit (DU) generates a CLAMP signal and DE signal, independent of the DISP signal indicating the display interval. The rising-edge start position and high-level width of the CLAMP signal and DE signal, with reference to the HSYNC signal falling edge, can be set in dot clock units. Figure 19.20 shows the timing chart. However, the DE signal is fixed at low level during the vertical blanking interval.
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19. Display Unit (DU) 19.6 Power-Down Sequence When executing the power-down sequence by the following modes or functions, turn off the display in advance. 1. 2. 3. 4. 5. Sleep mode Deep sleep mode Module standby Change of frequency Manual reset Even when the display unit (DU) enters the power-down sequence, the register values are retained. During a power-down sequence, do not access the display unit (DU). 19.6.1 Procedures before Executing the Power-Down Sequence 1.
PAGE 999
20. Graphics Data Translation Accelerator (GDTA) Section 20 Graphics Data Translation Accelerator (GDTA) This block incorporates a YUV data conversion processing module (CL) that converts data in the YUV 4:2:0 format to YUV 4:2:2 or ARGB format, as well as a video processing module (MC) that generates estimated images using motion vectors.
PAGE 1000
20. Graphics Data Translation Accelerator (GDTA) Figure 20.1 shows the GDTA block diagram.
PAGE 1001
20. Graphics Data Translation Accelerator (GDTA) (1) Target Interface The target interface controls access by the CPU to the GDTA internal registers, buffer RAM 0/1, and CL and MC function blocks (image processing function blocks). The target interface places a request queue/response queue in the high-speed SuperHyway bus reception unit, and alleviates the access load of the initiator on this bus.
PAGE 1002
20. Graphics Data Translation Accelerator (GDTA) (6) Buffer RAM Buffer RAM consists of two SRAM units each with an 8-Kbyte capacity. The RAM is used to store color conversion table data for CL functions (buffer RAM 0) and to store IDCT data for MC functions (buffer RAM 1). The entire 16-Kbyte capacity of this buffer RAM is allocated to a memory map seen from the CPU. Valid access sizes are 4, 8, 16 and 32 bytes, and invalid access sizes are 1 and 2 bytes.
PAGE 1003
20. Graphics Data Translation Accelerator (GDTA) 20.2 GDTA Address Space Figure 20.2 shows the GDTA address space (physical addresses). The GDTA consists of a number of function blocks; the address space is divided into function block units owned by the respective blocks. However, not all actually existing addresses are on the space; addresses following those in a function block are mapped as mirror spaces for the function block.
PAGE 1004
20. Graphics Data Translation Accelerator (GDTA) 20.3 Register Descriptions Table 20.1 to 20.3 show the register configuration of the GDTA. Table 20.4 to 20.6 show the register states in each processing mode. Table 20.
PAGE 1005
20. Graphics Data Translation Accelerator (GDTA) Table 20.
PAGE 1006
20. Graphics Data Translation Accelerator (GDTA) Table 20.
PAGE 1007
20. Graphics Data Translation Accelerator (GDTA) Table 20.
PAGE 1008
20. Graphics Data Translation Accelerator (GDTA) Table 20.
PAGE 1009
20. Graphics Data Translation Accelerator (GDTA) 20.3.1 GA Mask Register (GACMR) GACMR is in the GDTA common register block and enables writing to the GA enable register (GACER). Writing to GACER is enabled by writing of the key code to this register. In the initial state, the key code is not written and writing to GACER is disabled.
PAGE 1010
20. Graphics Data Translation Accelerator (GDTA) 20.3.2 GA Enable Register (GACER) GACER is in the GDTA common register block and controls the block operation.
PAGE 1011
20. Graphics Data Translation Accelerator (GDTA) 20.3.3 GA Interrupt Source Indicating Register (GACISR) GACISR is in the GDTA common register block and indicates the states of interrupt sources for each module.
PAGE 1012
20. Graphics Data Translation Accelerator (GDTA) 20.3.4 GA Interrupt Source Indication Clear Register (GACICR) GACICR is in the GDTA common register block and clears interrupt source indication for each module. Bits in this register are read as 0.
PAGE 1013
20. Graphics Data Translation Accelerator (GDTA) 20.3.5 GA Interrupt Enable Register (GACIER) GACIER is in the GDTA common register block and sets interrupt output for each module.
PAGE 1014
20. Graphics Data Translation Accelerator (GDTA) 20.3.6 GA CL Input Data Alignment Register (DRCL_CTL) DRCL_CTL is in the GDTA common register block and specifies data alignment of CL input data.
PAGE 1015
20. Graphics Data Translation Accelerator (GDTA) 20.3.7 GA CL Output Data Alignment Register (DWCL_CTL) DWCL_CTL is in the GDTA common register block and specifies data alignment of CL output data.
PAGE 1016
20. Graphics Data Translation Accelerator (GDTA) 20.3.8 GA MC Input Data Alignment Register (DRMC_CTL) DRMC_CTL is in the GDTA common register block and specifies data alignment of MC input data.
PAGE 1017
20. Graphics Data Translation Accelerator (GDTA) 20.3.9 GA MC Output Data Alignment Register (DWMC_CTL) DWMC_CTL is in the GDTA common register block and specifies data alignment of MC output data.
PAGE 1018
20. Graphics Data Translation Accelerator (GDTA) 20.3.10 GA Buffer RAM 0 Data Alignment Register (DCP_CTL) DCP_CTL is in the GDTA common register block and specifies data alignment of the data stored in buffer RAM 0.
PAGE 1019
20. Graphics Data Translation Accelerator (GDTA) 20.3.11 GA Buffer RAM 1 Data Alignment Register (DID_CTL) DID_CTL is in the GDTA common register block and specifies data alignment of the data stored in buffer RAM 1.
PAGE 1020
20. Graphics Data Translation Accelerator (GDTA) 20.3.12 CL Command FIFO (CLCF) CLCF is in the CL register block and receives commands. This register uses the FIFO method and recognizes four command parameters according to the writing order. This register does not retain the written values. This register is always read as 0.
PAGE 1021
20. Graphics Data Translation Accelerator (GDTA) 2. Setting Method When Setting Values in Succession When setting values in this register in succession, the CL module is able to receive the next command while the CL_CFF bit in CLSR is 0. To perform processing by changing the command alone, just set the new command in this register. 3. The input Y/U/V pointers and output pointers must be set to point to addresses on 32byte boundaries. If not, the lower address is regarded as 0. 4.
PAGE 1022
20. Graphics Data Translation Accelerator (GDTA) Bit Bit Name Initial Value R/W Description 1 CL_OA 0 R/W Specifies output address mode 0: Output address incremented When the output access size is 4 bytes, the address is incremented by H'4; when the output access size is 32 bytes, the address is incremented by H'20. 1: Output address fixed The address set in CLCF as command parameter 4 (output pointer) is output.
PAGE 1023
20. Graphics Data Translation Accelerator (GDTA) 20.3.14 CL Status Register (CLSR) CLSR is in the CL register block and indicates the internal states of the CL.
PAGE 1024
20. Graphics Data Translation Accelerator (GDTA) 20.3.15 CL Frame Width Setting Register (CLWR) CLWR is in the CL register block and sets the input image width in pixel units.
PAGE 1025
20. Graphics Data Translation Accelerator (GDTA) 20.3.16 CL Frame Height Setting Register (CLHR) CLHR is in the CL register block and sets the input image height in line units.
PAGE 1026
20. Graphics Data Translation Accelerator (GDTA) 20.3.17 CL Input Y Padding Size Setting Register (CLIYPR) CLIYPR is in the CL register block and sets the input Y padding size in byte units.
PAGE 1027
20. Graphics Data Translation Accelerator (GDTA) 20.3.18 CL Input UV Padding Size Setting Register (CLIUVPR) CLIUVPR is in the CL register block and sets the input UV padding size in byte units.
PAGE 1028
20. Graphics Data Translation Accelerator (GDTA) 20.3.19 CL Output Padding Size Setting Register (CLOPR) CLOPR is in the CL register block and sets the output padding size in byte units.
PAGE 1029
20. Graphics Data Translation Accelerator (GDTA) 20.3.20 CL Palette Pointer Register (CLPLPR) CLPLPR is in the CL register block and sets the color conversion table pointer. The RAM 0 address used for a work area should be specified. This register setting is used only in the ARBG conversion mode, not used in the YUYV conversion mode.
PAGE 1030
20. Graphics Data Translation Accelerator (GDTA) 20.3.21 MC Command FIFO (MCCF) MCCF is in the MC register block and receives commands. This register uses the FIFO method and recognizes a maximum of eight command parameters according to the writing order. This register does not retain the written values. This register is always read as 0.
PAGE 1031
20.
PAGE 1032
20.
PAGE 1033
20. Graphics Data Translation Accelerator (GDTA) 20.3.22 MC Status Register (MCSR) MCSR is in the MC register block and indicates the internal states of the MC.
PAGE 1034
20.
PAGE 1035
20. Graphics Data Translation Accelerator (GDTA) 20.3.24 MC Frame Height Setting Register (MCHR) MCHR is in the MC register block and sets the input image height in line units.
PAGE 1036
20. Graphics Data Translation Accelerator (GDTA) 20.3.25 MC Y Padding Size Setting Register (MCYPR) MCYPR is in the MC register block and sets the input Y padding size in byte units.
PAGE 1037
20. Graphics Data Translation Accelerator (GDTA) 20.3.26 MC UV Padding Size Setting Register (MCUVPR) MCUVPR is in the MC register block and sets the input UV padding size in byte units.
PAGE 1038
20. Graphics Data Translation Accelerator (GDTA) 20.3.27 MC Output Frame Y Pointer Register (MCOYPR) MCOYPR is in the MC register block and specifies the Y pointer address for an output frame.
PAGE 1039
20. Graphics Data Translation Accelerator (GDTA) 20.3.29 MC Output Frame V Pointer Register (MCOVPR) MCOVPR is in the MC register block and specifies the V pointer address for an output frame.
PAGE 1040
20. Graphics Data Translation Accelerator (GDTA) 20.3.31 MC Past Frame U Pointer Register (MCPUPR) MCPUPR is in the MC register block and specifies the U pointer address for a past frame.
PAGE 1041
20. Graphics Data Translation Accelerator (GDTA) 20.3.33 MC Future Frame Y Pointer Register (MCFYPR) MCFYPR is in the MC register block and specifies the Y pointer address for a future frame.
PAGE 1042
20. Graphics Data Translation Accelerator (GDTA) 20.3.35 MC Future Frame V Pointer Register (MCFVPR) MCFVPR is in the MC register block and specifies the V pointer address for a future frame.
PAGE 1043
20. Graphics Data Translation Accelerator (GDTA) 20.4 GDTA Operation 20.4.1 Explanation of CL Operation By writing 1 to the CL_EN bit in GACER, registers in the CL register unit can be accessed.
PAGE 1044
20. Graphics Data Translation Accelerator (GDTA) Table 20.7 shows YUYV4:2:2 conversion sequence shown in figure 20.3. No. in the table corresponds to the number used in figure 20.3. Table 20.7 YUYV4:2:2 Conversion Sequence No. Operation Description (1) YUV-separated input data stored in DDR2-SDRAM is read into the GDTA. (2) Input data reading The input data includes padding data with the specified input Y (UV) padding size, but the GDTA excludes this padding data when reading the data.
PAGE 1045
20. Graphics Data Translation Accelerator (GDTA) (2) Overview of ARGB Conversion Functions The following shows an outline of the ARGB conversion specification. 256 entries 256 entries 16 bits A A A Y1: 1.164 (Y-16) Y1: 1.164 (Y-16) Y1: 1.164 (Y-16) . . . . . . . . U0: -0.392 (U-128) U0: -0.392 (U-128) U0: -0.392 (U-128) U1: 2.017 (U-128) U1: 2.017 (U-128) U1: 2.017 (U-128) . . . . . . . . V0: 1.596 (V-128) V0: 1.596 (V-128) V0: 1.596 (V-128) V1: -0.813 (V-128) V1: -0.813 (V-128) V1: -0.
PAGE 1046
20. Graphics Data Translation Accelerator (GDTA) Table 20.8 shows ARGB8888 conversion sequence shown in figure 20.4. No. in the table corresponds to the number used in figure 20.4. (1) and (2) correspond to the numbers in figure 20.3. Table 20.8 ARGB8888 Conversion Sequence No. Operation Description (1) YUV-separated input data stored in DDR2-SDRAM is read into the GDTA.
PAGE 1047
20. Graphics Data Translation Accelerator (GDTA) No. Operation Description (4) ARGB data is generated from color information read from buffer RAM 0 using the following formula, and the converted data is output in the format shown in the display image of figure 20.4. ARGB conversion is performed according to the following conversion logic. ARGB conversion A = The result of computation of clip_0_255((A+16)>> 5) for unsigned 16-bit data (11 integer bits, 5 decimal bits) read from RAM 0 is output.
PAGE 1048
20. Graphics Data Translation Accelerator (GDTA) Start [Step (1) Clear the CL access mask] After the CPU sets the key code in GACMR within the bus interface, set GACER to enable access to the CL function block. [Step (2) Initialize the CL function block] The CPU sets the frame width/height, input Y/UV padding size, output padding size, and output data/address mode. In ARGB conversion mode, CLPLPR should also be set.
PAGE 1049
20. Graphics Data Translation Accelerator (GDTA) 20.4.2 Explanation of MC Operation By writing 1 to the MC_EN bit in GACER, registers in the MC register unit can be accessed.
PAGE 1050
20. Graphics Data Translation Accelerator (GDTA) (1) Estimated Image Generation Function The following shows an outline of the estimated image generation function.
PAGE 1051
20. Graphics Data Translation Accelerator (GDTA) Table 20.9 shows estimated image generation sequence shown in figure 20.6. No. in the table corresponds to the number used in figure 20.6. Table 20.9 Estimated Image Generation Sequence No. Operation (1) Description Calculation of The following formulae are used to compute output position (first row) (DDR2output position SDRAM output address).
PAGE 1052
20. Graphics Data Translation Accelerator (GDTA) No. Operation (2) Description Calculation of The following formulae are used to compute output positions (nth row and output position below) (DDR2-SDRAM output address).
PAGE 1053
20. Graphics Data Translation Accelerator (GDTA) No. Operation Description (3) The following formulae are used to compute input position (first row) (DDR2SDRAM input address).
PAGE 1054
20. Graphics Data Translation Accelerator (GDTA) No.
PAGE 1055
20. Graphics Data Translation Accelerator (GDTA) No. Operation Description (4) The following formulae are used to compute input positions (nth row and below) (DDR2-SDRAM input address).
PAGE 1056
20. Graphics Data Translation Accelerator (GDTA) No. Operation Description (6) Half-pixel correction processing is performed for the data read in (5). Half-pixel correction processing (For the Y pointer: 16 to the right and 16 downward in 4 pixel units, for a total of 256 processed) * The Recon_down value is used to perform half-pixel correction even/odd decisions. Decision results are as follows. (The Recon_right value is similarly used to perform half-pixel correction even/odd decisions.
PAGE 1057
20. Graphics Data Translation Accelerator (GDTA) No. Operation Description (7) IDCT data stored in buffer RAM 1 is read. IDCT data reading (Only blocks specified by a CBP setting of 1 are read from buffer RAM 1.) The IDCT data should be stored in buffer RAM 1 as 16-bit signed data. (The sign is discriminated using the uppermost bit (bit 15).
PAGE 1058
20. Graphics Data Translation Accelerator (GDTA) Start [Step (1) Clear the MC access mask] After the CPU sets the key code in GACMR within the bus interface, set GACER to enable access to the MC function block. [Step (2) Initialize the MC function block] The CPU sets the frame width/height, input Y/UV padding size, output frame Y/U/V pointers, past frame Y/U/V pointers, and future frame Y/U/V pointers. [Step (3) Write IDCT data to RAM 1] The CPU writes IDCT data to RAM 1.
PAGE 1059
20. Graphics Data Translation Accelerator (GDTA) 20.5 Interrupt Processing In the GDTA, there are four types of interrupt sources. There are three interrupt flags for CL processing end, MC processing end, and CL/MC errors, used to identify interrupt sources. The interrupt enable bit allows generation of interrupt requests. CL errors and MC errors use a common GAERI interrupt. Table 20.
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20. Graphics Data Translation Accelerator (GDTA) Data alignment unit: 1 byte 1. Conversion pattern 1 (CP1) 63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0 D0 D1 D2 D3 D4 D5 D6 D7 3.
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20. Graphics Data Translation Accelerator (GDTA) 20.7 Usage Notes When using the GDTA, note the following: 20.7.1 Regarding Module Stoppage During GDTA operation, the CPG register settings must not be done to stop a module (other modules as well as the GDTA). If a module is stopped during GDTA operation, the GDTA processing is stopped and processing contents set in CL/MC command FIFO are cleared.
PAGE 1062
20. Graphics Data Translation Accelerator (GDTA) 20.7.3 Regarding Frequency Changes During GDTA operation, the CPG register setting must not be used to change frequency. If frequency is changed during GDTA operation, the GDTA processing is stopped and processing contents set in CL/MC command FIFO are cleared. When changing the frequency, the frequency should be changed only after confirming that the CLSR.EXE bit (bit 3) in CLSR is 0 and the MC_CFA bits (bits 10 to 8) in MCSR are 000.
PAGE 1063
21. Serial Communication Interface with FIFO (SCIF) Section 21 Serial Communication Interface with FIFO (SCIF) This LSI is equipped with a 6-channel serial communication interface with built-in FIFO buffers (Serial Communication Interface with FIFO: SCIF). The SCIF can perform both asynchronous and clocked synchronous serial communications. 64-stage FIFO buffers are provided for transmission and reception, enabling fast, efficient, and continuous communication.
PAGE 1064
21. Serial Communication Interface with FIFO (SCIF) • Full-duplex communication capability The transmitter and receiver are independent units, enabling transmission and reception to be performed simultaneously. The transmitter and receiver both have a 64-stage FIFO buffer structure, enabling continuous transmission and reception of serial data. • LSB first for data transmission and reception • On-chip baud rate generator allows any bit rate to be selected.
PAGE 1065
21. Serial Communication Interface with FIFO (SCIF) Module data bus SCFRDRn (128 stages) (64 stages) SCIFn_RXD SCFTDRn (128 stages) (64 stages) SCRSRn SCTSRn SCSMRn SCLSRn SCTFDRn SCRFDRn SCFCRn SCFSRn SCSCRn SCBRRn Pck Baud rate generator SCSPTRn SCRERn Parity generation Pck/4 Pck/16 Pck/64 Transmission/ reception control SCIFn_TXD Peripheral bus Bus interface Figure 21.1 shows a block diagram of the SCIF. Figures 21.2 to 21.6 show block diagrams of the I/O ports in the SCIF.
PAGE 1066
21. Serial Communication Interface with FIFO (SCIF) Reset R D7 Q D RTSIO C Peripheral bus SPTRW Reset SCIF0_RTS R Q D RTSDT C D6 SPTRW Modem control enable signal* SCIF0_RTS signal SPTRR Legend: SPTRW: Write to SCSPTR SPTRR: Read from SCSPTR Note: * SCSPTR The SCIF0_RTS pin function is designated as modem control by the MCE bit in SCFCR. Figure 21.2 SCIF0_RTS Pin Rev.1.00 Jan.
PAGE 1067
21. Serial Communication Interface with FIFO (SCIF) Reset R D5 Q D CTSIO C Peripheral bus SPTRW Reset SCIF0_CTS R D4 Q D CTSDT C SPTRW SCIF0_CTS signal Modem control enable signal* SPTRR Legend: SPTRW: Write to SCSPTR SPTRR: Read from SCSPTR Note: * The SCIF0_CTS pin function is designated as modem control by the MCE bit in SCFCR. Figure 21.3 SCIF0_CTS Pin Rev.1.00 Jan.
PAGE 1068
21. Serial Communication Interface with FIFO (SCIF) Reset R D3 Q D SCKIO C Peripheral bus SPTRW SCIFn_SCK Reset R D2 Q D SCKDT C SPTRW Clock output enable signal* Serial clock output signal* Serial clock input signal* Serial input enable signal* Legend: SPTRW: Write to SCSPTR SPTRR: Read from SCSPTR SPTRR Note: * The SCIFn_SCK pin function is designated as internal clock output or external clock input by the C/A bit in SCSMR and the CKE1 and CKE0 bits in SCSCR. Figure 21.
PAGE 1069
21. Serial Communication Interface with FIFO (SCIF) SCIFn_RXD Serial receive data Peripheral bus SPTRR Legend: SPTRR: Read from SCSPTR Figure 21.6 SCIFn_RXD Pin (n = 0 to 5) 21.2 Input/Output Pins Table 21.1 shows the SCIF pin configuration. Since the pin functions are the same in each channel, the channel number is omitted in the description below. The modem control pins are available only in channel 0. Table 21.
PAGE 1070
21. Serial Communication Interface with FIFO (SCIF) 21.3 Register Descriptions The SCIF has the following registers. Since the register functions are the same in each channel, the channel number is omitted in the description below. Table 21.2 Register Configuration (1) Sync Ch. Register Name Abbrev.
PAGE 1071
21. Serial Communication Interface with FIFO (SCIF) Sync Ch. Register Name Abbrev.
PAGE 1072
21. Serial Communication Interface with FIFO (SCIF) Sync Ch. Register Name Abbrev.
PAGE 1073
21. Serial Communication Interface with FIFO (SCIF) Table 21.2 Register Configuration (2) Sleep/Deep Power-on Reset Manual Reset Sleep by PRESET Pin/ by WDT/Multiple by SLEEP Module Ch. Register Name Abbrev.
PAGE 1074
21. Serial Communication Interface with FIFO (SCIF) Sleep/Deep Ch. 2 Register Name Abbrev.
PAGE 1075
21. Serial Communication Interface with FIFO (SCIF) Sleep/Deep Ch. 4 Register Name Abbrev.
PAGE 1076
21. Serial Communication Interface with FIFO (SCIF) 21.3.1 Receive Shift Register (SCRSR) SCRSR is the register used to receive serial data. The SCIF sets serial data input from the SCIF_RXD pin in SCRSR in the order received, starting with the LSB (bit 0), and converts it to parallel data. When one byte of data has been received, it is transferred to SCFRDR, automatically. SCRSR cannot be directly read from and written to by the CPU. 21.3.
PAGE 1077
21. Serial Communication Interface with FIFO (SCIF) 21.3.3 Transmit Shift Register (SCTSR) SCTSR is a register used to transmit serial data. To perform serial data transmission, the SCIF first transfers transmit data from SCFTDR to SCTSR, then sends the data to the TXD pin starting with the LSB (bit 0). When transmission of one byte of serial data is completed, the next transmit data is automatically transferred from SCFTDR to SCTSR, and transmission started.
PAGE 1078
21. Serial Communication Interface with FIFO (SCIF) 21.3.5 Serial Mode Register (SCSMR) SCSMR is a 16-bit register used to set the SCIF's serial communication format and select the baud rate generator clock source. SCSMR can always be read from and written to by the CPU.
PAGE 1079
21. Serial Communication Interface with FIFO (SCIF) Bit Bit Name Initial Value R/W Description 5 PE 0 R/W Parity Enable In asynchronous mode, selects whether or not parity bit addition is performed in transmission, and parity bit checking is performed in reception. In clocked synchronous mode, parity bit addition and checking is disabled regardless of the PE bit setting.
PAGE 1080
21. Serial Communication Interface with FIFO (SCIF) Bit Bit Name Initial Value R/W Description 3 STOP 0 R/W Stop Bit Length In asynchronous mode, selects 1 or 2 bits as the stop bit length. The stop bit setting is valid only in asynchronous mode. Since the stop bit is not added in clocked synchronous mode, the STOP bit setting is invalid. 0: 1 stop bit*2 1: 2 stop bits*3 In reception, only the first stop bit is checked, regardless of the STOP bit setting.
PAGE 1081
21. Serial Communication Interface with FIFO (SCIF) 21.3.6 Serial Control Register (SCSCR) SCSCR is a register used to enable/disable transmission/reception by SCIF, serial clock output, interrupt requests, and to select transmission/reception clock source for the SCIF. SCSCR can always be read from and written to by the CPU.
PAGE 1082
21. Serial Communication Interface with FIFO (SCIF) Bit Bit Name Initial Value R/W Description 6 RIE 0 R/W Receive Interrupt Enable*1 Enables or disables generation of a receive-data-full interrupt (RXI) request when the RDF flag or DR flag in SCFSR is set to 1, a receive-error interrupt (ERI) request when the ER flag in SCFSR is set to 1, and a break interrupt (BRI) request when the BRK flag in SCFSR or the ORER flag in SCLSR is set to 1.
PAGE 1083
21. Serial Communication Interface with FIFO (SCIF) Bit Bit Name Initial Value R/W Description 4 RE 0 R/W Receive Enable Enables or disables the start of serial reception by the SCIF. Serial reception is started when a start bit or a synchronization clock input is detected in asynchronous mode or clocked synchronous mode, respectively, while the RE bit is set to 1.
PAGE 1084
21. Serial Communication Interface with FIFO (SCIF) Bit Bit Name Initial Value R/W Description 1 0 CKE1 CKE0 0 0 R/W R/W Clock Enable 1, 0 These bits select the SCIF clock source and whether to enable or disable the clock output from the SCIF_SCK pin. The CKE1 and CKE0 bits are used together to specify whether the SCIF_SCK pin functions as a serial clock output pin or a serial clock input pin.
PAGE 1085
21. Serial Communication Interface with FIFO (SCIF) 21.3.7 Serial Status Register n (SCFSR) SCFSR is a 16-bit register that consists of status flags that indicate the operating status of the SCIF. SCFSR can be always read from or written to by the CPU. However, 1 cannot be written to the ER, TEND, TDFE, BRK, RDF, and DR flags. Also note that in order to clear these flags they must be read as 1 beforehand. The FER flag and PER flag are read-only flags and cannot be modified.
PAGE 1086
21. Serial Communication Interface with FIFO (SCIF) Bit Bit Name Initial Value 7 ER 0 R/W*1 Receive Error Indicates that a framing error or parity error occurred during reception. The ER flag is not affected and retains its previous state when the RE bit in SCSCR is cleared to 0. When a receive error occurs, the receive data is still transferred to SCFRDR, and reception continues. The FER and PER bits in SCFSR can be used to determine whether there is a receive error in the readout data from SCFRDR.
PAGE 1087
21. Serial Communication Interface with FIFO (SCIF) Bit Bit Name Initial Value R/W Description 1 5 TDFE 1 R/W* Transmit FIFO Data Empty Indicates that data has been transferred from SCFTDR to SCTSR, the number of data bytes in SCFTDR has fallen to or below the transmit trigger data count set by the TTRG1 and TTRG0 bits in SCFCR, and new transmit data can be written to SCFTDR.
PAGE 1088
21. Serial Communication Interface with FIFO (SCIF) Bit Bit Name Initial Value R/W Description 3 FER 0 R Framing Error Display In asynchronous mode, indicates whether or not a framing error has been found in the data that is to be read from SCFRDR.
PAGE 1089
21. Serial Communication Interface with FIFO (SCIF) Bit 1 Bit Name RDF Initial Value 0 R/W Description 1 R/W* Receive FIFO Data Full Indicates that the received data has been transferred from SCRSR to SCFRDR, and the number of receive data bytes in SCFRDR is equal to or greater than the receive trigger count set by the RTRG1 and RTRG0 bits in SCFCR. 0: The number of receive data bytes in SCFRDR is less than the receive trigger setting count.
PAGE 1090
21. Serial Communication Interface with FIFO (SCIF) Bit 0 Bit Name DR Initial Value 0 R/W Description 1 R/W* Receive Data Ready In asynchronous mode, indicates that there are fewer than the receive trigger setting count of data bytes in SCFRDR, and no further data has arrived for at least 15 etu after the stop bit of the last data received. This is not set when using clocked synchronous mode.
PAGE 1091
21. Serial Communication Interface with FIFO (SCIF) 21.3.8 Bit Rate Register n (SCBRR) SCBRR is an 8-bit register that sets the serial transmission/reception bit rate in accordance with the baud rate generator operating clock selected by the CKS1 and CKS0 bits in SCSMR. SCBRR can always be read from and written to by the CPU. The SCBRR setting is found from the following equation.
PAGE 1092
21. Serial Communication Interface with FIFO (SCIF) 21.3.9 FIFO Control Register n (SCFCR) SCFCR is a register that performs data count resetting and trigger data number setting for transmit and receive FIFO registers, and also contains a loopback test enable bit. SCFCR can always be read from and written to by the CPU.
PAGE 1093
21. Serial Communication Interface with FIFO (SCIF) Bit Bit Name Initial Value R/W Description 5 TTRG1 0 R/W Transmit FIFO Data Count Trigger 4 TTRG0 0 R/W These bits are used to set the number of remaining transmit data bytes that sets the TDFE flag in SCFSR. The TDFE flag is set when the number of transmit data bytes in SCFTDR is equal to or less than the trigger setting count shown below.
PAGE 1094
21. Serial Communication Interface with FIFO (SCIF) 21.3.10 Transmit FIFO Data Count Register n (SCTFDR) SCTFDR is a 16-bit register that indicates the number of transmit data bytes stored in SCFTDR. SCTFDR can always be read from the CPU.
PAGE 1095
21. Serial Communication Interface with FIFO (SCIF) 21.3.11 Receive FIFO Data Count Register n (SCRFDR) SCRFDR is a 16-bit register that indicates the number of receive data bytes stored in SCFRDR. SCRFDR can always be read from the CPU.
PAGE 1096
21. Serial Communication Interface with FIFO (SCIF) 21.3.12 Serial Port Register n (SCSPTR) SCSPTR is a 16-bit readable/writable register that controls input/output and data for the port pins multiplexed with the serial communication interface (SCIF) pins at all times. Input data can be read from the RXD pin, and output data written to the TXD pin, and breaks in serial transmission/reception controlled, by means of bits 1 and 0.
PAGE 1097
21. Serial Communication Interface with FIFO (SCIF) Bit Bit Name Initial Value R/W Description 6 RTSDT* — R/W Serial Port SCIF_RTS Port Data Specifies the serial port SCIF_RTS pin input/output data. Input or output is specified by the RTSIO bit. In output mode, the RTSDT bit value is output to the SCIF_RTS pin. The SCIF_RTS pin value is read from the RTSDT bit regardless of the value of the RTSIO bit. The initial value of this bit after a power-on reset or manual reset is undefined.
PAGE 1098
21. Serial Communication Interface with FIFO (SCIF) Bit Bit Name Initial Value R/W Description 2 SCKDT — R/W Serial Port Clock Port Data Specifies the serial port SCIF_SCK pin input/output data. Input or output is specified by the SCKIO bit. In output mode, the SCKDT bit value is output to the SCIF_SCK pin. The SCIF_SCK pin value is read from the SCKDT bit regardless of the value of the SCKIO bit. The initial value of this bit after a power-on reset or manual reset is undefined.
PAGE 1099
21. Serial Communication Interface with FIFO (SCIF) 21.3.13 Line Status Register n (SCLSR) BIt: Initial value: R/W: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ORER 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W* Note: * Only 0 can be written to clear the flag. Bit Bit Name Initial Value R/W Description 15 to 1 — All 0 R Reserved These bits are always read as 0. The write value should always be 0.
PAGE 1100
21. Serial Communication Interface with FIFO (SCIF) 21.3.14 Serial Error Register n (SCRER) SCRER is a 16-bit register that indicates the number of receive errors in the data in SCFRDR. SCRER can always be read from the CPU.
PAGE 1101
21. Serial Communication Interface with FIFO (SCIF) 21.4 Operation 21.4.1 Overview The SCIF can perform serial communication in asynchronous mode, in which synchronization is achieved character by character and in clocked synchronous mode, in which synchronization is achieved with clock pulses. For details on asynchronous mode, see section 21.4.2, Operation in Asynchronous Mode.
PAGE 1102
21. Serial Communication Interface with FIFO (SCIF) Clocked Synchronous Mode • • • • Data length: Fixed at 8 bits LSB first for data transmission and reception Detection of overrun errors during reception Choice of peripheral clock (Pck) or SCIF_SCK pin input as SCIF clock source When peripheral clock (Pck) is selected: The SCIF operates on the baud rate generator clock and a serial clock is output to external devices.
PAGE 1103
21. Serial Communication Interface with FIFO (SCIF) Table 21.
PAGE 1104
21. Serial Communication Interface with FIFO (SCIF) 21.4.2 Operation in Asynchronous Mode In asynchronous mode, a character that consists of data with a start bit indicating the start of communication and a stop bit indicating the end of communication is transmitted or received. In this mode, serial communication is performed with synchronization achieved character by character. Inside the SCIF, the transmitter and receiver are independent units, enabling full-duplex communication.
PAGE 1105
21. Serial Communication Interface with FIFO (SCIF) (1) Data Transfer Format Table 21.6 shows the data transfer formats that can be used. Any of 8 transfer formats can be selected according to the SCSMR settings. Table 21.
PAGE 1106
21. Serial Communication Interface with FIFO (SCIF) (2) Clock Either an internal clock generated by the on-chip baud rate generator or an external clock input at the SCIF_SCK pin can be selected as the SCIF's serial clock, according to the settings of the C/A bit in SCSMR and the CKE1 and CKE0 bits in SCSCR. For details on SCIF clock source selection, see table 21.5. When an external clock is input to the SCIF_SCK pin, the clock frequency should be 16 times the bit rate used.
PAGE 1107
21. Serial Communication Interface with FIFO (SCIF) Figure 21.8 shows a sample SCIF initialization flowchart. Start of initialization [1] Set the clock selection in SCSCR. Be sure to clear bits TIE, RIE, TE, and RE to 0. Clear TE and RE bits in SCSCR to 0 [2] Set the data transfer format in SCSMR.
PAGE 1108
21. Serial Communication Interface with FIFO (SCIF) (4) Serial Data Transmission (Asynchronous Mode) Figure 21.9 shows a sample flowchart for serial transmission. Use the following procedure for serial data transmission after enabling the SCIF for transmission. Start of transmission [1] SCIF status check and transmit data write: Read SCFSR and check that the TDFE flag is set to 1, then write transmit data to SCFTDR, and clear the TDFE and TEND flags to 0.
PAGE 1109
21. Serial Communication Interface with FIFO (SCIF) In serial transmission, the SCIF operates as follows. 1. When data is written to SCFTDR, the SCIF transfers the data from SCFTDR to SCTSR and starts transmission. Confirm that the TDFE flag in SCFSR is set to 1 before writing transmit data to SCFTDR. The number of data bytes that can be written is at least 64 − (transmit trigger setting count). 2.
PAGE 1110
21. Serial Communication Interface with FIFO (SCIF) Figure 21.10 shows an example of the operation for transmission in asynchronous mode. Idle state (mark state) Start bit 1 SCIF_TXD Serial data 0 Data D0 Parity Stop Start bit bit bit D1 D7 0/1 1 0 Data D0 D1 Parity Stop bit bit D7 0/1 1 1 Idle state (mark state) TDFE TEND TXI interrupt TXI interrupt request Data written to SCFTDR request and TDFE read as 1 then cleared to 0 by TXI interrupt handler One frame Figure 21.
PAGE 1111
21. Serial Communication Interface with FIFO (SCIF) (5) Serial Data Reception (Asynchronous Mode) Figure 21.12 shows a sample flowchart for serial reception. Use the following procedure for serial data reception after enabling the SCIF for reception.
PAGE 1112
21. Serial Communication Interface with FIFO (SCIF) Error handling No ORER = 1? Yes Overrun error handling No ER = 1? Yes [1] Whether a framing error or parity error has occurred in the receive data that is to be read from SCFRDR can be ascertained from the FER and PER bits in SCFSR. [2] When a break signal is received, receive data (H'00) is not transferred to SCFRDR. However, note that the last data in SCFRDR is H'00, and the break data in which a framing error occurred is stored.
PAGE 1113
21. Serial Communication Interface with FIFO (SCIF) In serial reception, the SCIF operates as follows. 1. The SCIF monitors the transmission line, and if a 0-start bit is detected, performs internal synchronization and starts reception. 2. The received data is stored in SCRSR in LSB-to-MSB order. 3. The parity bit and stop bit are received. After receiving these bits, the SCIF carries out the following checks. (a) Stop bit check: The SCIF checks whether the stop bit is 1.
PAGE 1114
21. Serial Communication Interface with FIFO (SCIF) 5. When modem control is enabled, the SCIF_RTS signal is output when SCFRDR is empty. When SCIF_RTS is 0, reception is possible. When SCIF_RTS is 1, this indicates that SCFRDR contains bytes of data equal to or more than the SCIF_RTS output active trigger count. The SCIF_RTS output active trigger value is specified by bits 10 to 8 in SCFCR. For details, see section 21.3.9, FIFO Control Register n (SCFCR).
PAGE 1115
21. Serial Communication Interface with FIFO (SCIF) 21.4.3 Operation in Clocked Synchronous Mode Clocked synchronous mode, in which data is transmitted or received in synchronization with clock pulses, is suitable for fast serial communication. Since the transmitter and receiver are independent units in the SCIF, full-duplex communication can be performed by sharing the clock.
PAGE 1116
21. Serial Communication Interface with FIFO (SCIF) (1) Data Transfer Format A fixed 8-bit data format is used. No parity bit can be added. (2) Clock Either an internal clock generated by the on-chip baud rate generator or an external synchronization clock input at the SCIF_SCK pin can be selected as the SCIF's serial clock, according to the settings of the C/A bit in SCSMR and the CKE1 and CKE0 bits in SCSCR. For details on SCIF clock source selection, see table 21.5.
PAGE 1117
21. Serial Communication Interface with FIFO (SCIF) Start of initialization Clear TE and RE bits in SCSCR to 0 [1] [1] Leave the TE and RE bits cleared to 0 until the initialization almost ends. Be sure to clear the TIE, RIE, TE, and RE bits to 0. [2] Set the CKE1 and CKE0 bits. Set TFCL and RFCL bits in SCFCR to 1 to clear the FIFO buffer [3] Set the data transfer format in SCSMR. [4] Write a value corresponding to the bit rate into SCBRR. This is not necessary if an external clock is used.
PAGE 1118
21. Serial Communication Interface with FIFO (SCIF) (4) Serial Data Transmission (Clocked Synchronous Mode) Figure 21.17 shows a sample flowchart for serial transmission. Use the following procedure for serial data transmission after enabling the SCIF for transmission. [1] Initialization Start of transmission [1] SCIF initialization: See Sample SCIF Initialization Flowchart in figure 21.16.
PAGE 1119
21. Serial Communication Interface with FIFO (SCIF) In serial transmission, the SCIF operates as follows. 1. When data is written into SCFTDR, the SCIF transfers the data from SCFTDR to SCTSR and starts transmitting. Confirm that the TDFE flag in SCFSR is set to 1 before writing transmit data to SCFTDR. The number of data bytes that can be written is at least 64 (transmit trigger setting count). 2.
PAGE 1120
21. Serial Communication Interface with FIFO (SCIF) (5) Serial Data Reception (Clocked Synchronous Mode) Figure 21.19 shows a sample flowchart for serial reception. Use the following procedure for serial data reception after enabling the SCIF for reception. When switching the operating mode from asynchronous mode to clocked synchronous mode without initializing the SCIF, make sure that the ORER, PER7 to PER0, and FER7 to FER0 flags are cleared to 0.
PAGE 1121
21. Serial Communication Interface with FIFO (SCIF) Error handling No ORER = 1? Yes Overrun error handling Clear ORER flag in SCLSR to 0 End Figure 21.19 Sample Serial Reception Flowchart (2) In serial reception, the SCIF operates as follows. 1. The SCIF is initialized internally in synchronization with the input or output of the synchronization clock. 2. The receive data is stored in SCRSR in LSB-to-MSB order.
PAGE 1122
21. Serial Communication Interface with FIFO (SCIF) Synchronization clock Serial data SCIF_RXD Bit 7 LSB MSB Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 RDF ORER RXI interrupt request Data read from SCFRDR and RDF flag cleared to 0 by RXI interrupt handler RXI interrupt request BRI interrupt request by overrun error One frame Figure 21.20 Example of SCIF Reception Operation Rev.1.00 Jan.
PAGE 1123
21. Serial Communication Interface with FIFO (SCIF) (6) Transmitting and Receiving Serial Data Simultaneously (Clocked Synchronous Mode) Figure 21.21 shows a sample flowchart for transmitting and receiving data simultaneously. Use the following procedure for the simultaneous serial transmission/reception of serial data, after enabling the SCIF transmission/reception. Initialization [1] [1] SCIF initialization: See Sample SCIF Initialization Flowchart in figure 21.16.
PAGE 1124
21. Serial Communication Interface with FIFO (SCIF) 21.5 SCIF Interrupt Sources and the DMAC The SCIF has four interrupt sources for each channel: transmit-FIFO-data-empty interrupt (TXI) request, receive-error interrupt (ERI) request, receive-FIFO-data-full interrupt (RXI) request, and break interrupt (BRI) request. Table 21.7 shows the interrupt sources and their order of priority. The interrupt sources are enabled or disabled by means of the TIE, RIE, and REIE bits in SCSCR.
PAGE 1125
21. Serial Communication Interface with FIFO (SCIF) Table 21.
PAGE 1126
21. Serial Communication Interface with FIFO (SCIF) 21.6 Usage Notes Note the following when using the SCIF. (1) SCFTDR Writing and the TDFE Flag The TDFE flag in SCFSR is set when the number of transmit data bytes written in SCFTDR has fallen to or below the transmit trigger count set by bits TTRG1 and TTRG0 in SCFCR. After TDFE is set, transmit data up to the number of empty bytes in SCFTDR can be written, allowing efficient continuous transmission.
PAGE 1127
21. Serial Communication Interface with FIFO (SCIF) (4) Sending a Break Signal The input/output condition and level of the SCIF_TXD pin are determined by bits SPB2IO and SPB2DT in SCSPTR. This feature can be used to send a break signal. After the serial transmitter is initialized and until the TE bit is set to 1 (enabling transmission), the SCIF_TXD pin function is not selected and the value of the SPB2DT bit substitutes for the mark state.
PAGE 1128
21. Serial Communication Interface with FIFO (SCIF) Thus, the reception margin in asynchronous mode is given by formula (1). M= (0.5 - 1 2N ) - (L - 0.5) F - | D - 0.5 | (1 + F) × 100 % .................. (1) N M: Receive margin (%) N: Ratio of bit rate to clock (N = 16) D: Clock duty (D = 0 to 1.0) L: Frame length (L = 9 to 12) F: Absolute value of clock rate deviation From equation (1), if F = 0 and D = 0.5, the reception margin is 46.875%, as given by formula (2). When D = 0.5 and F = 0: M = (0.
PAGE 1129
22. Serial I/O with FIFO (SIOF) Section 22 Serial I/O with FIFO (SIOF) This LSI is equipped with a clock-synchronized serial I/O module with FIFO (SIOF). 22.
PAGE 1130
22. Serial I/O with FIFO (SIOF) Figure 22.1 shows a block diagram of the SIOF. SIOF interrupt request Peripheral bus Bus interface Control registers Transmit FIFO (32 bits × 16 stages) Transmit control data Pck Baud rate generator SIOF_MCLK 1/nMCLK Receive FIFO (32 bits × 16 stages) Receive control data Timing control SIOF_SCK SIOF_SYNC P/S S/P SIOF_TXD SIOF_RXD Figure 22.1 Block Diagram of SIOF Rev.1.00 Jan.
PAGE 1131
22. Serial I/O with FIFO (SIOF) 22.2 Input/Output Pins Table 22.1 shows the pin configuration. Table 22.
PAGE 1132
22. Serial I/O with FIFO (SIOF) 22.3 Register Descriptions Table 22.2 shows the register configuration of the SIOF. Table 22.3 shows the register states in each operating mode. Table 22.
PAGE 1133
22. Serial I/O with FIFO (SIOF) Table 22.
PAGE 1134
22. Serial I/O with FIFO (SIOF) 22.3.1 Mode Register (SIMDR) SIMDR is a 16-bit readable/writable register that sets the SIOF operating mode.
PAGE 1135
22. Serial I/O with FIFO (SIOF) Bit Bit Name Initial Value R/W Description 7 TXDIZ 0 R/W SIOF_TXD Pin Output when Transmission is Invalid* 0: High output when invalid 1: High-impedance state when invalid Note: Transmission is invalid when transmission is disabled, or when a slot that is not assigned as transmit data or control data is being transmitted. 6 RCIM 0 R/W Receive Control Data Interrupt Mode 0: Sets the RCRDY bit in SISTR when the contents of SIRCR change.
PAGE 1136
22. Serial I/O with FIFO (SIOF) 22.3.2 Control Register (SICTR) SICTR is a 16-bit readable/writable register that sets the SIOF operating state. BIt: 15 14 SCKE FSE Initial value: R/W: 0 R/W 0 R/W 13 12 11 10 9 8 7 6 5 4 3 2 — — — — TXE RXE — — — — — — 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R 0 R 0 R 0 R 0 R 0 R Bit Bit Name Initial Value R/W Description 15 SCKE 0 R/W Serial Clock Output Enable 1 0 TXRST RXRST 0 R/W 0 R/W This bit is valid in master mode.
PAGE 1137
22. Serial I/O with FIFO (SIOF) Bit Bit Name Initial Value R/W Description 8 RXE 0 R/W Receive Enable 0: Disables data reception from SIOF_RXD 1: Enables data reception from SIOF_RXD 7 to 2 ⎯ All 0 R • This bit setting becomes valid at the start of the next frame (at the rising edge of the SIOF_SYNC signal). • When the 1 setting for this bit becomes valid, the SIOF begins the reception of data from the SIOF_RXD pin.
PAGE 1138
22. Serial I/O with FIFO (SIOF) 22.3.3 Transmit Data Register (SITDR) SITDR is a 32-bit write-only register that specifies SIOF transmit data.
PAGE 1139
22. Serial I/O with FIFO (SIOF) 22.3.4 Receive Data Register (SIRDR) SIRDR is a 32-bit read-only register that reads receive data of the SIOF. SIRDR stores data in the receive FIFO.
PAGE 1140
22. Serial I/O with FIFO (SIOF) 22.3.5 Transmit Control Data Register (SITCR) SITCR is a 32-bit readable/writable register that specifies transmit control data of the SIOF. The setting of SITCR is valid only when bits FL3 to FL0 in SIMDR are set to 1xxx (x: any value). SITCR is initialized by the conditions shown in table 22.3, Register State in Each Operating Mode, or by a transmit reset by the TXRST bit in SICTR.
PAGE 1141
22. Serial I/O with FIFO (SIOF) 22.3.6 Receive Control Data Register (SIRCR) SIRCR is a 32-bit readable/writable register that stores receive control data of the SIOF. The setting of SIRCR is valid only when bits FL3 to FL0 in SIMDR are set to 1xxx (x: any value).
PAGE 1142
22. Serial I/O with FIFO (SIOF) 22.3.7 Status Register (SISTR) SISTR is a 16-bit readable/writable register that indicates the SIOF state. Each bit in this register becomes an SIOF interrupt source when the corresponding bit in SIIER is set to 1.
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22. Serial I/O with FIFO (SIOF) Bit Bit Name Initial Value R/W Description 12 TDREQ 0 R Transmit Data Transfer Request 0: Indicates that the size of empty space in the transmit FIFO does not exceed the size specified by the TFWM bit in SIFCTR. 1: Indicates that the size of empty space in the transmit FIFO exceeds the size specified by the TFWM bit in SIFCTR. A transmit data transfer request is issued when the empty space in the transmit FIFO exceeds the size specified by the TFWM bit in SIFCTR.
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22. Serial I/O with FIFO (SIOF) Bit Bit Name Initial Value R/W Description 9 RFFUL 0 R Receive FIFO Full 0: Receive FIFO not full 1: Receive FIFO full 8 RDREQ 0 R • This bit is valid when the RXE bit in SICTR is 1. • This bit indicates the state of the SIOF. If SIRDR is read from, this bit is automatically cleared to 0. • To enable the issuance of this interrupt source, set the RFFULE bit in SIIER to 1.
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22. Serial I/O with FIFO (SIOF) Bit Bit Name Initial Value R/W Description 5 SAERR 0 R/W Slot Assign Error 0: Indicates that no slot assign error occurs 1: Indicates that a slot assign error occurs A slot assign error occurs when the settings in SITDAR, SIRDAR, and SICDAR overlap. If a slot assign error occurs, the SIOF does not transmit data to the SIOF_TXD pin and does not receive data from the SIOF_RXD pin.
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22. Serial I/O with FIFO (SIOF) Bit Bit Name Initial Value R/W Description 3 TFOVF 0 R/W Transmit FIFO Overflow 0: Indicates that no transmit FIFO overflow occurs 1: Indicates that a transmit FIFO overflow occurs A transmit FIFO overflow means that there has been an attempt to write to SITDR when the transmit FIFO is full. When a transmit FIFO overflow occurs, the SIOF indicates overflow, and writing is invalid. 2 TFUDF 0 R/W • This bit is valid when the TXE bit in SICTR is 1.
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22. Serial I/O with FIFO (SIOF) Bit Bit Name Initial Value R/W Description 1 RFUDF 0 R/W Receive FIFO Underflow 0: Indicates that no receive FIFO underflow occurs 1: Indicates that a receive FIFO underflow occurs A receive FIFO underflow means that reading of SIRDR has occurred when the receive FIFO is empty. When a receive FIFO underflow occurs, the value of data read from SIRDR is not guaranteed. 0 RFOVF 0 R/W • This bit is valid when the RXE bit in SICTR is 1.
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22. Serial I/O with FIFO (SIOF) 22.3.8 Interrupt Enable Register (SIIER) SIIER is a 16-bit readable/writable register that enables the issuance of SIOF interrupts. When each bit in this register is set to 1 and the corresponding bit in SISTR is set to 1, the SIOF issues an interrupt.
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22.
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22. Serial I/O with FIFO (SIOF) 22.3.9 FIFO Control Register (SIFCTR) SIFCTR is a 16-bit readable/writable register that indicates the area available for the transmit/receive FIFO transfer.
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22. Serial I/O with FIFO (SIOF) Bit Bit Name Initial Value R/W Description 7 to 5 RFWM[2:0] 000 R/W Receive FIFO Watermark 000: Issue a transfer request when 1 stage or more of the receive FIFO are valid. 001: Setting prohibited 010: Setting prohibited 011: Setting prohibited 100: Issue a transfer request when 4 or more stages of the receive FIFO are valid. 101: Issue a transfer request when 8 or more stages of the receive FIFO are valid.
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22. Serial I/O with FIFO (SIOF) 22.3.10 Clock Select Register (SISCR) SISCR is a 16-bit readable/writable register that sets the serial clock generation conditions for the master clock. SCSCR can be specified when the TRMD1 and TRMD0 bits in SIMDR are set to B'10 or B'11.
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22. Serial I/O with FIFO (SIOF) Bit Bit Name Initial Value R/W Description 2 to 0 BRDV[2:0] 000 R/W Baud Rate Generator's Division Ratio Setting These bits set the frequency division ratio for the output stage of the baud rate generator.
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22. Serial I/O with FIFO (SIOF) Bit Bit Name Initial Value R/W Description 11 to 8 TDLA[3:0] 0000 R/W Transmit Left-Channel Data Assigns 3 to 0 These bits specify the position of left-channel data in a transmit frame as B'0000 (0) to B'1110 (14). 1111: Setting prohibited • 7 TDRE 0 R/W Transmit data for the left channel is specified in the SITDL bit in SITDR.
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22. Serial I/O with FIFO (SIOF) 22.3.12 Receive Data Assign Register (SIRDAR) SIRDAR is a 16-bit readable/writable register that specifies the position of the receive data in a frame.
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22. Serial I/O with FIFO (SIOF) 22.3.13 Control Data Assign Register (SICDAR) SICDAR is a 16-bit readable/writable register that specifies the position of the control data in a frame. SICDAR can be specified only when the FL bits in SIMDR are set to 1xxx (x: don't care.).
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22. Serial I/O with FIFO (SIOF) Bit Bit Name Initial Value R/W Description 3 to 0 CD1A[3:0] 0000 R/W Control Channel 1 Data Assigns 3 to 0 These bits specify the position of control channel 1 data in a receive or transmit frame as B'0000 (0) to B'1110 (14). 1111: Setting prohibited • Transmit data for the control channel 1 data is specified in the SITD1 bit in SITCR. • Receive data for the control channel 1 data is stored in the SIRD1 bit in SIRCR. Rev.1.00 Jan.
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22. Serial I/O with FIFO (SIOF) 22.4 Operation 22.4.1 Serial Clocks (1) Master/Slave Modes The following two modes are available as the SIOF clock mode. • Slave mode: SIOF_SCK, SIOF_SYNC input • Master mode: SIOF_SCK, SIOF_SYNC output (2) Baud Rate Generator In SIOF master mode, the baud rate generator (BRG) is used to generate the serial clock.
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22. Serial I/O with FIFO (SIOF) Table 22.5 shows an example of serial clock frequency. Table 22.5 SIOF Serial Clock Frequency Sampling Rate* Frame Length 8 kHz 44.1 kHz 48 kHz 32 bits 256 kHz 1.4112 MHz 1.536 MHz 64 bits 512 kHz 2.8224 MHz 3.072 MHz 128 bits 1.024 MHz 5.6448 MHz 6.144 MHz 256 bits 2.048 MHz 11.289 MHz 12.289 MHz Note: * 22.4.2 (1) Control data formats are valid when the FL bits are set to 1xxx (x: Don't care).
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22. Serial I/O with FIFO (SIOF) (a) Synchronous pulse 1 frame SIOF_SCK SIOF_SYNC SIOF_TXD SIOF_RXD Start bit data 1-bit delay (b) L/R 1 frame SIOF_SCK SIOF_SYNC SIOF_TXD SIOF_RXD Lch. Start bit of left channel data (1/2 frame length) No delay Rch. Start bit of right channel data (1/2 frame length) Figure 22.
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22. Serial I/O with FIFO (SIOF) (a) Falling-edge sampling (REDG = 0) (b) Rising-edge sampling (REDG = 1) SIOF_SCK SIOF_SCK SIOF_SYNC SIOF_SYNC SIOF_TXD SIOF_TXD SIOF_RXD SIOF_RXD Receive timing Transmit timing Receive timing Transmit timing Figure 22.4 SIOF Transmit/Receive Timing 22.4.3 Transfer Data Format The SIOF performs the following transfer.
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22. Serial I/O with FIFO (SIOF) (2) Frame Length The frame length to be transferred by the SIOF is specified by the FL3 to FL0 bits in SIMDR. Table 22.7 shows the relationship between the setting values and frame length. Table 22.
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22. Serial I/O with FIFO (SIOF) 22.4.4 (1) Register Allocation of Transfer Data Transmit/Receive Data Writing and reading of transmit/receive data is performed for the following registers. • Transmit data writing: SITDR (32-bit access) • Receive data reading: SIRDR (32-bit access) Figure 22.5 shows the transmit/receive data and the SITDR and SIRDR bit alignment.
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22. Serial I/O with FIFO (SIOF) Table 22.8 Audio Mode Specification for Transmit Data Bit Mode TDLE TDRE TLREP Monaural 1 0 x Stereo 1 1 0 Left and right same audio output 1 1 1 Legend: x: Don't care Table 22.9 Audio Mode Specification for Receive Data Bit Mode RDLE RDRE Monaural 1 0 Stereo 1 1 Note: Left and right same audio mode is not supported in receive data. To execute 8-bit monaural transmission or reception, use the left channel.
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22. Serial I/O with FIFO (SIOF) The number of channels in control data is specified by the CD0E and CD1E bits in SICDAR. Table 22.10 shows the relationship between the number of channels in control data and bit settings. Table 22.10 Number of Channels in Control Data Bit Number of Channels CD0E CD1E 1 1 0 2 1 1 Note: To use only one channel in control data, use channel 0. 22.4.5 Control Data Interface Control data performs control command output to the CODEC and status input from the CODEC.
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22. Serial I/O with FIFO (SIOF) (2) Control by Secondary FS (Slave Mode 2) The CODEC normally outputs the SIOF_SYNC signal as synchronization pulse (FS). In this method, the CODEC outputs the secondary FS specific to the control data transfer after 1/2 frame time has been passed (not the normal FS output timing) to transmit or receive control data. This method is valid for SIOF slave mode. The following summarizes the control data interface procedure by the secondary FS.
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22. Serial I/O with FIFO (SIOF) 22.4.6 (1) FIFO Overview The transmit and receive FIFO systems of the SIOF have the following features. • 16-stage 32-bit FIFOs for transmission and reception • The FIFO pointer can be updated in one read or write cycle regardless of access size of the CPU and DMAC. (One-stage 32-bit FIFO access cannot be divided into multiple accesses.) (2) Transfer Request The transfer request of the FIFO can be issued to the CPU or DMAC as the following interrupt sources.
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22. Serial I/O with FIFO (SIOF) Table 22.12 Conditions to Issue Receive Request RFWM2 to RFWM0 Number of Requested Stages* Receive Request Used Areas 000 1 Valid data is 1 stage or more Smallest 100 4 Valid data is 4 stages or more 101 8 Valid data is 8 stages or more 110 12 Valid data is 12 stages or more 111 16 Valid data is 16 stages Note: * Largest The number of requested stages is the number of stages in transmit/receive FIFO.
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22. Serial I/O with FIFO (SIOF) 22.4.7 Transmit and Receive Procedures Set each register after setting the PFC. (1) Transmission in Master Mode Figure 22.9 shows an example of settings and operation for master mode transmission. No.
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22. Serial I/O with FIFO (SIOF) (2) Reception in Master Mode Figure 22.10 shows an example of settings and operation for master mode reception. No.
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22. Serial I/O with FIFO (SIOF) (3) Transmission in Slave Mode Figure 22.11 shows an example of settings and operation for slave mode transmission. No.
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22. Serial I/O with FIFO (SIOF) (4) Reception in Slave Mode Figure 22.12 shows an example of settings and operation for slave mode reception. No.
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22. Serial I/O with FIFO (SIOF) (5) Transmit/Receive Reset The SIOF can separately reset the transmit and receive units by setting the following bits to 1. • Transmit reset: TXRST bit in SICTR • Receive reset: RXRST bit in SICTR Table 22.13 shows the details on initialization upon transmit or receive reset. Table 22.
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22. Serial I/O with FIFO (SIOF) 22.4.8 Interrupts The SIOF has one type of interrupt. (1) Interrupt Sources Interrupts can be issued by several sources. Each source is shown as an SIOF status in SISTR. Table 22.14 lists the SIOF interrupt sources. Table 22.14 SIOF Interrupt Sources No. Classification Bit Name Function Name Description 1 TDREQ Transmit FIFO transfer request The transmit FIFO stores data of specified size or more. TFEMP Transmit FIFO empty The transmit FIFO is empty.
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22. Serial I/O with FIFO (SIOF) (2) Regarding Transmit and Receive Classification The transmit sources and receive sources are signals indicating the state; after being set, if the state changes, they are automatically cleared by the SIOF. When the DMA transfer is used, a DMA transfer request is pulled low for one cycle at the end of DMA transfer. (3) Processing when Errors Occur On occurrence of each of the errors indicated as a status in SISTR, the SIOF performs the following operations.
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22. Serial I/O with FIFO (SIOF) 22.4.9 Transmit and Receive Timing Figures 22.13 to 22.19 show examples of the SIOF serial transmission and reception. (1) 8-bit Monaural Data (1) Synchronous pulse method, falling edge sampling, slot No.0 used for transmit and receive data, a frame length = 8 bits 1 frame SIOF_SCK SIOF_SYNC SIOF_TXD L-channel data SIOF_RXD Slot No.
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22. Serial I/O with FIFO (SIOF) (2) 8-bit Monaural Data (2) Synchronous pulse method, falling edge sampling, slot No.0 used for transmit and receive data, and frame length = 16 bits 1 frame SIOF_SCK SIOF_SYNC SIOF_TXD L-channel data SIOF_RXD Slot No.0 Slot No.
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22. Serial I/O with FIFO (SIOF) (4) 16-bit Stereo Data (1) L/R method, rising edge sampling, slot No.0 used for left-channel data, slot No.1 used for rightchannel data, and frame length = 32 bits 1 frame SIOF_SCK SIOF_SYNC SIOF_TXD L-channel data R-channel data Slot No.0 Slot No.
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22. Serial I/O with FIFO (SIOF) (6) 16-bit Stereo Data (3) Synchronous pulse method, falling edge sampling, slot No.0 used for left-channel data, slot No.1 used for right-channel data, slot No.2 used for control channel 0 data, slot No.3 used for control channel 1 data, and frame length = 128 bits 1 frame SIOF_SCK SIOF_SYNC SIOF_TXD SIOF_RXD L-channel data R-channel data Control channel 0 Control channel 1 Slot No.0 Slot No.1 Slot No.2 Slot No.3 Slot No.4 Slot No.5 Slot No.6 Slot No.
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22. Serial I/O with FIFO (SIOF) (8) Synchronization-Pulse Output Mode at End of Each Slot (SYNCAT Bit = 1) Synchronous pulse method, falling edge sampling, slot No.0 used for left-channel data, slot No.1 used for right-channel data, slot No.2 used for control channel 0 data, slot No.3 used for control channel 1 data, and frame length = 128 bits 1 frame SIOF_SCK SIOF_SYNC SIOF_TXD SIOF_RXD L-channel data R-channel data Control channel 0 Control channel 1 Slot No.0 Slot No.1 Slot No.2 Slot No.
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23. Serial Peripheral Interface (HSPI) Section 23 Serial Peripheral Interface (HSPI) This LSI incorporates one channel of the Serial Protocol Interface (HSPI). 23.1 Features The HSPI has the following features. • Operating mode: Master mode or Slave mode. • The transmit and receive sections within the module are double buffered to allow duplex communication. • A flexible peripheral clock (Pck) division strategy allows a wide range of bit rates to be supported.
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23. Serial Peripheral Interface (HSPI) Figure 23.1 is a block diagram of the HSPI. Peripheral bus Bus interface Registers HSPI_CS System control SPCR SPSR SPSCR SPTBR Transmit FIFO SPRBR Receive FIFO (Eight entries for each) In FIFO mode HSPI_RX LSB MSB Shift register HSPI_TX Pck Clock division Polarity selection SCK generator Figure 23.1 Block Diagram of HSPI Rev.1.00 Jan.
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23. Serial Peripheral Interface (HSPI) 23.2 Input/Output Pins The input/output pins of the HSPI is shown in table 23.1. Table 23.1 Pin Configuration Pin Name Abbrev. I/O Description Serial bit clock pin HSPI_CLK I/O Clock input/output Transmit data pin HSPI_TX Output Transmit data output Receive data pin HSPI_RX Input Receive data input Chip select pin HSPI_CS I/O Chip select 23.3 Register Descriptions Table 23.2 Register Configuration (1) Register Name Abbrev.
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23. Serial Peripheral Interface (HSPI) Table 23.3 Register Configuration (2) Register Name Manual Reset Power-on Reset by WDT/ by PRESET Multiple Abbrev.
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23. Serial Peripheral Interface (HSPI) 23.3.1 Control Register (SPCR) SPCR is a 32-bit readable/writable register that controls the transfer data of shift timing and specifies the clock polarity and frequency.
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23. Serial Peripheral Interface (HSPI) Bit Bit Name Initial Value R/W Description 5 IDIV 0 R/W Initial Clock Division Ratio 0: The peripheral clock (Pck) is divided by a factor of 4 initially to create an intermediate frequency, which is further divided to create the serial clock for master mode. 1: The peripheral clock (Pck) is divided by a factor of 32 initially to create an intermediate frequency, which is further divided to create the serial clock for master mode.
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23. Serial Peripheral Interface (HSPI) The serial clock frequency can be computed using the following formula: Serial clock frequency = Peripheral clock frequency (Initial division ratio × (Clock division count + 1) × 2) When the HSPI is configured as a slave, the IDIV and CLKC bits are ignored and the HSPI synchronizes to the externally supplied serial clock. The maximum value of the external serial clock that the module can operate with is Pck / 8.
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23. Serial Peripheral Interface (HSPI) 23.3.2 Status Register (SPSR) SPSR is a 32-bit readable/writable register. Through the status flags in SPSR, it can be confirmed whether or not the system is correctly operating. If the ROIE bit in SPSCR is set to 1, an interrupt request is generated due to the occurrence of the receive buffer overrun error or the warning of the receive buffer overrun error.
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23. Serial Peripheral Interface (HSPI) Bit Bit Name Initial Value R/W Description 8 TXEM 1 R Transmit FIFO Empty Flag This status flag is enabled only in FIFO mode. The flag is set to 1 when the transmit FIFO is empty of data to transmit. It is cleared to 0 when data is written to the transmit FIFO. If TXEM = 1 and TEIE = 1, an interrupt is generated. 7 RXFU 0 R Receive FIFO Full Flag This status flag is enabled only in FIFO mode.
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23. Serial Peripheral Interface (HSPI) Bit Bit Name Initial Value R/W Description 3 RXOW 0 R/W* Receive Buffer Overrun Warning Flag This status flag is set to 1 when a new serial data transfer has started before the previous received data is read from SPRBR. The RXOW remains set to 1 until writing 0 to this bit position. If RXOW= 1 and ROIE = 1, an interrupt is generated.
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23. Serial Peripheral Interface (HSPI) 23.3.3 System Control Register (SPSCR) SPSCR is a 32-bit readable/writable register that enables or disables interrupts or FIFO mode, selects either LSB first or MSB first in transmitting/receiving data, and master or slave mode. If any of the FFEN, LMSB, CSA, or MASL bit values are changed, the module will undergo a software reset.
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23. Serial Peripheral Interface (HSPI) Bit Bit Name Initial Value R/W Description 8 FFEN 0 R/W FIFO Mode Enable Enables or disables the FIFO mode. When FIFO mode is enabled, two 8-entry FIFOs are made available, one for transmit data and one for receive data. These FIFOs are read and written via SPTBR and SPRBR, respectively. When FIFO mode is disabled, the SPTBR and SPRBR are used directly so new data must be written to SPTBR and read from SPRBR for each and every transfer through the HSPI bus.
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23. Serial Peripheral Interface (HSPI) Bit Bit Name Initial Value R/W Description 2 RXDE 0 R/W Receive DMA Enable 0: Receive DMA transfer request disabled 1: Receive DMA transfer request enabled 1 TXDE 0 R/W Transmit DMA Enable 0: Transmit DMA transfer request disabled 1: Transmit DMA transfer request enabled 0 MASL 0 R/W Master/Slave Select Bit 0: HSPI module configured as a slave 1: HSPI module configured as a master 23.3.
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23. Serial Peripheral Interface (HSPI) 23.3.5 Receive Buffer Register (SPRBR) SPRBR is a 32-bit read-only register that stores received data.
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23. Serial Peripheral Interface (HSPI) 23.4 Operation 23.4.1 Operation Overview with FIFO Mode Disabled Figure 23.2 shows the flow of a transmit/receive operation procedure. Start Reset the system Select master or slave operation by setting the MASL bit in SPSCR Select required interrupts by setting TFIE and ROIE bits in SPSCR Check if SPTBR is empty by reading the TXFL bit in SPSR No Yes Write data to SPTBR Yes TX/RX data to/from slave Another transmit required? No End Figure 23.
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23. Serial Peripheral Interface (HSPI) The HSPI_CS pin should be used to select the HSPI module and prepare it to receive data from an external master when the HSPI is configured as a slave. When the FBS bit in SPCR is 0, the HSPI_CS pin must be driven high between successive bytes (the HSPI_CS pin must be driven high after a byte transfer). When FBS = 1, the HSPI_CS pin can stay low for several byte transmissions.
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23. Serial Peripheral Interface (HSPI) 23.4.3 Timing Diagrams The following diagrams explain the timing relationship of all shift and sample processes in the HSPI. Figure 23.3 shows the conditions when FBS = 0, figure 23.4 shows the conditions when FBS = 0 (continuous transfer), figure 23.5 shows the conditions when FBS = 1, and figure 23.6 shows the conditions when FBS = 1 (continuous transfer).
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23. Serial Peripheral Interface (HSPI) Data transfer cycle 1 2 3 4 5 6 7 8 HSPI_TX MSB 6 5 4 3 2 1 LSB HSPI_RX * MSB 6 5 4 3 2 1 HSPI_CLK (CLKP = 0) HSPI_CLK (CLKP = 1) LSB HSPI_CX Figure 23.5 Timing Conditions when FBS = 1 Data transfer cycle 1 2 HSPI_TX MSB 6 HSPI_RX * MSB 6 .. 8 9 10 LSB MSB 6 MSB 6 .. 16 HSPI_CLK (CLKP = 0) HSPI_CLK (CLKP = 1) LSB * LSB LSB HSPI_CS Figure 23.
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23. Serial Peripheral Interface (HSPI) 23.4.4 HSPI Software Reset If any of the control bits, except for SPCR and the interrupt and chip select value bits of SPSCR, are changed, then the HSPI software reset is generated. The receive and transmit FIFO pointers can be initialized by the HSPI software reset. The data transmission after the HSPI software reset should conform to transmitting and receiving protocol of HSPI and be performed from the beginning; otherwise, correct operation is not guaranteed.
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23. Serial Peripheral Interface (HSPI) 23.4.7 Flags and Interrupt Timing The interrupt timing when the flags of the status register (SPSR) and the system control register (SPSCR) are set is shown in figure 23.7. HSPI_CLK HSPI_CS Pck Internal interrupt Flags (SPSR) Interrupt Figure 23.7 Flags and Interrupt Timing If an interrupt cause (receive FIFO halfway, etc.) occurs, it is reflected to the status register (SPSR) in synchronization with Pck, and an interrupt occurs. 23.4.
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24. Multimedia Card Interface (MMCIF) Section 24 Multimedia Card Interface (MMCIF) This LSI supports a multimedia card interface (MMCIF). The MMC mode interface can be utilized. The MMCIF is a clock-synchronous serial interface that transmits/receives data that is distinguished in terms of command and response. A number of commands/responses are predefined in the multimedia card.
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24. Multimedia Card Interface (MMCIF) Figure 24.1 shows a block diagram of the MMCIF. Port MMCIF MMCDAT Data transmission/ reception control Peripheral bus Peripheral bus interface FIFO Command transmission/ response reception control MMCCMD Interrupt control FSTAT TRAN ERR FRDY MMC mode control Card clock generator MMCCLK Figure 24.1 Block Diagram of MMCIF 24.2 Input/Output Pins Table 24.1 summarizes the pins of the MMCIF. Table 24.
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24. Multimedia Card Interface (MMCIF) 24.3 Register Descriptions Table 24.2 shows the MMCIF register configuration. Table 24.2 Register Configuration (1) Register Name Abbrev.
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24. Multimedia Card Interface (MMCIF) Register Name Abbrev.
PAGE 1205
24. Multimedia Card Interface (MMCIF) Table 24.3 Register Configuration (2) Power-on Reset by Manual PRESET Reset by WDT/ Sleep by Pin/WDT/ Multiple SLEEP Register Name Abbrev.
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24. Multimedia Card Interface (MMCIF) Power-on Reset by Manual Reset PRESET by WDT/ Sleep by Pin/WDT/ Multiple SLEEP Register Name Abbrev.
PAGE 1207
24. Multimedia Card Interface (MMCIF) 24.3.1 Command Registers 0 to 5 (CMDR0 to CMDR5) The CMDR registers are six 8-bit registers. A command is written to CMDR as shown in table 24.4, and the command is transmitted when the CMDSTART bit in CMDSTRT is set to 1. Each command is transmitted in order form the MSB (bit 7) in CMDR0 to the LSB (bit 0) in CMDR5. Table 24.4 CMDR Configuration Register Contents Operation CMDR0 to CMDR4 Command argument Write command arguments.
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24. Multimedia Card Interface (MMCIF) (2) CMDR5 Bit: 7 6 5 Initial value: R/W: 0 R 0 R 0 R 4 3 2 1 0 R 0 R 0 R 0 R CRC 0 End 0 R Bit Bit Name Initial Value R/W Description 7 to 1 CRC All 0 R These bits are always read as 0. The write value should always be 0. 0 End 0 R This bit is always read as 0. The write value should always be 0. 24.3.
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24. Multimedia Card Interface (MMCIF) Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ CMD START 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W Bit Bit Name Initial Value R/W Description 7 to 1 — All 0 R Reserved These bits are always read as 0. The write value should always be 0. 0 CMDSTART 0 R/W Starts command transmission when 1 is written. This bit is automatically cleared to 0 after the MMCIF received the CMDSTART command.
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24. Multimedia Card Interface (MMCIF) Bit Bit Name Initial Value R/W Description 6 — 0 R Reserved This bit is always read as 0. The write value should always be 0. 5 RD_CONTI 0 R/W Read Continue Read data reception is resumed when 1 is written while the sequence has been halted by FIFO full or termination of block reading in multiple block read. This bit is cleared to 0 automatically when 1 is written and the MMCIF received the RD_CONTI command.
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24. Multimedia Card Interface (MMCIF) In write data transmission, the contents of the command response and data response should be analyzed, and then transmission should be triggered. In addition, the data transmission should be temporarily halted by FIFO full/empty, and it should be resumed when the preparation has been completed.
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24. Multimedia Card Interface (MMCIF) Initial Value Bit Bit Name 5 FIFO_EMPTY 0 R/W Description R FIFO Empty This bit is set to 1 when the FIFO becomes empty while data is being sent to the card, and cleared to 0 when DATA_EN is set to 1 or the command sequence is completed. Indicates whether the FIFO holds data or not. 0: The FIFO includes data. 1: The FIFO is empty. 4 CWRE 0 R Command Register Write Enable Indicates whether the CMDR command is being transmitted or has been transmitted.
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24. Multimedia Card Interface (MMCIF) Bit Bit Name Initial Value R/W Description 0 REQ 0 R Interrupt Request Indicates whether an interrupt is requested or not. When any of the INTSTR0, INTSTR1 and INTSTR2 flags is set, this bit is set to 1. Setting of the INTSTR0, INTSTR1 and INTSTR2 flags is controlled by the enable bits in INTCR0, INTSTR1 and INTCR2. 0: No interrupt requested. 1: Interrupt requested. 24.3.
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24. Multimedia Card Interface (MMCIF) Bit Bit Name Initial Value R/W Description 4 DTIE 0 R/W Data Transfer End Interrupt Flag Setting Enable 0: Disables data transfer end interrupt (disables DTI flag setting). 1: Enables data transfer end interrupt (enables DTI flag setting). 3 CRPIE 0 R/W Command Response Receive End Interrupt Flag Setting Enable 0: Disables command response receive end interrupt (disables CRPI flag setting).
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24. Multimedia Card Interface (MMCIF) (2) INTCR1 Bit: 7 6 INTR INTR Q2E Q1E Initial value: 0 0 R/W: R/W R/W 5 INTR Q0E 0 R/W 4 3 ⎯ ⎯ 0 R 0 R 2 1 CRCE DTE RIE RIE 0 0 R/W R/W Bit Bit Name Initial Value R/W Description 7 INTRQ2E 0 R/W ERR Interrupt Enable 0 CTE RIE 0 R/W 0: Disables ERR interrupt. 1: Enables ERR interrupt. 6 INTRQ1E 0 R/W TRAN Interrupt Enable 0: Disables TRAN interrupt. 1: Enables TRAN interrupt.
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24. Multimedia Card Interface (MMCIF) (3) INTCR2 Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 INTR Q3E ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ FRDYIE 0 R/W 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W Bit Bit Name Initial Value R/W Description 7 INTRQ3E 0 R/W FRDY Interrupt Enable 0: Disables FRDY interrupt. 1: Enables FRDY interrupt. 6 to 1 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0.
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24. Multimedia Card Interface (MMCIF) 24.3.6 Interrupt Status Registers 0 to 2 (INTSTR0 to INTSTR2) The INTSTR registers enable or disable MMCIF interrupts FSTAT, TRAN, ERR and FRDY, and interrupt flags.
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24. Multimedia Card Interface (MMCIF) Bit Bit Name Initial Value R/W Description Interrupt output 5 DRPI 0 R/W Data Response Interrupt Flag TRAN 0: No interrupt [Clearing condition] Write 0 after reading DRPI = 1. (Writing 1 is invalid) 1: Interrupt requested [Setting condition] When the CRC status is received while DRPIE = 1. 4 DTI 0 R/W Data Transfer End Interrupt Flag TRAN 0: No interrupt [Clearing condition] Write 0 after reading DTI = 1.
PAGE 1219
24. Multimedia Card Interface (MMCIF) Bit Bit Name Initial Value R/W Description Interrupt output 2 CMDI 0 R/W Command Transmit End Interrupt Flag TRAN 0: No interrupt [Clearing condition] Write 0 after reading CMDI = 1. (Writing 1 is invalid) 1: Interrupt requested [Setting condition] When command transmission ends while CMDIE = 1. (When the CWRE bit in CSTR is cleared.) 1 DBSYI 0 R/W Data Busy End Interrupt Flag TRAN 0: No interrupt [Clearing condition] Write 0 after reading DBSYI = 1.
PAGE 1220
24. Multimedia Card Interface (MMCIF) (2) INTSTR1 Bit: Initial value: R/W: 7 6 5 4 3 ⎯ ⎯ ⎯ ⎯ ⎯ 0 R 0 R 0 R 0 R 0 R Bit Bit Name Initial Value R/W 7 to 3 — All 0 R 2 1 0 CRC DTERI CTERI ERI 0 0 0 R/W R/W R/W Description Interrupt output Reserved — These bits are always read as 0. The write value should always be 0. 2 CRCERI 0 R/W CRC Error Interrupt Flag ERR 0: No interrupt [Clearing condition] Write 0 after reading CRCERI = 1.
PAGE 1221
24. Multimedia Card Interface (MMCIF) Bit Bit Name Initial Value R/W Description Interrupt output 0 CTERI 0 R/W Command Timeout Error Interrupt Flag ERR 0: No interrupt [Clearing condition] Write 0 after reading CTERI = 1. (Writing 1 is invalid) 1: Interrupt requested [Setting condition] When a command timeout error specified in TOCR occurs while CTERIE = 1. Rev.1.00 Jan.
PAGE 1222
24. Multimedia Card Interface (MMCIF) (3) INTSTR2 Bit: Initial value: R/W: 7 6 5 4 3 2 — — — — — — 0 R 0 R 0 R 0 R 0 R 0 R 1 0 FRDY FRDYI _TU — 0 R R/W Bit Bit Name Initial Value R/W Description Interrupt output 7 to 2 ⎯ All 0 R Reserved ⎯ These bits are always read as 0. The write value should always be 0.
PAGE 1223
24. Multimedia Card Interface (MMCIF) 24.3.7 Transfer Clock Control Register (CLKON) CLKON controls the transfer clock frequency and clock ON/OFF. At this time, use a sufficiently slow clock for transfer through open-drain type output in MMC mode. In a command sequence, do not perform clock ON/OFF or frequency modification.
PAGE 1224
24. Multimedia Card Interface (MMCIF) 24.3.8 Command Timeout Control Register (CTOCR) CTOCR specifies the period to generate a timeout for the command response. The counter (CTOUTC), to which the peripheral bus does not have access, counts the transfer clock to monitor the command timeout. The initial value of CTOUTC is 0, and CTOUTC starts counting the transfer clock from the start of command transmission.
PAGE 1225
24. Multimedia Card Interface (MMCIF) 24.3.9 Transfer Byte Number Count Register (TBCR) TBCR is an 8-bit readable/writable register that specifies the number of bytes to be transferred (block size) for each single block transfer command. TBCR specifies the number of data block bytes not including the start bit, end bit, and CRC. The multiple block transfer command corresponds to the number of bytes of each data block. This setting is ignored by the stream transfer command.
PAGE 1226
24. Multimedia Card Interface (MMCIF) 24.3.10 Mode Register (MODER) MODER is an 8-bit readable/writable register that specifies the MMCIF operating mode. The following sequence should be repeated when the MMCIF uses the multimedia card: Send a command, wait for the end of the command sequence and the end of the data busy state, and send a next command.
PAGE 1227
24. Multimedia Card Interface (MMCIF) 24.3.11 Command Type Register (CMDTYR) CMDTYR is an 8-bit readable/writable register that specifies the command format in conjunction with RSPTYR. Bits TY1 and TY0 specify the existence and direction of transfer data, and bits TY6 to TY2 specify the additional settings. All of bits TY6 to TY2 should be cleared to 0 or only one of them should be set to 1. Bits TY6 to TY2 can only be set to 1 if the corresponding settings in TY1 and TY0 allow that setting.
PAGE 1228
24. Multimedia Card Interface (MMCIF) Bit Bit Name Initial Value R/W Description 3 TY3 0 R/W Type 3 Set this bit to 1 when specifying stream transfer. Bits TY1 and TY0 should be set to 01 or 10. The command sequence of the stream transfer specified by this bit ends when it is aborted by the CMD12 command. 2 TY2 0 R/W Type 2 Set this bit to 1 when specifying a multiple block transfer. Bits TY1 and TY0 should be set to 01 or 10.
PAGE 1229
24. Multimedia Card Interface (MMCIF) Bit Bit Name Initial Value R/W Description 6 RTY6 0 R/W Response Type 5 Sets data busy status from the MMC card. This bit is set to perform CRC check for the response (R2 response of MMC mode) when the command that reads, as a response, the register value of the multimedia card, including CRC7, is executed. RTY2 to RTY0 must be set to 101. 5 RTY5 0 R/W Response Type 5 Sets data busy status from the MMC card.
PAGE 1230
24. Multimedia Card Interface (MMCIF) Table 24.5 summarizes the correspondence between the commands described in the MultiMediaCard System Specification Version 3.1 and the settings of the CMDTYR and RSPTYR registers. Table 24.
PAGE 1231
24.
PAGE 1232
24. Multimedia Card Interface (MMCIF) 24.3.13 Transfer Block Number Counter (TBNCR) A value other than 0 must be written to the TBNCR register if a multiple block transfer is selected through the TY5 and TY6 bits in the CMDTYR. Set the transfer block number in the TBNCR. The value of TBNCR is decremented by one as each block transfer is executed and the command sequence ends when the TBNCR value equals 0.
PAGE 1233
24. Multimedia Card Interface (MMCIF) 24.3.14 Response Registers 0 to 16, D (RSPR0 to RSPR16, RSPRD) RSPR0 to RSPR16 are command response registers, which are seventeen 8-bit registers. RSPRD is an 8-bit CRC status register. The number of command response bytes differs according to the command. The number of command response bytes can be specified by RSPTYR in the MMCIF. The command response is shifted-in from bit 0 in RSPR16, and shifted to the number of command response bytes × 8 bits. Table 24.
PAGE 1234
24. Multimedia Card Interface (MMCIF) (1) RSPR0 to RSPR16 Bit: 7 6 5 4 0 R/W 0 R/W 0 R/W 0 R/W 3 2 1 0 0 R/W 0 R/W 0 R/W RSPR Initial value: R/W: 0 R/W Bit Bit Name Initial Value R/W Description 7 to 0 RSPR H'00 R/W These bits are cleared to H'00 by writing an arbitrary value. RSPR0 to RSPR16 comprise a continuous 17-byte shift register.
PAGE 1235
24. Multimedia Card Interface (MMCIF) 24.3.15 Data Timeout Register (DTOUTR) DTOUTR specifies the period to generate a data timeout. The 16-bit counter (DTOUTC) and a prescaler, to which the peripheral bus does not have access, count the peripheral clock to monitor the data timeout. The prescaler always counts the peripheral clock, and outputs a count pulse for every 10,000 peripheral clock cycles.
PAGE 1236
24. Multimedia Card Interface (MMCIF) 24.3.16 Data Register (DR) DR is a register for reading/writing FIFO data. Word/byte access is enabled to addresses of this register. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 — R/W — R/W — R/W — R/W 3 2 1 0 — R/W — R/W DR Initial value: R/W: — R/W — R/W — R/W — R/W — R/W — R/W — R/W — R/W — — R/W R/W Bit Bit Name Initial Value R/W Description 15 to 0 DR ⎯ R/W Register for reading/writing FIFO data. Word/byte access is enabled.
PAGE 1237
24. Multimedia Card Interface (MMCIF) 1 word (2 bytes) H'01 H'23 H'45 H'67 H'89 H'AB 64 words . . . . . . FIFO Figure 24.2 DR Access Example 24.3.17 FIFO Pointer Clear Register (FIFOCLR) The FIFO write/read pointer is cleared by writing an arbitrary value to FIFOCLR.
PAGE 1238
24. Multimedia Card Interface (MMCIF) 24.3.18 DMA Control Register (DMACR) DMACR sets DMA request signal output. DMAEN enables or disables a DMA request signal. The DMA request signal is output based on a value that has been set to SET2 to SET0. Bit: 7 6 DMAEN AUTO Initial value: R/W: 0 R/W 0 R/W 5 4 3 2 1 0 ⎯ ⎯ ⎯ SET2 SET1 SET0 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 7 DMAEN 0 R/W DMA Enable 0: Disables output of DMA request signal.
PAGE 1239
24. Multimedia Card Interface (MMCIF) 24.4 Operation The multimedia card is an external storage media that can be easily connected or disconnected. The MMCIF operates in MMC mode. Insert a card and supply power to it. Then operate the MMCIF by applying the transfer clock after setting an appropriate transfer clock frequency. Do not connect or disconnect the card during command sequence execution or in the data busy state. 24.4.
PAGE 1240
24. Multimedia Card Interface (MMCIF) (1) Operation of Broadcast Commands CMD0, CMD1, CMD2, and CMD4 are broadcast commands. These commands and the CMD3 command comprise a sequence assigning relative addresses to individual cards. In this sequence, the CMD output format is open drain, and the command response is wired-OR. During the issuance of this command sequence, the transfer clock frequency should be set to a sufficiently low value. • All cards are initialized to the idle state by CMD0.
PAGE 1241
24. Multimedia Card Interface (MMCIF) (3) Operation of Commands Not Requiring Command Response Some broadcast commands do not require a command response. Figure 24.3 shows an example of the command sequence for commands that do not require a command response. Figure 24.4 shows the operational flow for commands that do not require a command response. • Make settings to issue the command. • Set the CMDSTART bit in CMDSTRT to 1 to start command transmission.
PAGE 1242
24. Multimedia Card Interface (MMCIF) Start of command sequence Set command data in CMDR0 to CMDR4 Set command type in CMDTYR Set command response type in RSPTYR Set the CMDSTART bit in CMDSTRT to 1 (CMDI) interrupt detected? No Yes End of command sequence Figure 24.
PAGE 1243
24. Multimedia Card Interface (MMCIF) • The command response is received from the card. If the card returns no command response, the command response is detected by the command timeout error (CTERI). • The end of the command sequence is detected by poling the BUSY flag in CSTR or by the command response receive end interrupt (CRPI). • Check whether the state is data busy through the DTBUSY bit in CSTR.
PAGE 1244
24. Multimedia Card Interface (MMCIF) Input/output pins MMCCLK MMCCMD Command output (48 bits) Command response reception (Busy state) MMCDAT CMDSTRT (CMDSTART) Command transmission started Response reception completed INTSTR0 (CMDI) (CRPI) Busy state ends (DBSYI) CSTR (CWRE) Command transmission period (BUSY) Command sequence execution period (DTBUSY_TU) (DTBUSY) Data busy period (REQ) Figure 24.6 Example of Command Sequence for Commands without Data Transfer (with Data Busy State) Rev.1.
PAGE 1245
24. Multimedia Card Interface (MMCIF) Start of command sequence Set command data in CMDR0 to CMDR4 Set command type in CMDTYR Set command response type in RSPTYR Write 1 to CMDSTRT Yes CRCERI interrupt detected? No CRPI interrupt detected? No Yes R1b response? No Yes DTBUSY detected? Yes No DBSYI interrupt detected? No CTERI interrupt detected? No Yes Write 1 to CMDOFF Yes End of command sequence Figure 24.7 Example of Operational Flow for Commands without Data Transfer Rev.1.00 Jan.
PAGE 1246
24. Multimedia Card Interface (MMCIF) (5) Commands with Read Data Flash memory operation commands include a number of commands involving read data. Such commands confirm the card status by the command argument and command response, and receive card information and flash memory data from the MMCDAT pin. In multiple block transfer, two transfer methods can be used; one is open-ended and another one is pre-defined.
PAGE 1247
24. Multimedia Card Interface (MMCIF) • The end of the command sequence is detected by poling the BUSY flag in CSTR, by the data transfer end interrupt (DTI) or pre-defined multiple block transfer end (BTI). • Write the CMDOFF bit to 1 if a CRC error (CRCERI) or a command timeout error (CTERI) occurs in the command response reception. • Clear the FIFO by writing the CMDOFF bit to 1, when CRC error (CRCERI) and data timeout error (DTERI) occurs in the read data reception.
PAGE 1248
24.
PAGE 1249
24.
PAGE 1250
24.
PAGE 1251
24.
PAGE 1252
24. Multimedia Card Interface (MMCIF) Start of command sequence Clear FIFO Set the block size in TBCR Execute CMD16 CMD16 normal end? No Yes Execute CMD18 (Set CMDR then CMDSTRT) Yes CRCERI interrupt detected? No No CRPI interrupt detected? Yes No CTERI interrupt detected? Read response register No Yes Response status normal? Yes 1 2 Figure 24.13 Example of Operational Flow for Commands with Read Data (1) (Open-ended Multiple Block Transfer) Rev.1.00 Jan.
PAGE 1253
24.
PAGE 1254
24. Multimedia Card Interface (MMCIF) Start of command sequence Clear FIFO Set the block size in TBCR Execute CMD16 CMD16 normal end? No Yes Set the number of blocks for transfer (TBNCR) Execute CMD23 CMD23 normal end? No Yes Execute CMD18 (Set CMDR then CMDSTRT) CRCERI interrupt detected? Yes No CRPI interrupt detected? No Yes No CTERI interrupt detected? Read response register No Yes Response status normal? Yes 1 2 Figure 24.
PAGE 1255
24.
PAGE 1256
24.
PAGE 1257
24. Multimedia Card Interface (MMCIF) (6) Commands with Write Data Flash memory operation commands include a number of commands involving write data. Such commands confirm the card status by the command argument and command response, and transmit card information and flash memory data via the MMCDAT pin. For a command that is related to time-consuming processing such as flash memory write, the card indicates the data busy state via the MMCDAT pin.
PAGE 1258
24. Multimedia Card Interface (MMCIF) • The end of the command sequence is detected by poling the BUSY flag in CSTR, data transfer end interrupt (DTI), data response interrupt (DRPI), or pre-defined multiple block transfer end (BTI). • The data busy state is checked through DTBUSY in CSTR. If the card is in data busy state, the end of the data busy state is detected by the data busy end interrupt (DBSYI).
PAGE 1259
24. Multimedia Card Interface (MMCIF) Input/output pins MMCCLK CMD24 (WRITE_SINGLE_BLOCK) MMCCMD Command Command response MMCDAT CMDSTRT (CMDSTART) Command transmission started Status Write data Busy OPCR (DATAEN) INTSTR0 (CMDI) (CRPI) (DTI) (DRPI) (DBSYI) (FEI) CSTR (CWRE) (BUSY) Single block write command execution sequence (FIFO_EMPTY) (DTBUSY) (DTBUSY_TU) (REQ) Figure 24.15 Example of Command Sequence for Commands with Write Data (Block Size ≤ FIFO Size) Rev.1.00 Jan.
PAGE 1260
24.
PAGE 1261
24.
PAGE 1262
24.
PAGE 1263
24.
PAGE 1264
24. Multimedia Card Interface (MMCIF) Start of command sequence Clear FIFO Set the block size in TBCR Execute CMD16 CMD16 normal end? No Yes Execute CMD25 (Set CMDR then CMDSTRT) Yes CRCERI interrupt detected? No CRPI interrupt detected? No Yes No CTERI interrupt detected? Read response register Response status normal? No Yes Yes 1 2 Figure 24.20 (1) Example of Operational Flow for Commands with Write Data (Open-ended Multiple Block Transfer) Rev.1.00 Jan.
PAGE 1265
24.
PAGE 1266
24. Multimedia Card Interface (MMCIF) Start of command sequence Clear FIFO Set the block size in TBCR Execute CMD16 CMD16 normal end? No Yes Set the number of blocks in TBNCR Execute CMD 23 CMD 23 normal end? No Yes Execute CMD25 (Set CMDR then CMDSTRT) CRCERI interrupt detected? Yes No CRPI interrupt detected? No Yes No CTERI interrupt detected? Read response register Response status normal? No Yes Yes 1 2 Figure 24.
PAGE 1267
24.
PAGE 1268
24. Multimedia Card Interface (MMCIF) Start of command sequence Clear FIFO Execute CMD20 (Set CMDR then CMDSTRT) Yes CRCERI interrupt detected? No CRPI interrupt detected? No Yes No CTERI interrupt detected? Read response register Response status normal? No Yes Yes Write data to FIFO Set DATAEN to 1 No FEI interrupt detected? Yes No All data written to FIFO? Yes Set CMDOFF to 1 Set CMDOFF to 1 Execute CMD12 End of command sequence Figure 24.
PAGE 1269
24. Multimedia Card Interface (MMCIF) 24.5 MMCIF Interrupt Sources Table 24.7 lists the MMCIF interrupt sources. The interrupt sources are classified into four groups, and four interrupt vectors are assigned. Each interrupt source can be individually enabled by the enable bits in INTCR0 to INTCR2. Disabled interrupt sources do not set the flag. Table 24.
PAGE 1270
24. Multimedia Card Interface (MMCIF) 24.6 Operations when Using DMA 24.6.1 Operation in Read Sequence In order to transfer data in FIFO with the DMAC, set MMCIF (DMACR) after setting the DMAC*. Transmit the read command after setting DMACR. Figure 24.22 to 24.24 shows the operational flow for a read sequence. • • • • • Clear FIFO and make settings in DMACR. Read command transmission is started. Command response is received from the card. Read data is received from the card.
PAGE 1271
24. Multimedia Card Interface (MMCIF) • An error in a command sequence (during data reception) is detected through the CRC error flag or data timeout flag. When these flags are detected, set the CMDOFF bit in OPCR to 1, issue CMD12 and suspend the command sequence. • The data remains in FIFO after the read sequence end. Set the SET[2:0] bits in DMACR to 100 to read all data in FIFO if necessary. • Confirm the DMA transfer end and clear the DMAEN bit in DMACR to 0.
PAGE 1272
24.
PAGE 1273
24. Multimedia Card Interface (MMCIF) Start of command sequence Clear FIFO Set the block size in TBCR Execute CMD16 CMD16 normal end? No Yes Configure the DMAC Set DMACR (in the MMCIF) Execute CMD 18 (Set CMDR then CMDSTRT) CRCERI interrupt detected? Yes No CRPI interrupt detected? No Yes CTERI interrupt detected? Read response register Response status normal? No Yes No Yes 1 2 Figure 24.23 (1) Example of Read Sequence Flow (Open-ended Multiple Block Transfer) Rev.1.00 Jan.
PAGE 1274
24. Multimedia Card Interface (MMCIF) 1 2 CRCERI interrupt detected? Yes No DTERI interrupt detected? Yes No No DTI interrupt detected? Yes No Next block read? Yes Set RD_CONTI to 1 Set DMACR to H'84 No DMA transfer end? Yes Set CMDOFF to 1 Set CMDOFF to 1 Execute CMD12 Execute CMD12 Clear DMACR to H'00 Clear DMACR to H'00 Set CMDOFF to 1 Clear DMACR to H'00 Clear FIFO End of command sequence Figure 24.23 (2) Example of Read Sequence Flow (Open-ended Multiple Block Transfer) Rev.1.
PAGE 1275
24. Multimedia Card Interface (MMCIF) Start of command sequence Clear FIFO Set the block size in TBCR Execute CMD16 CMD16 normal end? No Yes Set the number of blocks in TBNCR Execute CMD 23 CMD 23 normal end? No Yes Configure the DMAC Set DMACR (in the MMCIF) Execute CMD 18 (Set CMDR then CMDSTRT) CRCERI interrupt detected? Yes No CRPI interrupt detected? No Yes CTERI interrupt detected? Read response register Response status normal? No Yes No Yes 1 2 Figure 24.
PAGE 1276
24.
PAGE 1277
24.
PAGE 1278
24.
PAGE 1279
24. Multimedia Card Interface (MMCIF) 1 2 CRCERI interrupt detected? Yes No DTERI interrupt detected? Yes No No BTI interrupt detected? Yes Set DMACR to H'84 No DMA transfer end? Yes Set CMDOFF to 1 Set CMDOFF to 1 Set CMDOFF to 1 Execute CMD12 Clear DMACR to H'00 Clear DMACR to H'00 Clear DMACR to H'00 Clear FIFO End of command sequence Figure 24.25 (2) Example of Operational Flow for Auto-mode Pre-defined Multiple Block Read Transfer Rev.1.00 Jan.
PAGE 1280
24. Multimedia Card Interface (MMCIF) 24.6.2 Operation in Write Sequence To transfer data to FIFO with the DMAC, set MMCIF (DMACR) after setting the DMAC. Then, start transfer to the card after a FIFO ready interrupt. Figure 24.26 to 24.28 shows the operational flow for a write sequence. • • • • Clear FIFO. Transmit write command. Make settings in DMACR, and set write data to FIFO.
PAGE 1281
24. Multimedia Card Interface (MMCIF) • An error in a command sequence (during data transmission) is detected through the CRC error flag (CRCERI) or data timeout error flag. When these flags are detected, set the CMDOFF bit in OPCR to 1, issue CMD12 (Stop Tran in SPI mode), and suspend the command sequence. • Confirm there is no data busy state. Detect end of the data busy state by the data busy end flag (DBSYI).
PAGE 1282
24. Multimedia Card Interface (MMCIF) Start of command sequence Clear FIFO Set the size of block for transfer in TBCR Execute CMD16 CMD16 normal end? No Yes Execute CMD 24 (Set CMDR then CMDSTRT) CRCERI interrupt detected? Yes No CRPI interrupt detected? No Yes CTERI interrupt detected? Read response register Response status normal? No Yes No Yes Configure the DMAC Set DMACR (in the MMCIF) 1 2 Figure 24.26 (1) Example of Write Sequence Flow (Single Block Transfer) Rev.1.00 Jan.
PAGE 1283
24. Multimedia Card Interface (MMCIF) 1 No 2 FRDYI interrupt detected or DMA transfer end? Yes Set the DATAEN bit to 1 No DMA transfer end? Yes Clear DMACR to H'00 No DTI interrupt detected? Yes CRCERI interrupt detected? Yes No DTERI interrupt detected? Yes No No DRPI interrupt detected? Set CMDOFF to 1 Yes No DTBUSY detected? Yes No DBSYI interrupt detected? Yes End of command sequence Figure 24.26 (2) Example of Write Sequence Flow (Single Block Transfer) Rev.1.00 Jan.
PAGE 1284
24. Multimedia Card Interface (MMCIF) Start of command sequence Clear FIFO Set the block size in TBCR Execute CMD16 CMD16 normal end? No Yes Execute CMD 25 (Set CMDR then CMDSTRT) CRCERI interrupt detected? Yes No CRPI interrupt detected? No Yes CTERI interrupt detected? Read response register Response status normal? No Yes No Yes Configure the DMAC Set DMACR (in the MMCIF) 1 2 Figure 24.27 (1) Example of Write Sequence Flow (Open-ended Multiple Block Transfer) Rev.1.00 Jan.
PAGE 1285
24.
PAGE 1286
24. Multimedia Card Interface (MMCIF) Start of command sequence Clear FIFO Set the block size in TBCR Execute CMD16 CMD16 normal end? No Yes Set the number of blocks in TBNCR Execute CMD 23 CMD 23 normal end? No Yes Execute CMD 25 (Set CMDR then CMDSTRT) CRCERI interrupt detected? Yes No CRPI interrupt detected? No Yes CTERI interrupt detected? Read response register Response status normal? No Yes No Yes Configure the DMAC Set DMACR (in the MMCIF) 1 2 Figure 24.
PAGE 1287
24.
PAGE 1288
24.
PAGE 1289
24. Multimedia Card Interface (MMCIF) Start of command sequence Clear FIFO Set the block size in TBCR Execute CMD16 CMD16 normal end? No Yes Set the number of blocks in TBNCR Execute CMD 23 CMD 23 normal end? No Yes Execute CMD 25 (Set CMDR then CMDSTRT) CRCERI interrupt detected? Yes No CRPI interrupt detected? No Yes CTERI interrupt detected? Read response register Response status normal ended? No Yes No Yes Configure the DMAC Set DMACR (in the MMCIF) 1 2 Figure 24.
PAGE 1290
24. Multimedia Card Interface (MMCIF) 1 2 No DMA transfer end? Yes Clear DMACR to H'00 CRCERI or WRERI interrupt detected? Yes No DTERI interrupt detected? Yes No No BTI interrupt detected? Yes No DTBUSY detected? Yes No DBSYI interrupt detected? Yes Set CMDOFF to 1 Set CMDOFF to 1 Set CMDOFF to 1 Execute CMD12 or Stop Tran Clear DMACR to H'00 Clear FIFO End of command sequence Figure 24.29 (2) Example of Operational Flow for Auto-mode Pre-defined Multiple Block Write Transfer Rev.1.00 Jan.
PAGE 1291
24. Multimedia Card Interface (MMCIF) 24.7 Register Accesses with Little Endian Specification When the little endian is specified, the access size for registers or that for memory where the corresponding data is stored should be fixed. For example, if data read from the MMCIF with the word size is written to memory and then it is read from memory with the byte size, data misalignment occurs. Rev.1.00 Jan.
PAGE 1292
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan.
PAGE 1293
25. Audio Codec Interface (HAC) Section 25 Audio Codec Interface (HAC) The HAC, the audio codec digital controller interface, supports a subset of Audio Codec 97 (AC'97) Version 2.1. The HAC provides serial transmission to/reception from the AC97 codec. Each channel of the HAC can be connected to a single audio codec device. The HAC carries out data extraction from/insertion into audio frames.
PAGE 1294
25. Audio Codec Interface (HAC) Figure 25.1 shows a block diagram of the HAC.
PAGE 1295
25. Audio Codec Interface (HAC) 25.2 Input/Output Pins Table 25.1 describes the HAC pin configuration. Table 25.
PAGE 1296
25. Audio Codec Interface (HAC) 25.3 Register Descriptions The following shows the HAC registers. In this manual, the registers are not discriminated by the channel. Table 25.2 Register Configuration (1) Channel Register Name Abbrev.
PAGE 1297
25. Audio Codec Interface (HAC) Table 25.2 Register Configuration (2) Channel Register Name Abbrev.
PAGE 1298
25. Audio Codec Interface (HAC) Channel Register Name Abbrev.
PAGE 1299
25. Audio Codec Interface (HAC) 25.3.1 Control and Status Register (HACCR) HACCR is a 32-bit read/write register for controlling input/output and monitoring the interface status.
PAGE 1300
25. Audio Codec Interface (HAC) Bit Bit Name Initial Value R/W Description 10 WMRT 0 W HAC Warm Reset Use a warm reset only after power-up, or only to exit from the power-down mode by the power-down command. [Write] 0: Always write 0 to this bit before writing 1 again. (When this bit is changed from 0 to 1, a warm reset is performed.) 1: Performs a warm reset on the HAC-connected codec. [Read] Always read as 0. 9 ⎯ 1 R Reserved This bit is always read as 1. The write value should always be 1.
PAGE 1301
25. Audio Codec Interface (HAC) 25.3.2 Command/Status Address Register (HACCSAR) HACCSAR is a 32-bit read/write register that specifies the address of the codec register to be read /written. When requesting a write to/read from a codec register, write the command register address to HACCSAR and set the ST bit in the HACCR register to 1. The HAC then transmits this register address to the codec via slot 1. After the codec has responded to a read request (HACRSR.
PAGE 1302
25. Audio Codec Interface (HAC) Bit Bit Name Initial Value R/W Description 18 CA6/SA6 0 R/W 17 CA5/SA5 0 R/W Codec Control Register Addresses 6 to 0/Codec Status Register Addresses 6 to 0 16 CA4/SA4 0 R/W [Write] 15 CA3/SA3 0 R/W Specify the address of the codec register to be written. 14 CA2/SA2 0 R/W [Read] 13 CA1/SA1 0 R/W 12 CA0/SA0 0 R/W Indicate the status address received via slot 1, corresponding to the codec register whose data has been returned in HACCSDR.
PAGE 1303
25. Audio Codec Interface (HAC) 25.3.3 Command/Status Data Register (HACCSDR) HACCSDR is a 32-bit read/write data register used for accessing the codec register. Write the command data to HACCSDR and set the ST bit in the HACCR register to 1. The HAC then transmits the data to the codec via slot 2. After the codec has responded to a read request (HACRSR.STDRY = 1), the status data received via slot 2 can be read out from HACCSDR. In both read and write, HACCSAR stores the related codec register address.
PAGE 1304
25. Audio Codec Interface (HAC) Bit Bit Name Initial Value R/W Description 31 to 20 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0. 19 CD15/SD15 0 R/W Command Data 15 to 0/Status Data 15 to 0 18 CD14/SD14 0 R/W 17 CD13/SD13 0 R/W 16 CD12/SD12 0 R/W Write data to these bits and then write the codec register address in HACCSAR. The HAC then transmits the data to the codec.
PAGE 1305
25. Audio Codec Interface (HAC) 25.3.4 PCM Left Channel Register (HACPCML) HACPCML is a 32-bit read/write register used for accessing the left channel of the codec in digital audio recording or stream playback. To transmit the PCM playback left channel data to the codec, write the data to HACPCML. To receive the PCM record left channel data from the codec, read HACPCML. The data is left justified when accommodating a codec with ADC/DAC resolution of 20 bits or less.
PAGE 1306
25.
PAGE 1307
25. Audio Codec Interface (HAC) 25.3.5 PCM Right Channel Register (HACPCMR) HACPCMR is a 32-bit read/write register used for accessing the right channel of the codec in digital audio recording or stream playback. To transmit the PCM playback right channel data to the codec, write the data to HACPCMR. To receive the PCM record right channel data from the codec, read HACPCMR. The data is left justified when accommodating a codec with ADC/DAC resolution of 20 bits or less.
PAGE 1308
25. Audio Codec Interface (HAC) 25.3.6 TX Interrupt Enable Register (HACTIER) HACTIER is a 32-bit read/write register that enables or disables HAC TX interrupts.
PAGE 1309
25. Audio Codec Interface (HAC) 25.3.7 TX Status Register (HACTSR) HACTSR is a 32-bit read/write register that indicates the status of the HAC TX controller. Writing 0 to the bit will initialize it.
PAGE 1310
25. Audio Codec Interface (HAC) Bit Bit Name Initial Value R/W*2 Description 27 to 10 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0. 9 PLTFUN 0 R/W PCML TX Underrun 0: No PCML TX underrun has occurred. 1: PCML TX underrun has occurred because the codec has requested slot 3 data but new data is not written to HACPCML. 8 PRTFUN 0 R/W PCMR TX Underrun 0: No PCMR TX underrun has occurred.
PAGE 1311
25. Audio Codec Interface (HAC) 25.3.8 RX Interrupt Enable Register (HACRIER) HACRIER is a 32-bit read/write register that enables or disables HAC RX interrupts.
PAGE 1312
25. Audio Codec Interface (HAC) Initial Value Bit Bit Name 12 PRRFOVIE 0 R/W Description R/W PCMR RX Overrun Interrupt Enable 0: Disables PCMR RX overrun interrupts. 1: Enables PCMR RX overrun interrupts. 11 to 0 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0. 25.3.9 RX Status Register (HACRSR) HACRSR is a 32-bit read/write register that indicates the status of the HAC RX controller. Writing 0 to the bit will initialize it.
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25. Audio Codec Interface (HAC) Bit Bit Name Initial Value R/W* Description 31 to 23 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0. 22 STARY 0 R/W Status Address Ready 0: HACCSAR (status address) is not ready. 1: HACCSAR (status address) is ready. 21 STDRY 0 R/W Status Data Ready 0: HACCSDR (status data) is not ready. 1: HACCSDR (status data) is ready. 20 PLRFRQ 0 R/W PCML RX Request 0: PCML RX data is not ready.
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25. Audio Codec Interface (HAC) 25.3.10 HAC Control Register (HACACR) HACACR is a 32-bit read/write register used for controlling the HAC interface.
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25. Audio Codec Interface (HAC) Bit Bit Name Initial Value R/W Description 25 ⎯ 0 R Reserved This bit is always read as 0. The write value should always be 0. 24 RXDMAL_EN 0 R/W RX DMA Left Enable 0: Disables 20-bit RX DMA for HACPCML. 1: Enables 20-bit RX DMA for HACPCML. 23 TXDMAL_EN 0 R/W TX DMA Left Enable 0: Disables 20-bit TX DMA for HACPCML. 1: Enables 20-bit TX DMA for HACPCML. 22 RXDMAR_EN 0 R/W RX DMA Right Enable 0: Disables 20-bit RX DMA for HACPCMR.
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25. Audio Codec Interface (HAC) 25.4 AC 97 Frame Slot Structure Figure 25.2 shows the AC97 frame slot structure. This LSI supports slots 0 to 4 only. Slots 5 to 12 (hatched area) are out of scope. Slot No.
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25. Audio Codec Interface (HAC) Table 25.
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25. Audio Codec Interface (HAC) 25.5 Operation 25.5.1 Receiver The HAC receiver receives serial audio data input on the HAC_SDIN pin, synchronous to HAC_BITCLK. From slot 0, the receiver extracts tag bits that indicate which other slots contain valid data. It will update the receive data only when receiving valid slot data indicated by the tag bits. Supporting data only in slots 1 to 4, the receiver ignores tag bits and data related to slots 5 to 12.
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25. Audio Codec Interface (HAC) 25.5.3 DMA The HAC supports DMA transfer for slots 3 and 4 of both the RX and TX frames. Specify the slot data size for DMA transfer, 16 or 20 bits, with the DMARX16 and DMATX16 bits in HACACR. When the data size is 20 bits, transfer of data slots 3 and 4 requires two local bus access cycles. Since each of the receiver and transmitter has its DMA request, the stereo mode generates a DMA request for slots 3 and 4 separately.
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25. Audio Codec Interface (HAC) 25.5.5 Initialization Sequence Figure 25.3 shows an example of the initialization sequence.
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25. Audio Codec Interface (HAC) Prerequisite: ACR.TX12_ATOMIC = 1 Write to codec Write 0 to TSR.CMDAMT Write 0 to TSR.CMDDMT Clear RetryCnt to 0 Set data in CSDR Set Addr. in CSAR Clear LoopCnt to 0 TSR.CMDAMT = 1 & TSR.
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25. Audio Codec Interface (HAC) Read codec Input: RegN (address of the codec register to be read) RegN = Last_Reg? No Yes Read_codec_aux (RegV) RegV = H'7C (Vender ID1) Dummy read Yes Error No Error Last_Reg: Address of the register read last time Read_codec_aux (RegN) In continuous reading of registers in some off-chip codec devices, the data in the register previously read may be read again. In such case, take the steps in this flowchart.
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25. Audio Codec Interface (HAC) Send_read_request Input: RegN (address of the codec register to be read) Write 0 to RSR.STARY Write 0 to RSR.
PAGE 1324
25. Audio Codec Interface (HAC) WaitLoop_CMDAMT Clear LoopCnt 3 to 0 TSR.CMDAMT = 1 No Yes Wait for 1 μs LoopCnt 3 ++ Write 0 to TSR.CMDAMT No E3 < LoopCnt 3 Return Yes Error WaitLoop_RSR Clear LoopCnt 4 to 0 RSR.STARY = 1 & RSR.STDRY = 1 Yes No Wait for 1 μs LoopCnt 4 ++ Write 0 to RSR.STARY Write 0 to RSR.
PAGE 1325
25. Audio Codec Interface (HAC) 25.5.6 Power-Down Mode It is possible to stop or resume the supply of clock to the HAC using the MSTP16 and MSTP17 bits in the standby control register 0 (MSTPCR0), which is a register used in power-down modes. To cancel module standby function and resume the supply of clock to the HAC, write 0 to the MSTP16 and MSTP17 bits in the standby control register 0 (MSTPCR0). It enables all accesses to the HAC.
PAGE 1326
25. Audio Codec Interface (HAC) Rev.1.00 Jan.
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26. Serial Sound Interface (SSI) Module Section 26 Serial Sound Interface (SSI) Module This LSI incorporates two channels of serial sound interface (SSI) modules that send or receive audio data to or from a variety of devices. In addition to the common formats, they support burst and multi-channel mode. 26.1 Features The SSI has the following features.
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26. Serial Sound Interface (SSI) Module Figure 26.1 is a block diagram of the SSI module. Peripheral bus INTC DMAC Interrupt request Control circuit Register Data buffer DMA request SSICR SSISR SSITDR Serial audio bus Barrel shifter SSIRDR SSIn_SDATA MSB SSIn_WS Shift register LSB Bit counter Serial clock control SSIn_SCK Divider SSIn_CLK SSI module Note: n = 0 to 1 Figure 26.1 Block Diagram of SSI Module Rev.1.00 Jan.
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26. Serial Sound Interface (SSI) Module 26.2 Input/Output Pins Table 26.1 lists the pin configurations relating to the SSI module. Table 26.
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26. Serial Sound Interface (SSI) Module 26.3 Register Descriptions The SSI has the following registers. In this manual, the register description is not discriminated by the channel. Table 26.2 Register Configuration (1) Channel Register Name Abbrev.
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26. Serial Sound Interface (SSI) Module 26.3.1 Control Register (SSICR) SSICR is a 32-bit readable/writable register that controls interrupts, selects each polarity status, and sets operating mode.
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26. Serial Sound Interface (SSI) Module Bit Bit Name Initial Value R/W Description 23 22 CHNL1 CHNL0 0 0 R/W R/W Channels These bits indicate the number of channels in each system word. These bits are ignored if CPEN = 1. 00: 1 channel per system word 01: 2 channels per system word 10: 3 channels per system word 11: 4 channels per system word 21 20 19 DWL2 DWL1 DWL0 0 0 0 R/W R/W R/W Data Word Length These bits indicate the number of bits in a data word. These bits are ignored if CPEN = 1.
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26. Serial Sound Interface (SSI) Module Bit Bit Name Initial Value R/W Description 14 SWSD 0 R/W Serial WS Direction 0: Serial word select input, slave mode 1: Serial word select output, master mode Note: In non-compressed mode (SSICR.CPEN=0), the combination of (SCKD, SWSD) = (0, 0) or (1, 1) is available.
PAGE 1334
26. Serial Sound Interface (SSI) Module Bit Bit Name Initial Value R/W Description 12 SWSP 0 R/W Serial WS Polarity The function of this bit depends on whether the SSI module is in non-compressed mode or compressed mode. CPEN = 0 (Non compressed mode): 0: SSI_WS is low for the first system word, high for the second system word 1: SSI_WS is high for the first system word, low for the second system word CPEN = 1 (Compressed mode): 0: SSI_WS is active high flow control.
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26. Serial Sound Interface (SSI) Module Bit Bit Name Initial Value R/W Description 9 PDTA 0 R/W Parallel Data Alignment This bit is ignored if CPEN = 1. If the data word length = 32, 16 or 8 then this bit has no meaning. This bit is applied to SSIRDR in receive mode and to SSITDR in transmit mode.
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26. Serial Sound Interface (SSI) Module Bit Bit Name Initial Value R/W Description 8 DEL 0 R/W Serial Data Delay Set this bit to 1, if CPEN=1 0: 1 clock cycle delay between SSI_WS and SSI_SDATA 1: No delay between SSI_WS and SSI_SDATA 7 BREN 0 R/W Burst Mode Enable 0: Burst mode is disabled. 1: Burst mode is enabled. Burst mode is used only in compressed mode (CPEN = 1) and transmit mode. When burst mode is enabled the SSI_SCK signal is gated.
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26. Serial Sound Interface (SSI) Module Bit Bit Name Initial Value R/W Description 2 CPEN 0 R/W Compressed Mode Enable 0: Compressed mode disabled 1: Compressed mode enabled Note: In compressed mode (CPEN=1), using operation mode except slave transmitter (SWSD=0 and TRMD=1). Do not change this bit when EN = 1.
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26. Serial Sound Interface (SSI) Module 26.3.2 Status Register (SSISR) SSISR is configured by status flags that indicate the operating status of the SSI module and bits that indicate the current channel number and word number.
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26. Serial Sound Interface (SSI) Module Bit Bit Name Initial Value R/W Description 27 UIRQ 0 R/W* Underflow Error Interrupt Status Flag This status flag indicates that the data has been supplied at a lower rate than the required rate. This bit is set to 1 regardless of the setting of UIEN bit. In order to clear it to 0, write 0 in it. If UIRQ = 1 and UIEN = 1, then an interrupt will be generated.
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26. Serial Sound Interface (SSI) Module Bit Bit Name Initial Value R/W Description 26 OIRQ 0 R/W* Overflow Error Interrupt Status Flag This status flag indicates that the data has been supplied at a higher rate than the required rate. This bit is set to 1 regardless of the setting of OIEN bit. In order to clear it to 0, write 0 in it. If OIRQ = 1 and OIEN = 1, then an interrupt will be generated.
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26. Serial Sound Interface (SSI) Module Bit Bit Name Initial Value R/W Description 24 DIRQ 0 R Data Interrupt Status Flag This status flag indicates that the SSI module requires that data be either read out or written in. This bit is set to 1 regardless of the setting of DIEN bit, so that polling will be possible. The interrupt can be masked by clearing DIEN bit to 0, but writing 0 in this bit will not clear the interrupt. If DIRQ = 1 and DIEN = 1, then an interrupt will be generated.
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26. Serial Sound Interface (SSI) Module Bit Bit Name Initial Value R/W Description 1 SWNO 1 R Serial Word Number The number indicates the current word number. When TRMD = 0 (Receive Mode): This bit indicates which system word the current data in SSIRDR is. Regardless whether the data has been read out from SSIRDR, when the data in SSIRDR is updated by transfer from the shift register, this value will change.
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26. Serial Sound Interface (SSI) Module 26.3.3 Transmit Data Register (SSITDR) SSITDR is a 32-bit register that stores data to be transmitted. Data written to SSITDR is transferred to the shift register as it is required for transmission. If the data word length is less than 32 bits then its alignment should be as defined by the PDTA control bit in SSICR. Reading this register will return the data in the buffer. Bit: Initial value: R/W: Bit: Initial value: R/W: 26.3.
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26. Serial Sound Interface (SSI) Module 26.4 Operation 26.4.1 Bus Format The SSI module can operate as a transmitter or a receiver and can be configured into many serial bus formats in either mode. The bus formats can be one of eight major modes as shown in table 26.3.
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26. Serial Sound Interface (SSI) Module 26.4.2 Non-Compressed Modes The non-compressed mode is designed to support all serial audio streams which are split into channels. It can support Philips, Sony and Matsushita modes as well as many more variants on these modes. (1) Slave Receiver This mode allows the SSI module to receive serial data from another device. The clock and word select signals used for the serial data stream are also supplied from an external device.
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26. Serial Sound Interface (SSI) Module 1. Philips Format Figures 26.2 and 26.3 show the supported Philips protocol both with padding and without. Padding occurs when the data word length is smaller than the system word length. SCKP = 0, SWSP = 0, DEL = 0, CHNL = 00 System word length = data word length SSI_SCK SSI_WS SSI_SDATA prev. sample MSB LSB+1 LSB System word 1 = data word 1 MSB LSB+1 LSB next sample System word 2 = data word 2 Figure 26.
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26. Serial Sound Interface (SSI) Module 2. Sony Format SCKP = 0, SWSP = 0, DEL = 1, CHNL = 00, SPDP = 0, SDTA = 0 System word length > data word length SSI_SCK SSI_WS SSI_SDATA MSB LSB MSB Data word 1 Padding next LSB Data word 2 System word 1 Padding System word 2 Figure 26.4 Sony Format (with Serial Data First, Followed by Padding Bits) 3.
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26. Serial Sound Interface (SSI) Module Table 26.
PAGE 1349
26. Serial Sound Interface (SSI) Module In the case of the SSI module configured as a transmitter then each word that is written to SSITDR is transmitted in order on the serial audio bus. In the case of the SSI module configured as a receiver each word received on the serial audio bus is presented for reading in order by SSIRDR. Figures 26.6 to 26.8 show how 4, 6 and 8 channels are transferred on the serial audio bus.
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26. Serial Sound Interface (SSI) Module SCKP = 0, SWSP = 1, DEL = 1, CHNL = 11, SPDP = 0, SDTA = 1 System word length > data word length × 4 SSI_SCK SSI_WS Padding MSB LSB MSB Data word 1 LSB MSB Data word 2 LSB MSB Data word 3 System word 1 LSB Data word 4 MSB Padding SSI_SDATA LSB MSB Data word 5 LSB MSB Data word 6 LSB MSB Data word 7 System word 2 Figure 26.8 Multi-channel Format (8 Channels, Serial Data First, Followed by Padding Bits, with Padding) Rev.1.00 Jan.
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26. Serial Sound Interface (SSI) Module (7) Configuration Fields—Signal Format Fields There are several more configuration bits in non-compressed mode which will now be demonstrated. These bits are NOT mutually exclusive, however some configurations will probably not be useful for any other device. They are demonstrated by referring to the following basic sample format shown in figure 26.9.
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26. Serial Sound Interface (SSI) Module 1. Inverted Clock As basic sample format configuration except SCKP = 1 SSI_SCK System word 1 SSI_WS SSI_SDATA TD28 0 0 TD31 TD30 TD29 TD28 System word 2 0 0 TD31 TD30 TD29 TD28 0 0 TD31 0 0 TD31 1 1 TD31 Figure 26.10 Inverted Clock 2. Inverted Word Select As basic sample format configuration except SWSP = 1 SSI_SCK System word 1 SSI_WS SSI_SDATA TD28 0 0 TD31 TD30 TD29 TD28 System word 2 0 0 TD31 TD30 TD29 TD28 Figure 26.
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26. Serial Sound Interface (SSI) Module 4. Padding Bits First, Followed by Serial Data, with Delay As basic sample format configuration except SDTA = 1 SSI_SCK System word 1 SSI_WS SSI_SDATA TD30 TD29 TD28 0 0 System word 2 TD31 TD30 TD29 TD28 0 0 TD31 TD30 TD29 TD28 0 Figure 26.13 Padding Bits First, Followed by Serial Data, with Delay 5.
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26. Serial Sound Interface (SSI) Module 7. Parallel Right Aligned with Delay As basic sample format configuration except PDTA = 1 SSI_SCK System word 1 SSI_WS SSI_SDATA TD0 0 0 System word 2 TD3 TD2 TD1 TD0 0 0 TD3 TD2 TD1 TD0 0 0 TD3 0 0 0 Figure 26.16 Parallel Right Aligned with Delay 8.
PAGE 1355
26. Serial Sound Interface (SSI) Module The word select pin in this mode does not act as a system word start signal as in non-compressed mode, but instead is used to indicate that the receiver can receive another data burst, or the transmitter can transmit another data burst. Figures 26.18 and 26.19 show the compressed mode data transfer, with burst mode disabled, and enabled, respectively.
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26. Serial Sound Interface (SSI) Module (1) Slave Receiver This mode allows the module to receive a serial bit stream from another device and store it in memory. The shift register clock can be supplied from an external device or from an internal clock. The word select pin is used as an input flow control. Assuming that SWSP = 0 if SSI_WS is high then the module will receive the bit stream in blocks of 32 bits, one data bit per clock.
PAGE 1357
26. Serial Sound Interface (SSI) Module 26.4.4 Operation Modes There are three modes of operation: configuration, enabled and disabled. Figure 26.20 shows the transition diagram between these operation modes. Power-on reset Manual reset Module configration (after reset) EN = 1 (IDST = 0) EN = 0 (IDST = 1) Module disabled (waiting until bus inactive) EN = 0 (IDST = 0) Module enabled (normal tx/rx) Figure 26.
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26. Serial Sound Interface (SSI) Module 26.4.5 Transmit Operation Transmission can be controlled in one of two ways: either DMA or an interrupt driven. DMA driven is preferred to reduce the CPU load. In DMA control mode, an underflow or overflow of data or DMAC transfer end is notified by using an interrupt. The alternative is using the interrupts that the SSI module generates to supply data as required.
PAGE 1359
26.
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26.
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26. Serial Sound Interface (SSI) Module 26.4.6 Receive Operation As with transmission the reception can be controlled in one of two ways: either DMA or an interrupt driven. Figures 26.23 and 26.24 show the flow of operation. When disabling the SSI module, the SSI clock must be supplied continuously until the module enters in the idle state, which is indicated by the IIRQ bit. Note: * SCKD = 0: Clock input through the SSI_SCK pin SCKD = 1: Clock input through the SSI_CLK pin Rev.1.00 Jan.
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26.
PAGE 1363
26.
PAGE 1364
26. Serial Sound Interface (SSI) Module When an underflow or overflow error condition is met (UIRQ = 1 or OIRQ = 1), the CHNO[1:0] and SWNO bits can be used to recover the SSI module to a known status. When an underflow or overflow occurs, the CPU can read the number of channels and the number of system words to determine what point the serial audio stream has currently reached.
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26. Serial Sound Interface (SSI) Module 26.5 Usage Note 26.5.1 Restrictions when an Overflow Occurs during Receive DMA Operation If an overflow occurs during receive DMA operation, the module must be reactivated. The receive buffer of SSI has 32-bit common register to the left channel and right channel.
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26. Serial Sound Interface (SSI) Module SCK One system word Keep active WS input until IDST become 1 (more than five system words) SSI_WS SSI_SDATA SSISR.IDST SSICR.EN Resumption from first or second WS falling edge (SWSP = 0) after EN bit is set to 1 SSI internal state Data transmission Termination and transition to idle Idle or data transmission Figure 26.25 SSI Transfer Termination and Resumption Timing in Slave Mode Rev.1.00 Jan.
PAGE 1367
27. NAND Flash Memory Controller (FLCTL) Section 27 NAND Flash Memory Controller (FLCTL) The NAND flash memory controller (FLCTL) provides interfaces with an external NAND-type flash memory. 27.
PAGE 1368
27. NAND Flash Memory Controller (FLCTL) (5) Data Transfer FIFO • On-chip 224-byte FLDTFIFO for data transfer of flash memory • On-chip 32-byte FLECFIFO for data transfer of a control code • Flag bit for detection of overrun or underrun during access from the CPU or DMA (6) DMA Transfer • By individually specifying the transfer destinations of data and control code of flash memory to the DMA controller, data and control code can be transferred to different areas.
PAGE 1369
27. NAND Flash Memory Controller (FLCTL) Figure 27.1 shows a block diagram of the FLCTL.
PAGE 1370
27. NAND Flash Memory Controller (FLCTL) 27.2 Input/Output Pins Table 27.1 shows the pin configuration of the FLCTL. Table 27.1 Pin Configuration Corresponding Flash Memory Pin Pin Name Function I/O NAND Type Description FCE Chip enable Output CE Enables flash memory connected to this LSI. Multiplexed with SCIF0_CTS/INTD. FD7 to FD0 Data I/O I/O I/O7 to I/O0 I/O pins for command, address, and data.
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27. NAND Flash Memory Controller (FLCTL) Corresponding Flash Memory Pin Pin Name Function I/O NAND Type Description FR/B Ready/busy Input R/B Ready/Busy Indicates ready state at high level. Indicates busy state at low level. Multiplexed with SCIF0_RXD/HSPI_RX. —* — — WP Write Protect/Reset Prevents accidental erasure or programming when power is turned on or off, at low level. FSE Spare area enable Output SE Spare Area Enable Enables access to spare area.
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27. NAND Flash Memory Controller (FLCTL) 27.3 Register Descriptions Table 27.2 shows the register configuration of FLCTL. Table 27.3 shows the register states in each processing mode. Table 27.
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27. NAND Flash Memory Controller (FLCTL) Table 27.
PAGE 1374
27. NAND Flash Memory Controller (FLCTL) 27.3.1 Common Control Register (FLCMNCR) FLCMNCR is a 32-bit readable/writable register that specifies the type (NAND) of flash memory, access mode, and FCE pin output.
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27. NAND Flash Memory Controller (FLCTL) Bit Bit Name Initial Value R/W Description 15 FCKSEL 0 R/W Flash Clock Select 0: Divides the operating clock of the FLCTL (a peripheral clock) by two and uses it as the FCLK 1: Uses the operating clock of the FLCTL (a peripheral clock) as the FCLK 14 to 12 — All 0 R Reserved These bits are always read as 0. The write value should always be 0. 11, 10 ACM[1:0] 00 R/W Access Mode Specification [1:0] Specify access mode.
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27. NAND Flash Memory Controller (FLCTL) 27.3.2 Command Control Register (FLCMDCR) FLCMDCR is a 32-bit readable/writable register that issues a command in command access mode, specifies address issue, and specifies destination of data to be input or output. In sector access mode, FLCMDCR specifies the number of sector transfers.
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27. NAND Flash Memory Controller (FLCTL) Bit Bit Name Initial Value R/W Description 25 CDSRC 0 R/W Data Buffer Specification Specifies the data buffer to be read from or written to in the data stage* in command access mode. 0: Specifies FLDATAR as the data buffer. 1: Specifies FLDTFIFO as the data buffer. 24 DOSR 0 R/W Status Read Check Specifies whether the status read is performed after the second command has been issued in command access mode.
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27. NAND Flash Memory Controller (FLCTL) Bit Bit Name Initial Value R/W Description 16 DOCMD1 0 R/W First Command Stage* Execution Specification Specifies whether the first command stage* is executed in command access mode. 0: Does not execute the first command stage 1: Executes the first command stage 15 to 0 SCTCNT [15:0] H'0000 R/W Sector Transfer Count Specification Specify the number of sectors to be read continuously in sector access mode.
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27. NAND Flash Memory Controller (FLCTL) 27.3.4 Address Register (FLADR) FLADR is a 32-bit readable/writable register that specifies an address to be output in command access mode. In sector access mode, a physical sector number specified in the physical sector address bits is converted into an address to be output.
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27.
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27. NAND Flash Memory Controller (FLCTL) 27.3.5 Address Register 2 (FLADR2) FLADR2 is a 32-bit readable/writable register that is valid when the ADRCNT2 bit in FLCMDCR is 1. This register specifies the value to be output as an address in command mode.
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27. NAND Flash Memory Controller (FLCTL) 27.3.6 Data Counter Register (FLDTCNTR) FLDTCNTR is a 32-bit readable/writable register that specifies the number of bytes to be read or written in command access mode.
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27. NAND Flash Memory Controller (FLCTL) 27.3.7 Data Register (FLDATAR) FLDATAR is a 32-bit readable/writable register. It stores data to be input or output used when the CDSRC bit in FLCMDCR is cleared to 0 in command access mode.
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27. NAND Flash Memory Controller (FLCTL) 27.3.8 Interrupt DMA Control Register (FLINTDMACR) FLINTDMACR is a 32-bit readable/writable register that enables or disables DMA transfer requests or interrupts. A transfer request from the FLCTL to the DMAC is issued after each access mode has started. Bit: 31 30 29 28 27 26 25 Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit: 15 14 13 12 11 10 9 Initial value: R/W: 0 R 0 R 0 R 0 R 0 R Rev.1.00 Jan.
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27. NAND Flash Memory Controller (FLCTL) Bit Bit Name Initial Value R/W Description 31 to 22 — All 0 R Reserved These bits are always read as 0. The write value should always be 0. 21, 20 FIFOTRG [1:0] 00 R/W FIFO Trigger Setting Change the condition for the FIFO transfer request.
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27. NAND Flash Memory Controller (FLCTL) Bit Bit Name Initial Value R/W Description 18 AC0CLR 0 R/W FLDTFIFO Clear Clears the address counter of FLDTFIFO. 0: Retains the address counter value of FLDTFIFO. In flash-memory access, clear this bit to 0. 1: Clears the address counter of FLDTFIFO. After clearing the counter, clear this bit to 0 17 DREQ1EN 0 R/W FLECFIFODMA Request Enable Enables or disables the DMA transfer request issued from FLECFIFO.
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27. NAND Flash Memory Controller (FLCTL) Bit Bit Name Initial Value R/W Description 7 BTOERB 0 R/W Timeout Error This bit is set to 1 if a timeout error occurs (bits RBTIMCNT20 to RBTIMCNT0 in FLBSYCNT are set to 0 after they are decremented). Since this bit is a flag bit, 1 cannot be written to this bit. Only 0 can be written to clear the flag.
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27. NAND Flash Memory Controller (FLCTL) Bit Bit Name Initial Value R/W Description 3 BTOINTE 0 RW Interrupt Enable at Timeout Error Enables or disables an interrupt request to the CPU when a timeout error has occurred. 0: Disables the interrupt request to the CPU by a timeout error 1: Enables the interrupt request to the CPU by a timeout error 2 TEINTE 0 R/W Transfer End Interrupt Enable Enables or disables an interrupt request to the CPU when a transfer has been ended (TREND bit in FLTRCR).
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27. NAND Flash Memory Controller (FLCTL) 27.3.9 Ready Busy Timeout Setting Register (FLBSYTMR) FLBSYTMR is a 32-bit readable/writable register that specifies the timeout time when the FRB pin is busy.
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27. NAND Flash Memory Controller (FLCTL) 27.3.10 Ready Busy Timeout Counter (FLBSYCNT) FLBSYCNT is a 32-bit read-only register. The status of flash memory read by the status read is stored in the bits STAT7 to STAT0. The timeout time set in bits RBTMOUT20 to RBTMOUT0 in FLBSYTMR is copied to bits RBTIMCNT20 to RBTIMCNT0 and counting down is started when the FRB pin enters the busy state.
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27. NAND Flash Memory Controller (FLCTL) 27.3.11 Data FIFO Register (FLDTFIFO) FLDTFIFO is used to read from or write to the data FIFO area. The read and write directions specified by the SELRW bit in FLCMDCR must match the read or write access directions specified in this register.
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27. NAND Flash Memory Controller (FLCTL) 27.3.12 Control Code FIFO Register (FLECFIFO) FLECFIFO is used to read from or write to the control code FIFO area. The read and write directions specified by the SELRW bit in FLCMDCR must match the read and write access directions specified in this register.
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27. NAND Flash Memory Controller (FLCTL) 27.3.13 Transfer Control Register (FLTRCR) Setting the TRSTRT bit to 1 starts access to flash memory. The completion of the access can be checked by the TREND bit. Bit: 7 6 5 4 3 2 1 0 TREND TRSTRT Initial value: R/W: 0 R 0 R 0 R 0 R Bit Bit Name Initial Value R/W Description 7 to 2 — All 0 R Reserved 0 R 0 R 0 R/W 0 R/W These bits are always read as 0. The write value should always be 0.
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27. NAND Flash Memory Controller (FLCTL) 27.4 Operation 27.4.1 Operating Modes Two operating modes are supported. • Command access mode • Sector access mode 27.4.2 Command Access Mode Command access mode is a mode that accesses flash memory by specifying a command to be issued to flash memory, address, data, read or write direction, and number of times for the registers. In this mode, DMA transfer of input or output data can be performed by using FLDTFIFO.
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27. NAND Flash Memory Controller (FLCTL) Figures 27.3 and 27.4 show examples of writing operation for NAND-type flash memory (512 + 16 bytes). CLE ALE WE RE I/O7 to I/O0 H'80 A1 A2 A3 1 2 3 4 5 6 R/B Figure 27.3 Writing Operation Timing for NAND-Type Flash Memory CLE ALE WE RE I/O7 to I/O0 H'10 H'70 Status R/B Figure 27.4 Status Read Operation Timing for NAND-Type Flash Memory Rev.1.00 Jan.
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27. NAND Flash Memory Controller (FLCTL) (2) NAND-Type Flash Memory Access (2048 + 64 Bytes) Figure 27.5 shows an example of reading operation for NAND-type flash memory. In this example, the first command is set to H'00, the second command is set to H'30, address data length is set to 4 bytes, and the number of read bytes is set to 4 bytes in the data counter. Command stage Address stage Command stage Data stage CLE ALE WE R/B Figure 27.5 Reading Operation Timing for NAND-Type Flash Memory Rev.
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27. NAND Flash Memory Controller (FLCTL) Figures 27.6 and 27.7 show examples of writing operation for NAND-type flash memory (2048 + 64 bytes). CLE ALE WE H'10 4 3 2 1 A4 A3 A2 I/O7 to I/O0 A1 H'80 RE R/B Figure 27.6 Writing Operation Timing for NAND-Type Flash Memory CLE ALE WE RE I/O7 to I/O0 H'10 H'70 Status R/B Figure 27.7 Status Read Operation Timing for NAND-Type Flash Memory Rev.1.00 Jan.
PAGE 1398
27. NAND Flash Memory Controller (FLCTL) 27.4.3 Sector Access Mode In sector access mode, flash memory can be read from or written to in sector units by specifying the number of physical sectors to be accessed. Since 512-byte data is stored in FLDTFIFO and 16-byte control code is stored in FLECFIFO, DMA transfer can be performed by setting the DREQ1EN and DREQ0EN bits in FLINTDMACR. Figure 27.
PAGE 1399
27. NAND Flash Memory Controller (FLCTL) (1) Physical Sector Figure 27.9 shows the relationship between the physical sector address and flash memory address of NAND-type flash memory.
PAGE 1400
27. NAND Flash Memory Controller (FLCTL) (2) Continuous Sector Access Continuous physical sectors can be read from or written to by specifying the start physical sector address of NAND-type flash memory and the number of sectors to be transferred. Figure 27.10 shows an example of physical sector specification register and transfer count specification register settings when transferring logical sectors 0 to 40, which are not contiguous because of an unusable sector in NAND-type flash memory.
PAGE 1401
27. NAND Flash Memory Controller (FLCTL) 27.4.4 Status Read The FLCTL can read the status register of a NAND-type flash memory. The data in the status register of a NAND-type flash memory is input through the I/O7 to I/O0 pins and stored in the bits STAT7 to STAT0 in FLBSYCNT. The bits STAT7 to STAT0 in FLBSYCNT can be read by the CPU.
PAGE 1402
27. NAND Flash Memory Controller (FLCTL) (2) Status Read of NAND-Type Flash Memory (2048 + 64 Bytes) The status read of NAND-type flash memory can be performed by inputting the command H'70 to NAND-type flash memory. When the DOSR bit in FLCMDCR is set to 1 and writing is performed in command access mode or sector access mode, the FLCTL automatically inputs H'70 to NANDtype flash memory and status read is performed.
PAGE 1403
27. NAND Flash Memory Controller (FLCTL) 27.5 Example of Register Setting The examples of setting and starting registers in each access mode are shown below.
PAGE 1404
27.
PAGE 1405
27.
PAGE 1406
27. NAND Flash Memory Controller (FLCTL) 27.6 Interrupt Processing The FLCTL has four interrupt sources. Each of the interrupt sources has its corresponding interrupt flag. The interrupt request is generated independently if the interrupt is enabled by the interrupt enable bit. The status error and ready/busy timeout error use the common FLSTE interrupt. Table 27.
PAGE 1407
28. General Purpose I/O Ports (GPIO) Section 28 General Purpose I/O Ports (GPIO) 28.1 Features This LSI has sixteen general-purpose ports (A to H, J to N, and P to R), which provide 111 input/output pins. The general-purpose I/O (GPIO) port pins are multiplexed with the pins of peripheral modules to select whether the pins are used by the GPIO or the peripheral modules. The GPIO has the following features.
PAGE 1408
28. General Purpose I/O Ports (GPIO) Table 28.
PAGE 1409
28.
PAGE 1410
28.
PAGE 1411
28.
PAGE 1412
28. General Purpose I/O Ports (GPIO) 28.2 Register Descriptions The following registers are provided to control the GPIO ports. Table 28.2 Register Configuration (1) Register Name Abbrev.
PAGE 1413
28. General Purpose I/O Ports (GPIO) Register Name Abbrev.
PAGE 1414
28. General Purpose I/O Ports (GPIO) Table 28.2 Register Configuration (2) Register Name Abbrev.
PAGE 1415
28. General Purpose I/O Ports (GPIO) Register Name Abbrev.
PAGE 1416
28. General Purpose I/O Ports (GPIO) 28.2.1 Port A Control Register (PACR) PACR is a 16-bit readable/writable register that selects the pin function and controls the input pull-up MOS.
PAGE 1417
28. General Purpose I/O Ports (GPIO) Bit Bit Name Initial value R/W Description 9 PA4MD1 0 R/W PA4 Mode 8 PA4MD0 0 R/W 00: LBSC/PCIC module (D60/AD28)* When the bus mode is set to DU via the bus-mode pins (MODE11 and MODE12), port input (pull-up MOS: On) is selected.
PAGE 1418
28. General Purpose I/O Ports (GPIO) Bit Bit Name Initial value R/W Description 1 PA0MD1 0 R/W PA0 Mode 0 PA0MD0 0 R/W 00: LBSC/PCIC module (D56/AD24)* When the bus mode is set to DU via the bus-mode pins (MODE11 and MODE12), port input (pull-up MOS: On) is selected. 01: Port output 10: Port input (pull-up MOS: Off) 11: Port input (pull-up MOS: On) Note: * The module that uses the pin can be selected by the bus-mode pins (MODE11 and MODE12).
PAGE 1419
28. General Purpose I/O Ports (GPIO) 28.2.2 Port B Control Register (PBCR) PBCR is a 16-bit readable/writable register that selects the pin function and controls the input pullup MOS.
PAGE 1420
28. General Purpose I/O Ports (GPIO) Bit Bit Name Initial value R/W Description 9 8 PB4MD1 PB4MD0 0 0 R/W R/W PB4 Mode 00: LBSC/PCIC module (D52/AD20)* When the bus mode is set to DU via the bus-mode pins (MODE11 and MODE12), port input (pull-up MOS: On) is selected.
PAGE 1421
28. General Purpose I/O Ports (GPIO) 28.2.3 Port C Control Register (PCCR) PCCR is a 16-bit readable/writable register that selects the pin function and controls the input pullup MOS.
PAGE 1422
28.
PAGE 1423
28. General Purpose I/O Ports (GPIO) 28.2.4 Port D Control Register (PDCR) PDCR is a 16-bit readable/writable register that selects the pin function and controls the input pull-up MOS.
PAGE 1424
28.
PAGE 1425
28. General Purpose I/O Ports (GPIO) 28.2.5 Port E Control Register (PECR) PECR is a 16-bit readable/writable register that selects the pin function and controls the input pullup MOS.
PAGE 1426
28. General Purpose I/O Ports (GPIO) Bit Bit Name Initial value R/W Description 5 PE2MD1 0 R/W PE2 Mode 4 PE2MD0 0 R/W 00: PCIC module (GNT1) When the bus mode is set to the local bus or DU via the bus mode pins (MODE1 and MODE2), port input (pull-up MOS: On) is selected.
PAGE 1427
28. General Purpose I/O Ports (GPIO) 28.2.6 Port F Control Register (PFCR) PFCR is a 16-bit readable/writable register that selects the pin function and controls the input pullup MOS.
PAGE 1428
28.
PAGE 1429
28. General Purpose I/O Ports (GPIO) 28.2.7 Port G Control Register (PGCR) PGCR is a 16-bit readable/writable register that selects the pin function and controls the input pull-up MOS.
PAGE 1430
28.
PAGE 1431
28. General Purpose I/O Ports (GPIO) 28.2.8 Port H Control Register (PHCR) PHCR is a 16-bit readable/writable register that selects the pin function and controls the input pull-up MOS.
PAGE 1432
28.
PAGE 1433
28. General Purpose I/O Ports (GPIO) 28.2.9 Port J Control Register (PJCR) PJCR is a 16-bit readable/writable register that selects the pin function and controls the input pullup MOS.
PAGE 1434
28.
PAGE 1435
28. General Purpose I/O Ports (GPIO) 28.2.10 Port K Control Register (PKCR) PKCR is a 16-bit readable/writable register that selects the pin function and controls the input pull-up MOS.
PAGE 1436
28.
PAGE 1437
28. General Purpose I/O Ports (GPIO) 28.2.11 Port L Control Register (PLCR) PLCR is a 16-bit readable/writable register that selects the pin function and controls the input pullup MOS.
PAGE 1438
28.
PAGE 1439
28. General Purpose I/O Ports (GPIO) 28.2.12 Port M Control Register (PMCR) PMCR is a 16-bit readable/writable register that selects the pin function and controls the input pull-up MOS.
PAGE 1440
28. General Purpose I/O Ports (GPIO) 28.2.13 Port N Control Register (PNCR) PNCR is a 16-bit readable/writable register that selects the pin function and controls the input pull-up MOS.
PAGE 1441
28.
PAGE 1442
28. General Purpose I/O Ports (GPIO) 28.2.14 Port P Control Register (PPCR) PPCR is a 16-bit readable/writable register that selects the pin function and controls the input pullup MOS.
PAGE 1443
28. General Purpose I/O Ports (GPIO) Bit Bit Name Initial value R/W Description 7 PP3MD1 0 R/W PP3 Mode 6 PP3MD0 0 R/W 00: PCIC/DU module (LOCK/ODDF)* When the bus mode is set to the local bus by the bus mode pins (MODE11 and MODE12), port input (pull-up MOS: On) is selected.
PAGE 1444
28. General Purpose I/O Ports (GPIO) 28.2.15 Port Q Control Register (PQCR) PQCR is a 16-bit readable/writable register that selects the pin function and controls the input pull-up MOS.
PAGE 1445
28. General Purpose I/O Ports (GPIO) Bit Bit Name Initial value R/W Description 5 PQ2MD1 0 R/W PQ2 Mode 4 PQ2MD0 0 R/W 00: PCIC module (REQ0/REQOUT) When the bus mode is set to the local bus or DU via the bus mode pins (MODE1 and MODE2), port input (pull-up MOS: On) is selected.
PAGE 1446
28. General Purpose I/O Ports (GPIO) 28.2.16 Port R Control Register (PRCR) PRCR is a 16-bit readable/writable register that selects the pin function and controls the input pullup MOS.
PAGE 1447
28. General Purpose I/O Ports (GPIO) Bit Bit Name Initial value R/W Description 3 PR1MD1 0 R/W PR1 Mode 2 PR1MD0 0 R/W 00: LBSC/PCIC module (WE5/CBE1)* When the bus mode is set to DU via the bus-mode pins (MODE11 and MODE12), port input (pull-up MOS: On) is selected.
PAGE 1448
28. General Purpose I/O Ports (GPIO) 28.2.17 Port A Data Register (PADR) PADR is an 8-bit readable/writable register that stores port A data. Bit: 7 6 5 4 3 2 1 0 PA7DT PA6DT PA5DT PA4DT PA3DT PA2DT PA1DT PA0DT Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 7 PA7DT 0* R/W 6 PA6DT 0* R/W 5 PA5DT 0* R/W These bits store output data of a pin which is used as a general-purpose output port.
PAGE 1449
28. General Purpose I/O Ports (GPIO) 28.2.18 Port B Data Register (PBDR) PBDR is an 8-bit readable/writable register that stores port B data. Bit: 7 6 5 4 3 2 1 0 PB7DT PB6DT PB5DT PB4DT PB3DT PB2DT PB1DT PB0DT Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 7 PB7DT 0* R/W 6 PB6DT 0* R/W 5 PB5DT 0* R/W These bits store output data of a pin which is used as a general-purpose output port.
PAGE 1450
28. General Purpose I/O Ports (GPIO) 28.2.19 Port C Data Register (PCDR) PCDR is an 8-bit readable/writable register that stores port C data. Bit: 7 6 5 4 3 2 1 0 PC7DT PC6DT PC5DT PC4DT PC3DT PC2DT PC1DT PC0DT Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit Bit Name Initial value R/W Description 7 PC7DT 0 R/W 6 PC6DT 0 R/W 5 PC5DT 0 R/W These bits store output data of a pin which is used as a general-purpose output port.
PAGE 1451
28. General Purpose I/O Ports (GPIO) 28.2.20 Port D Data Register (PDDR) PDDR is an 8-bit readable/writable register that stores port D data. Bit: 7 6 5 4 3 2 1 0 PD7DT PD6DT PD5DT PD4DT PD3DT PD2DT PD1DT PD0DT Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit Bit Name Initial value R/W Description 7 PD7DT 0 R/W 6 PD6DT 0 R/W 5 PD5DT 0 R/W These bits store output data of a pin which is used as a general-purpose output port.
PAGE 1452
28. General Purpose I/O Ports (GPIO) 28.2.21 Port E Data Register (PEDR) PEDR is an 8-bit readable/writable register that stores port E data. Bit: Initial value: R/W: 7 6 — — 0 R/W 0 R/W 5 4 3 2 1 0 PE5DT PE4DT PE3DT PE2DT PE1DT PE0DT 0 R/W 0 R/W Bit Bit Name Initial value R/W Description 7 and 6 ⎯ All 0 R/W Reserved x R/W 0 R/W 0 R/W x R/W These bits are always read as 0, and the write value should always be 0.
PAGE 1453
28. General Purpose I/O Ports (GPIO) 28.2.22 Port F Data Register (PFDR) PFDR is an 8-bit readable/writable register that stores port F data. Bit: 7 6 5 4 3 2 1 0 PF7DT PF6DT PF5DT PF4DT PF3DT PF2DT PF1DT PF0DT Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit Bit Name Initial value R/W Description 7 PF7DT 0 R/W 6 PF6DT 0 R/W 5 PF5DT 0 R/W These bits store output data of a pin which is used as a general-purpose output port.
PAGE 1454
28. General Purpose I/O Ports (GPIO) 28.2.23 Port G Data Register (PGDR) PGDR is an 8-bit readable/writable register that stores port G data. Bit: 7 6 5 4 3 2 1 0 PG7DT PG6DT PG5DT PG4DT PG3DT PG2DT PG1DT PG0DT Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit Bit Name Initial value R/W Description 7 PG7DT 0 R/W 6 PG6DT 0 R/W 5 PG5DT 0 R/W These bits store output data of a pin which is used as a general-purpose output port.
PAGE 1455
28. General Purpose I/O Ports (GPIO) 28.2.24 Port H Data Register (PHDR) PHDR is an 8-bit readable/writable register that stores port H data.
PAGE 1456
28. General Purpose I/O Ports (GPIO) 28.2.25 Port J Data Register (PJDR) PJDR is an 8-bit readable/writable register that stores port J data. Bit: 7 6 5 4 3 2 1 0 PJ7DT PJ6DT PJ5DT PJ4DT PJ3DT PJ2DT PJ1DT PJ0DT Initial value: R/W: x R/W Bit Bit Name Initial value 7 PJ7DT Pin input R/W 6 PJ6DT Pin input R/W 5 PJ5DT Pin input R/W 4 PJ4DT Pin input R/W 3 PJ3DT Pin input R/W 2 PJ2DT Pin input R/W 1 PJ1DT Pin input R/W 0 PJ0DT Pin input R/W R/W Rev.1.00 Jan.
PAGE 1457
28. General Purpose I/O Ports (GPIO) 28.2.26 Port K Data Register (PKDR) PKDR is an 8-bit readable/writable register that stores port K data. Bit: 7 6 5 4 3 2 1 0 PK7DT PK6DT PK5DT PK4DT PK3DT PK2DT PK1DT PK0DT Initial value: R/W: 0 R/W 0 R/W x x x x R/W R/W R/W R/W x R/W x R/W Bit Bit Name Initial value R/W Description 7 PK7DT 0 R/W 6 PK6DT 0 R/W 5 PK5DT Pin input R/W These bits store output data of a pin which is used as a general-purpose output port.
PAGE 1458
28. General Purpose I/O Ports (GPIO) 28.2.27 Port L Data Register (PLDR) PLDR is an 8-bit readable/writable register that stores port L data. Bit: 7 6 5 4 3 2 1 0 PL7DT PL6DT PL5DT PL4DT PL3DT PL2DT PL1DT PL0DT Initial value: R/W: x R/W Bit Bit Name Initial value 7 PL7DT Pin input R/W 6 PL6DT Pin input R/W 5 PL5DT Pin input R/W 4 PL4DT Pin input R/W 3 PL3DT Pin input R/W 2 PL2DT Pin input R/W 1 PL1DT Pin input R/W 0 PL0DT Pin input R/W R/W Rev.1.00 Jan.
PAGE 1459
28. General Purpose I/O Ports (GPIO) 28.2.28 Port M Data Register (PMDR) PMDR is an 8-bit readable/writable register that stores port M data. Bit: Initial value: R/W: 7 6 5 4 3 2 — — — — — — 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit Bit Name Initial value R/W Description 7 to 2 ⎯ All 0 R/W Reserved 1 0 PM1DT PM0DT 0 R/W 0 R/W These bits are always read as 0, and the write value should always be 0.
PAGE 1460
28. General Purpose I/O Ports (GPIO) 28.2.29 Port N Data Register (PNDR) PNDR is an 8-bit readable/writable register that stores port N data. Bit: 7 6 5 4 3 2 1 0 PN7DT PN6DT PN5DT PN4DT PN3DT PN2DT PN1DT PN0DT Initial value: R/W: x R/W Bit Bit Name Initial value 7 PN7DT Pin input R/W 6 PN6DT Pin input R/W 5 PN5DT 0 R/W 4 PN4DT 0 R/W 3 PN3DT 0 R/W 2 PN2DT 0 R/W 1 PN1DT 0 R/W 0 PN0DT 0 R/W R/W Rev.1.00 Jan.
PAGE 1461
28. General Purpose I/O Ports (GPIO) 28.2.30 Port P Data Register (PPDR) PPDR is an 8-bit readable/writable register that stores port P data. Bit: Initial value: R/W: 7 6 — — 0 R/W 0 R/W 5 4 3 2 1 0 PP5DT PP4DT PP3DT PP2DT PP1DT PP0DT 0 R/W 0 R/W Bit Bit Name Initial value R/W Description 7 and 6 ⎯ All 0 R/W Reserved 0 R/W 0 R/W 0 R/W 0 R/W These bits are always read as 0, and the write value should always be 0.
PAGE 1462
28. General Purpose I/O Ports (GPIO) 28.2.31 Port Q Data Register (PQDR) PQDR is an 8-bit readable/writable register that stores port Q data. Bit: Initial value: R/W: 7 6 5 — — — 0 R/W 0 R/W 0 R/W 4 3 2 1 0 PQ4DT PQ3DT PQ2DT PQ1DT PQ0DT 0 R/W Bit Bit Name Initial value R/W Description 7 to 5 ⎯ All 0 R/W Reserved 0 R/W 0 R/W 0 R/W 0 R/W These bits are always read as 0, and the write value should always be 0.
PAGE 1463
28. General Purpose I/O Ports (GPIO) 28.2.32 Port R Data Register (PRDR) PRDR is an 8-bit readable/writable register that stores port R data. Bit: Initial value: R/W: 7 6 5 4 — — — — 0 R/W 0 R/W 0 R/W 0 R/W 3 2 1 0 PR3DT PR2DT PR1DT PR0DT Bit Bit Name Initial value R/W Description 7 to 4 ⎯ All 0 R/W Reserved 0 R/W 0 R/W 0 R/W 0 R/W These bits are always read as 0, and the write value should always be 0.
PAGE 1464
28. General Purpose I/O Ports (GPIO) 28.2.33 Port E Pull-Up Control Register (PEPUPR) PEPUPR is an 8-bit readable/writable register that performs the pull-up control for each of the port E3 and E0 (PE3 and PE0) pins when the pins are used by peripheral modules. When the port E pins are used by the GPIO, the setting for this register is ignored.
PAGE 1465
28. General Purpose I/O Ports (GPIO) 28.2.34 Port H Pull-Up Control Register (PHPUPR) PHPUPR is an 8-bit readable/writable register that performs the pull-up control for each of the port H7 to H0 (PH7 to PH0) pins when the port H pins are used by peripheral modules. When the port H pins are used by the GPIO, the setting for this register is ignored.
PAGE 1466
28. General Purpose I/O Ports (GPIO) 28.2.35 Port J Pull-Up Control Register (PJPUPR) PJPUPR is an 8-bit readable/writable register that performs the pull-up control for each of the port J7 to J0 (PJ7 to PJ0) pins when the port J pins are used by peripheral modules. When the port J pins are used by the GPIO, the setting for this register is ignored.
PAGE 1467
28. General Purpose I/O Ports (GPIO) 28.2.36 Port K Pull-Up Control Register (PKPUPR) PKPUPR is an 8-bit readable/writable register that performs the pull-up control for each of the port K7 to K0 (PK7 to PK0) pins when the port K pins are used by peripheral modules. When the port K pins are used by the GPIO, the setting for this register is ignored.
PAGE 1468
28. General Purpose I/O Ports (GPIO) 28.2.37 Port L Pull-Up Control Register (PLPUPR) PLPUPR is an 8-bit readable/writable register that performs the pull-up control for each of the port L7 to L0 (PL7 to PL0) pins when the port L pins are used by peripheral modules. When the port L pins are used by the GPIO, the setting for this register is ignored.
PAGE 1469
28. General Purpose I/O Ports (GPIO) 28.2.38 Port M Pull-Up Control Register (PMPUPR) PMPUPR is an 8-bit readable/writable register that performs the pull-up control for each of the port M1 and M0 (PM1 to PM0) pins when the port M pins are used by peripheral modules. When the port M pins are used by the GPIO, the setting for this register is ignored.
PAGE 1470
28. General Purpose I/O Ports (GPIO) 28.2.39 Port N Pull-Up Control Register (PNPUPR) PNPUPR is an 8-bit readable/writable register that performs the pull-up control for each of the port N7 to N0 (PN7 to PN0) pins when the port N pins are used by peripheral modules. When the port N pins are used by the GPIO, the setting for this register is ignored.
PAGE 1471
28. General Purpose I/O Ports (GPIO) 28.2.40 Input-Pin Pull-Up Control Register 1 (PPUPR1) PPUPR1 is a 16-bit readable/writable register that performs the pull-up control for the pin corresponding to each bit of the register field.
PAGE 1472
28. General Purpose I/O Ports (GPIO) Bit Bit Name Initial value R/W Description 15 to 8 — All 1 R/W Reserved These bits are always read as 1, and the write value should always be 1.
PAGE 1473
28. General Purpose I/O Ports (GPIO) 28.2.42 Peripheral Module Select Register 1 (P1MSELR) P1MSELR is a 16-bit readable/writable register. This register can be used to select the module that uses multiplexed pins. For details of pin multiplexing, see table 28.1. This register is valid only when peripheral modules are selected by PACR to PHCR, PJCR to PNCR, PPCR to PRCR of the GPIO.
PAGE 1474
28. General Purpose I/O Ports (GPIO) Bit Bit Name Initial value R/W Description 12 PMSEL12 0 R/W 11 PMSEL11 0 R/W Out of the modules DMAC, SCIF[2], MMCIF, and SIOF, selects the one uses the pins DACK3/SCIF2_SCK/MMCDAT/SIOF_SCK and DACK2/SCIF2_TXD/MMCCMD/SIOF_TXD. 00: DMAC 01: SIOF* 10: SCIF[2] 11: MMCIF 10 P1MSEL10 0 R/W Out of the modules DMAC and LBSC, selects the one which uses the pins MODE12/DRAK3/CE2B and DRAK2/CE2A.
PAGE 1475
28. General Purpose I/O Ports (GPIO) Bit Bit Name Initial value R/W Description 6 P1MSEL6 0 R/W 5 P1MSEL5 0 R/W Out of the modules SCIF[2] and SIOF, selects the one using the pin SCIF2_RXD/SIOF_RXD.
PAGE 1476
28. General Purpose I/O Ports (GPIO) Bit Bit Name Initial value R/W Description 0 P1MSEL0 0 R/W Out of the modules SCIF[3] and SCIF[4], and FLCTL, selects the one which uses the pins MODE4/SCIF3_TXD/FCLE, MODE7/SCIF3_RXD/FALE, MODE8/SCIF3_SCK/FD0, MODE9/SCIF4_TXD/FD1, MODE10/SCIF4_RXD/FD2, and MODE11/SCIF4_SCK/FD3. 0: SCIF[3] and SCIF[4] 1: FLCTL At power-on reset by the PRESET pin, MODE4 and MODE7 to MODE11 are selected.
PAGE 1477
28. General Purpose I/O Ports (GPIO) 28.2.43 Peripheral Module Select Register 2 (P2MSELR) P2MSELR is a 16-bit readable/writable register. This register can be used to select the module that uses multiplexed pins. For details of pin multiplexing, see table 28.1. This register is valid only when peripheral modules are selected by PACR to PHCR, PJCR to PNCR, PPCR to PRCR of the GPIO.
PAGE 1478
28. General Purpose I/O Ports (GPIO) Bit Bit Name Initial value R/W Description 15 to 3 — All 0 R/W Reserved These bits are always read as 0, and the write value should always be 0. 2 P2MSEL2 0 R/W Out of the modules RESET and INTC, selects the one which uses the pin MRESETOUT/IRQOUT. 0: Selects RESET 1: Selects INTC 1 P2MSEL1 0 R/W Selects the pin group used by the SIOF. 0: Uses the SIOF pin selected by P1MSEL4 and 3.
PAGE 1479
28. General Purpose I/O Ports (GPIO) 28.3 Usage Example Setting procedure examples are described below. 28.3.1 Port Output Function To output the data of port data registers (PADR to PRDR) from the GPIO output port, write B'01 to the corresponding two bits in port control registers (PACR to PRCR).
PAGE 1480
28. General Purpose I/O Ports (GPIO) 28.3.2 Port Input function To input the data via the GPIO port, write B'10 or B'11 to the corresponding two bits in port control registers (PACR to PRCR). B’10 should be written when the pull-up MOS is off, and B'11 when the pull-up MOS is on. The input data to each port can be read out from the corresponding bit in port data registers (PADR to PRCR).
PAGE 1481
28. General Purpose I/O Ports (GPIO) 28.3.3 Peripheral Module Function The procedures for setting the peripheral module function are described below. 1. Select the peripheral module by using the peripheral module select register 1 (P1MSELR) and peripheral module select register 2 (P2MSELR). 2. When an input or input/output pin is used, it is necessary to set the pull-up MOS for each pin by using the port pull-up control registers (PEPUPR, PHPUPR, PJPUPR, PKPUPR. PLPUPR, PMPUPR, and PNPUPR).
PAGE 1482
28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan.
PAGE 1483
29. User Break Controller (UBC) Section 29 User Break Controller (UBC) The user break controller (UBC) provides versatile functions to facilitate program debugging. These functions help to ease creation of a self-monitor/debugger, which allows easy program debugging using this LSI alone, without using the in-circuit emulator.
PAGE 1484
29. User Break Controller (UBC) Figure 29.1 shows the UBC block diagram. ASID Access control SDB SAB Internal bus Access comparator CBR0 ASID comparator Address comparator CAR0 CAMR0 Channel 0 operation control CRR0 Access comparator CBR1 ASID comparator Address comparator Data comparator Channel 1 operation control CAR1 CAMR1 CDR1 CDMR1 CETR1 CRR1 CCMFR Control CBCR User break is requested.
PAGE 1485
29. User Break Controller (UBC) 29.2 Register Descriptions The UBC has the following registers. Table 29.
PAGE 1486
29. User Break Controller (UBC) Table 29.
PAGE 1487
29. User Break Controller (UBC) 29.2.1 Match Condition Setting Registers 0 and 1 (CBR0 and CBR1) CBR0 and CBR1 are readable/writable 32-bit registers which specify the break conditions for channels 0 and 1, respectively.
PAGE 1488
29. User Break Controller (UBC) Bit Bit Name Initial Value R/W Description 29 to 24 MFI 100000 R/W Match Flag Specify Specifies the match flag to be included in the match conditions. 000000: MF0 bit of the CCMFR register 000001: MF1 bit of the CCMFR register Others: Reserved (setting prohibited) Note: The initial value is the reserved value, but when 1 is written into CBR0[0], MFI must be set to 000000 or 000001.
PAGE 1489
29. User Break Controller (UBC) Bit Bit Name Initial Value R/W Description 7, 6 CD All 0 R/W Bus Select Specifies the bus to be included in the match conditions. This bit is valid only when the operand access cycle is specified as a match condition. 00: Operand bus for operand access Others: Reserved (setting prohibited) 5, 4 ID All 0 R/W Instruction Fetch/Operand Access Select Specifies the instruction fetch cycle or operand access cycle as the match condition.
PAGE 1490
29.
PAGE 1491
29. User Break Controller (UBC) Bit Bit Name Initial Value R/W Description 23 to 16 AIV All 0 R/W ASID Specify Specifies the ASID value to be included in the match conditions. 15 DBE 0 R/W Data Value Enable*3 Specifies whether or not to include the data value in the match condition. This bit is valid only when the operand access cycle is specified as a match condition. 0: The data value is not included in the match conditions; thus, not checked.
PAGE 1492
29. User Break Controller (UBC) Bit Bit Name Initial Value R/W 7, 6 CD All 0 R/W Description Bus Select Specifies the bus to be included in the match conditions. This bit is valid only when the operand access cycle is specified as a match condition. 00: Operand bus for operand access Others: Reserved (setting prohibited) 5, 4 ID All 0 R/W Instruction Fetch/Operand Access Select Specifies the instruction fetch cycle or operand access cycle as the match condition.
PAGE 1493
29. User Break Controller (UBC) 29.2.2 Match Operation Setting Registers 0 and 1 (CRR0 and CRR1) CRR0 and CRR1 are readable/writable 32-bit registers which specify the operation to be executed when channels 0 and 1 satisfy the match condition, respectively. The following operations can be set in the CRR0 and CRR1 registers: (1) breaking at a desired timing for the instruction fetch cycle and (2) requesting a break.
PAGE 1494
29.
PAGE 1495
29. User Break Controller (UBC) 29.2.3 Match Address Setting Registers 0 and 1 (CAR0 and CAR1) CAR0 and CAR1 are readable/writable 32-bit registers specifying the virtual address to be included in the break conditions for channels 0 and 1, respectively.
PAGE 1496
29. User Break Controller (UBC) 29.2.4 Match Address Mask Setting Registers 0 and 1 (CAMR0 and CAMR1) CMAR0 and CMAR1 are readable/writable 32-bit registers which specify the bits to be masked among the address bits specified by using the match address setting register of the corresponding channel. (Set the bits to be masked to 1.
PAGE 1497
29.
PAGE 1498
29. User Break Controller (UBC) 29.2.5 Match Data Setting Register 1 (CDR1) CDR1 is a readable/writable 32-bit register which specifies the data value to be included in the break conditions for channel 1.
PAGE 1499
29. User Break Controller (UBC) 29.2.6 Match Data Mask Setting Register 1 (CDMR1) CDMR1 is a readable/writable 32-bit register which specifies the bits to be masked among the data value bits specified using the match data setting register. (Set the bits to be masked to 1.
PAGE 1500
29. User Break Controller (UBC) 29.2.7 Execution Count Break Register 1 (CETR1) CETR1 is a readable/writable 32-bit register which specifies the number of the channel hits before a break occurs. A maximum value of 212 – 1 can be specified. When the execution count value is included in the match conditions by using the match condition setting register, the value of this register is decremented by one every time the channel is hit.
PAGE 1501
29. User Break Controller (UBC) 29.2.8 Channel Match Flag Register (CCMFR) CCMFR is a readable/writable 32-bit register which indicates whether or not the match conditions have been satisfied for each channel. When a channel match condition has been satisfied, the corresponding flag bit is set to 1. To clear the flags, write the data containing value 0 for the bits to be cleared and value 1 for the other bits to this register.
PAGE 1502
29. User Break Controller (UBC) 29.2.9 Break Control Register (CBCR) CBCR is a readable/writable 32-bit register which specifies whether or not to use the user break debugging support function. For details on the user break debugging support function, refer to section 29.4, User Break Debugging Support Function.
PAGE 1503
29. User Break Controller (UBC) 29.3 Operation Description 29.3.1 Definition of Words Related to Accesses "Instruction fetch" refers to an access in which an instruction is fetched. For example, fetching the instruction located at the branch destination after executing a branch instruction is an instruction access. "Operand access" refers to any memory access accompanying execution of an instruction. For example, accessing an address (PC + disp × 2 + 4) in the instruction MOV.
PAGE 1504
29. User Break Controller (UBC) 29.3.2 User Break Operation Sequence The following describes the sequence from when the break condition is set until the user break exception handling is initiated. 1. Specify the operand size, bus, instruction fetch/operand access, and read/write as the match conditions using the match condition setting register (CBR0 or CBR1).
PAGE 1505
29. User Break Controller (UBC) 6. While the BL bit in the SR register is 1, no break requests are accepted. However, whether or not the condition has been satisfied is determined. When the condition is determined to be satisfied, the corresponding condition match flag is set. 7. If the sequential break conditions are set, the condition match flag is set every time the match conditions are satisfied for each channel.
PAGE 1506
29. User Break Controller (UBC) 29.3.4 Operand Access Cycle Break 1. Table 29.4 shows the relation between the operand sizes specified using the match condition setting register (CBR0 or CBR1) and the address bits to be compared for the operand access cycle break. Table 29.
PAGE 1507
29. User Break Controller (UBC) 4. If the operand bus is selected, a break occurs after executing the instruction which has satisfied the conditions and immediately before executing the next instruction. However, if the data value is included in the match conditions, a break may occur after executing several instructions after the instruction which has satisfied the conditions; therefore, it is impossible to identify the instruction causing the break.
PAGE 1508
29. User Break Controller (UBC) • When the match condition is satisfied at the instruction fetch cycle for the first channel in the sequence whereas the match condition is satisfied at the operand access cycle for the second channel in the sequence: Instruction B is 0 or one instruction after instruction A Sequential operation is not guaranteed. Instruction B is two or more instructions after instruction A Sequential operation is guaranteed.
PAGE 1509
29. User Break Controller (UBC) 29.3.6 Program Counter Value to be Saved When a break has occurred, the address of the instruction to be executed when the program restarts is saved in the SPC then the exception handling state is initiated. A unique instruction causing a break can be identified unless the data value is included in the match conditions. 1.
PAGE 1510
29. User Break Controller (UBC) 29.4 User Break Debugging Support Function By using the user break debugging support function, the branch destination address can be modified when the CPU accepts the user break request. Specifically, setting the UBDE bit of break control register CBCR to 1 allows branching to the address indicated by DBR instead of branching to the address indicated by the [VBR + offset]. Figure 29.2 shows the flowchart of the user break debugging support function.
PAGE 1511
29. User Break Controller (UBC) 29.
PAGE 1512
29. User Break Controller (UBC) With the above settings, the user break occurs after executing the instruction at address H'00037226 where ASID is H'80 before executing the instruction at address H'0003722E where ASID is H'70.
PAGE 1513
29. User Break Controller (UBC) With the above settings, the user break occurs after executing the instruction at address H'00037226 where ASID is H'80 and before executing the instruction at address H'0003722E where ASID is H'70.
PAGE 1514
29. User Break Controller (UBC) ⎯ Channel 1 Address: H'00008010 / Address mask: H'00000006 / ASID: H'70 Data: H'00000000 / Data mask: H'00000000 / Execution count: H'00000000 Bus cycle: Instruction fetch (before executing the instruction) Data values and execution count are not included in the conditions.
PAGE 1515
29. User Break Controller (UBC) 29.6 Usage Notes 1. A desired break may not occur between the time when the instruction for rewriting the UBC register is executed and the time when the written value is actually reflected on the register. After the UBC register is updated, execute one of the following three methods. A. Read the updated UBC register, and execute a branch using the RTE instruction. (It is not necessary that a branch using the RTE instruction is next to a reading UBC register.) B.
PAGE 1516
29. User Break Controller (UBC) ⎯ If the post-instruction-execution break and data access break have occurred simultaneously with the re-execution type exception (including the pre-instruction-execution break) having a higher priority, only the re-execution type exception is accepted, and no condition match flags are set. When the exception handling has finished thus clearing the exception source, and when the same instruction has been executed again, the break occurs setting the corresponding flag.
PAGE 1517
30. User Debugging Interface (H-UDI) Section 30 User Debugging Interface (H-UDI) The H-UDI is a serial input/output interface which supports to a subset of JTAG (IEEE 1149.1). The H-UDI is used to connect emulators. 30.1 Features The H-UDI is a serial input/output interface which supports to a subset of JTAG (IEEE 1149.1: IEEE Standard Test Access Port and Boundary-Scan Architecture). The H-UDI is used to connect emulators. Do not use the JTAG functions of this interface when using an emulator.
PAGE 1518
30. User Debugging Interface (H-UDI) Break controller ASEBRK/BRKACK Interrupt/reset Boundaryscan TAP controller SDBSR TCK TMS Pin multiplexer SDBPR TAP controller Decoder TRST SDIR SDINT TDO AUDSYNC AUDCK AUDATA3 AUDATA2 AUDATA1 AUDATA0 Trace controller Figure 30.1 Block Diagram of H-UDI Rev.1.00 Jan.
PAGE 1519
30. User Debugging Interface (H-UDI) 30.2 Input/Output Pins Table 30.1 shows the pin configuration of the H-UDI. Table 30.1 Pin Configuration of H-UDI When Not in Use Pin Name Function I/O Description TCK Clock Input The functions are the same as the serial clock input pin of JTAG. In synchronization with this signal, data is sent from the TDI pin to the HUDI circuit or data is read from the TDO pin.
PAGE 1520
30. User Debugging Interface (H-UDI) Notes: 1. This pin is pulled up in the chip. In designing the board that can connect an emulator, or using interrupts or resets through the H-UDI, there is no problem with putting the pull-up resistor outside this LSI. 2.
PAGE 1521
30. User Debugging Interface (H-UDI) 30.3 Register Description The H-UDI has the following registers. Table 30.2 Register Configuration (1) CPU Side Register Name Abbreviation R/W Area P4 Address Area 7 Address Size Sync Clock Instruction register SDIR R H'FC11 0000 H'1C11 0000 16 Pck Interrupt source register SDINT R/W H'FC11 0018 H'1C11 0018 16 Pck Boundary scan register SDBSR ⎯ ⎯ ⎯ ⎯ ⎯ Bypass register SDBPR ⎯ ⎯ ⎯ ⎯ ⎯ Table 30.
PAGE 1522
30. User Debugging Interface (H-UDI) 30.3.1 Instruction Register (SDIR) SDIR is a 16-bit read-only register that can be read from the CPU. Commands are set via the serial input pin (TDI). SDIR is initialized by TRST or in the Test-Logic-Reset state of the TAP. This register can be written to by the H-UDI, regardless of the CPU mode. Operation is not guaranteed when a reserved command is set to this register.
PAGE 1523
30. User Debugging Interface (H-UDI) Bit Bit Name Initial Value R/W Description 15 to 1 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0. 0 INTREQ 0 R/W Interrupt Request Indicates whether or not an interrupt by an H-UDI interrupt command has occurred. Clearing this bit to 0 by the CPU cancels an interrupt request. When writing 1 to this bit, the previous value is maintained. 30.3.
PAGE 1524
30. User Debugging Interface (H-UDI) Table 30.
PAGE 1525
30.
PAGE 1526
30.
PAGE 1527
30.
PAGE 1528
30.
PAGE 1529
30.
PAGE 1530
30.
PAGE 1531
30.
PAGE 1532
30.
PAGE 1533
30. User Debugging Interface (H-UDI) 30.4 Operation 30.4.1 Boundary-Scan TAP Controller (IDCODE, EXTEST, SAMPLE/PRELOAD, and BYPASS) In the H-UDI in this LSI, the boundary-scan TAP controller is separated from the TAP controller for other H-UDI function control. When the TRST is asserted (including when the power is turned on), the boundary-scan TAP controller operates and the boundary scan function specified in JTAG can be used.
PAGE 1534
30.
PAGE 1535
30. User Debugging Interface (H-UDI) 30.4.2 TAP Control Figure 30.3 shows the internal states of the TAP controller. The controller supports the state transitions specified in JTAG with the subset. • The condition of transition is the TMS value at the rising edge of TCK. • The TDI value is sampled at the rising edge of TCK and shifted at the falling edge of TCK. • The TDO value is changed at the falling edge of TCK. The TDO is in the high impedance state other than in the Shift-DR or Shift-IR state.
PAGE 1536
30. User Debugging Interface (H-UDI) 30.4.3 H-UDI Reset The H-UDI is reset by a power-on reset by the SDIR command. To reset the H-UDI, send the HUDI reset assert command from the H-UDI pin, and then send the H-UDI reset negate command (see figure 30.4). The time required between the H-UDI reset assert and H-UDI reset negate commands is the same as the time to keep the reset pin low in order to reset this LSI by a poweron reset.
PAGE 1537
30. User Debugging Interface (H-UDI) 30.4.4 H-UDI Interrupt The H-UDI interrupt function generates an interrupt by setting a command value in SDIR through the H-UDI. The H-UDI interrupt function is general exception or interrupt operation, that is, execution is branched to the address based on VBR and is returned to the branch source by the RTE instruction. In this case, the exception code stored in INTEVT is H'600. Also, the priority of the H-UDI interrupt is controlled by bits 28 to 24 in INT2PRI4.
PAGE 1538
30. User Debugging Interface (H-UDI) Rev.1.00 Jan.
PAGE 1539
31. Register List Section 31 Register List This section is a summary of the contents of the descriptions of on-chip I/O registers in the individual sections. 31.1 Register Address List The addresses of the I/O registers incorporated in the SH7785 are listed in table 31.1. The registers are grouped by functional module, and these appear in the same order as the sections of the manual. Since this is a summary, parts of the descriptions, along with the notes, have been omitted.
PAGE 1540
31. Register List Table 31.
PAGE 1541
31.
PAGE 1542
31.
PAGE 1543
31.
PAGE 1544
31.
PAGE 1545
31.
PAGE 1546
31.
PAGE 1547
31.
PAGE 1548
31.
PAGE 1549
31.
PAGE 1550
31.
PAGE 1551
31.
PAGE 1552
31.
PAGE 1553
31.
PAGE 1554
31.
PAGE 1555
31.
PAGE 1556
31.
PAGE 1557
31.
PAGE 1558
31.
PAGE 1559
31.
PAGE 1560
31.
PAGE 1561
31.
PAGE 1562
31.
PAGE 1563
31. Register List 31.2 States of the Registers in the Individual Operating Modes The states of the I/O registers incorporated in the SH7785 in the individual operating modes are listed in tables 31.2 to table 31.9. The registers are described in order of section number in this manual, and are grouped by functional module. Since this is a summary, parts of the descriptions, along with the notes, have been omitted. For details on the registers, refer to the descriptions in the corresponding sections.
PAGE 1564
31. Register List Module Name INTC Name Abbrev.
PAGE 1565
31. Register List Module Name INTC LBSC DDR2IF Power-on Manual Reset Sleep/ Reset by by Deep Sleep by PRESET Pin/ WDT/Multiple SLEEP Exception Instruction Name Abbrev.
PAGE 1566
31. Register List Module Name DDR2IF PCIC Name Abbrev.
PAGE 1567
31. Register List Module Name PCIC Name Abbrev.
PAGE 1568
31. Register List Module Name PCIC Power-on Manual Reset Sleep/ Reset by by Deep Sleep by PRESET Pin/ WDT/Multiple SLEEP Name Abbrev.
PAGE 1569
31. Register List Table 31.3 States of the Registers in the Individual Operating Modes (2) Power-on Manual Reset Sleep/ Reset by by Deep Sleep by PRESET Pin/ WDT/Multiple SLEEP Module Name Name Abbrev.
PAGE 1570
31. Register List DMAC Manual Reset Sleep/ Reset by by Deep Sleep by PRESET Pin/ WDT/Multiple SLEEP Module Name Abbrev.
PAGE 1571
31. Register List DMAC Manual Reset Sleep/ Reset by by Deep Sleep by PRESET Pin/ WDT/Multiple SLEEP Module Name Abbrev.
PAGE 1572
31. Register List Table 31.4 States of the Registers in the Individual Operating Modes (3) Power-on Module Manual Reset Sleep/ Reset by Power-on by PRESET Pin/ Reset by WDT/Multiple by SLEEP Deep Sleep Name Name Abbrev.
PAGE 1573
31. Register List Table 31.5 States of the Registers in the Individual Operating Modes (4) Power-on Manual Reset Sleep/ Reset by by Deep Sleep by PRESET Pin/ WDT/Multiple SLEEP Module Name Name Abbrev.
PAGE 1574
31.
PAGE 1575
31. Register List Module Name DU Name Abbrev.
PAGE 1576
31. Register List DU Manual Reset Sleep/ Reset by by Deep Sleep by PRESET Pin/ WDT/Multiple SLEEP Module Name Abbrev.
PAGE 1577
31. Register List Module Name DU Name Abbrev.
PAGE 1578
31. Register List DU Manual Reset Sleep/ Reset by by Deep Sleep by PRESET Pin/ WDT/Multiple SLEEP Module Name Abbrev.
PAGE 1579
31. Register List Module Name DU Name Abbrev.
PAGE 1580
31. Register List GDTA Manual Reset Sleep/ Reset by by Deep Sleep by PRESET Pin/ WDT/Multiple SLEEP Module Name Abbrev.
PAGE 1581
31. Register List Module Name GDTA SCIF Name Abbrev.
PAGE 1582
31. Register List Module Name SCIF Name Abbrev.
PAGE 1583
31. Register List Module Name SCIF SIOF Name Abbrev.
PAGE 1584
31. Register List Table 31.6 States of the Registers in the Individual Operating Modes (5) Power-on Manual Reset Sleep/ Reset by by Deep Sleep by PRESET Pin/ WDT/Multiple SLEEP Module Software Name Name Abbrev.
PAGE 1585
31. Register List Table 31.7 States of the Registers in the Individual Operating Modes (6) Power-on Manual Reset Sleep/ Reset by by Deep Sleep by PRESET Pin/ WDT/Multiple SLEEP Module Name Name Abbrev.
PAGE 1586
31. Register List MMCIF HAC Manual Reset Sleep/ Reset by by Deep Sleep by PRESET Pin/ WDT/Multiple SLEEP Module Name Abbrev.
PAGE 1587
31. Register List Power-on Manual Reset Sleep/ Reset by by Deep Sleep by PRESET Pin/ WDT/Multiple SLEEP Module Abbrev.
PAGE 1588
31. Register List Power-on Manual Reset Sleep/ Reset by by Deep Sleep by PRESET Pin/ WDT/Multiple SLEEP Module Name Name Abbrev.
PAGE 1589
31. Register List Power-on Manual Reset Sleep/ Reset by by Deep Sleep by PRESET Pin/ WDT/Multiple SLEEP Module Name Name Abbrev.
PAGE 1590
31. Register List Table 31.8 States of the Registers in the Individual Operating Modes (7) Module Power-on Manual Reset Sleep/ Reset by by Deep Sleep by PRESET Pin/ WDT/Multiple SLEEP Name Name Abbrev.
PAGE 1591
32. Electrical Characteristics Section 32 Electrical Characteristics 32.1 Absolute Maximum Ratings Table 32.1 Absolute Maximum Ratings*1, 2 Item Symbol Value Unit I/O, CPG, PCI power supply voltage VDDQ −0.3 to 4.5 V −0.3 to 1.4 V VDDQ-PLL1 VDDQ-PLL2 VDDQ-TD Internal power supply voltage VDD VDD-PLL1/2 VDDA-PLL1 DDR power supply VDD-DDR −0.3 to 2.5 V Input voltage Vin (3.3V type) −0.3 to VDDQ +0.3 V Vin (1.8V type) −0.3 to VDD-DDR +0.
PAGE 1592
32. Electrical Characteristics 32.2 DC Characteristics Table 32.2 DC Characteristics (Ta = −20 to 85/−40 to 85°C) Item Symbol Min. Typ. Max. Unit Test Conditions Power supply voltage VDDQ 3.0 3.3 3.6 V Normal mode, sleep mode, module standby mode VDD-DDR 1.7 1.8 1.9 VDD 1.0 1.1 1.2 mA Ick = 600 MHz VDDQ-PLL1/2 VDDQ-TD VDD-PLL1/2 VDDA-PLL1 Current dissipation Normal operation Vref 0.49 × 0.50 × 0.
PAGE 1593
32. Electrical Characteristics Item Input voltage Symbol Min. Typ. Max. Unit Test Conditions V PRESET, NMI, TRST VIH VDDQ × 0.9 ⎯ VDDQ +0.3 EXTAL VDDQ × 0.8 ⎯ VDDQ +0.3 ~34MHz External clock input VDDQ × 1.0 ⎯ VDDQ +0.3 34MHz~67MHz External clock input VDDQ = 3.0 to 3.6 V VIH (DC) Vref ⎯ +0.125 VDD-DDR +0.3 VIH (AC) Vref +0.2 ⎯ ⎯ VIH VDDQ × 0.6 ⎯ VDDQ +0.3 Other PCI pins VDDQ × 0.5 ⎯ VDDQ +0.3 Other input pins 2.0 ⎯ VDDQ +0.3 PRESET, NMI, TRST VIL −0.3 ⎯ VDDQ × V 0.
PAGE 1594
32. Electrical Characteristics Item Symbol Min. AC differential input voltage VID (AC) 0.5 VDD-DDR V +0.6 AC differential cross point voltage VIX (AC) VDD-DDR ⎯ × 0.5 – 0.175 VDD-DDR × 0.5 + 0.175 Input leak current |L| ⎯ ⎯ 5 μA |lin| ⎯ ⎯ 1 μA |lsti| ⎯ ⎯ 1 DDR pins Three-state All input pins leak current I/O, all output pins (off condition) Rev.1.00 Jan. 10, 2008 Page 1564 of 1658 REJ09B0261-0100 Typ. Max. Unit Item VIN = 0.5 to VDDQ −0.5 V VIN = 0.5 to VDDQ −0.
PAGE 1595
32. Electrical Characteristics Item Output voltage Symbol Min. Typ. Max. Unit Test Conditions ⎯ ⎯ V VTT ⎯ +0.603 ⎯ AUDCK, AUDSYNC, AUDATA0, AUDATA1, AUDATA2, AUDATA3 VTT ⎯ +0.603 ⎯ Other output pins 2.4 ⎯ ⎯ VDDQ = 3.0 V IOH = –2 mA ⎯ ⎯ 0.55 VDDQ = 3.0 V IOL = 4 mA DDR pins ⎯ ⎯ VTT –0.603 VTT = Vref + 0.04 V IOL = 13.4 mA AUDCK, AUDSYNC, AUDATA0, AUDATA1, AUDATA2, AUDATA3 ⎯ ⎯ VTT –0.603 Other output pins ⎯ ⎯ 0.55 PCI pins VOH DDR pins PCI pins VOL 2.4 VTT = Vref –0.
PAGE 1596
32. Electrical Characteristics Table 32.3 Permissible Output Currents Item Symbol Min. Typ. Max. Unit Permissible output low current (per pin; DDR pins) IOL ⎯ ⎯ 13.4 mA Permissible output low current (per pin; PCI pins) ⎯ ⎯ 4 Permissible output low current (per pin; other than DDR and PCI pins) ⎯ ⎯ 2 Permissible output low current (total) ΣIOL ⎯ ⎯ 120 Permissible output high current (per pin; DDR pins) −IOH ⎯ ⎯ 13.
PAGE 1597
32. Electrical Characteristics 32.3 AC Characteristics In principle, this LSI's input should be synchronous. Unless specified otherwise, ensure that the setup time and hold times for each input signal are observed. Table 32.5 Clock Timing Item Operating frequency CPU, FPU, cache, TLB Symbol Min. f Typ. Max. Unit MHz 1 603 DDR2-SDRAM bus 200 302 External bus 1 101 PCI bus DC 67 Peripheral modules 1 51 Rev.1.00 Jan.
PAGE 1598
32. Electrical Characteristics 32.3.1 Clock and Control Signal Timing Table 32.6 Clock and Control Signal Timing Item EXTAL clock input frequency Divider 1: × 1, PLL1: × 72, PLL2 in operation*4 Symbol Min. Max. Unit fEX 12 17 MHz 23 34 59 83 29 43 Divider 1: × 1, PLL1: × 36, PLL2 in operation*6 EXTAL clock input cycle time Divider 1: × 1, PLL1: × 72, PLL2 in operation*4 tEXcyc Divider 1: × 1, PLL1: × 36, 6 PLL2 in operation* Figure ns 32.
PAGE 1599
32. Electrical Characteristics Item Symbol MODE reset hold time MODE13 to MODE11, tMDRH MODE8 to MODE5 Min. Max. Unit Figure 20 ⎯ ns 32.6 MODE14, MODE10, MODE9, MODE4 to MODE0 32.4 PRESET assert time tRESW 20 ⎯ tcyc 32.4 PLL synchronization settling time tPLL 400 ⎯ μs 32.5 TRST reset hold time tTRSTRH 0 ⎯ ns 32.4 PRESET input rise time tPRr ⎯ 20 μs 32.6 PRESET input fall time tPRf ⎯ 20 μs 32.6 Notes: 1.
PAGE 1600
32. Electrical Characteristics tCKOcyc tCKOH1 VOH tCKOL1 VOH VOH 1/2VDDQ 1/2VDDQ VOL tCKOf VOL tCKOr Figure 32.2 CLKOUT Clock Output Timing (1) tCKOH2 1.5V tCKOL2 1.5V 1.5V Figure 32.3 CLKOUT Clock Output Timing (2) Rev.1.00 Jan.
PAGE 1601
32. Electrical Characteristics Oscillation settling time Internal clock VDD min VDD tRESW tOSC1 PRESET tOSCMD MODE14 MODE10 MODE9 MODE4 to MODE0 tMDRH tTRSTRH TRST CLKOUT Notes: 1. Oscillation settling time for the case when the on-chip resonator is used 2. PLL2 is operating Figure 32.4 Power-On Oscillation Settling Time EXTAL input CLKOUT output tPLL Figure 32.5 PLL Synchronization Settling Time Rev.1.00 Jan.
PAGE 1602
32. Electrical Characteristics tPRf tPRr PRESET tMDRH tMDRS MODE13 to MODE11 MODE8 to MODE5 Figure 32.6 MODE Pin Setup/Hold Timing 32.3.2 Control Signal Timing Table 32.7 Control Signal Timing Conditions: VDDQ = 3.0 to 3.6 V, VDD = 1.1 V, Ta = −20 to +85/−40 to +85°C, CL = 30 pF Item Symbol Min. Max. Unit Figure BREQ setup time* tBREQS 3 — ns 32.7 BREQ hold time tBREQH 1.
PAGE 1603
32. Electrical Characteristics CKIO tBREQH tBREQH tBREQS tBREQS BREQ tBACKD BACK tBACKD tBOFF1 A[25:0], CSn, BS, RD/WR, CE2A, CE2B, RAS, WEn, RD, CASn tBON1 Figure 32.7 Control Signal Timing Power-on reset Normal operation CLKOUT PRESET STATUS1 STATUS0 Normal Reset tSTD Figure 32.8 STATUS Pin Output Timing at Power-On Reset Rev.1.00 Jan.
PAGE 1604
32. Electrical Characteristics 32.3.3 Bus Timing Table 32.8 Bus Timing Conditions: VDDQ = 3.0 to 3.6 V, VDD = 1.1 V, Ta = −20 to +85/−40 to 85°C, CL = 30 pF Item Symbol Min. Max. Unit Address delay time tAD 1.5 6 ns BS delay time tBSD 1.5 6 ns CS delay time tCSD 1.5 6 ns R/W delay time tRWD 1.5 6 ns RD delay time tRSD 1.5 6 ns Read data setup time tRDS 2.5 ⎯ ns Read data hold time tRDH 1.5 ⎯ ns WE delay time (falling edge) tWEDF 1.
PAGE 1605
32. Electrical Characteristics T1 T2 CLKOUT tAD tAD tCSD tCSD tRWD tRWD A25 to A0 CSn RD/WR tRSD tRSD tRSD RD tRDS D31 to D0 (Read) tWED1 tRDH tWEDF tWEDF WEn tWDD tWDD tWDD D31 to D0 (Write) tBSD tBSD BS RDY tDACD DACKn (SA: IO ← memory) tDACDF DACKn (SA: IO → memory) tDACD tDACD tDACDF tDACD tDACD DACKn (DA) Legend: IO: DACK device SA: Single-address DMA transfer DA: Dual-address DMA transfer Note: DACK is configured as active-high. Figure 32.
PAGE 1606
32. Electrical Characteristics Tw T1 T2 CLKOUT tAD tAD tCSD tCSD tRWD tRWD A25 to A0 CSn RD/WR tRSD tRSD tRSD RD tRDS D31 to D0 (Read) tRDH tWED1 tWEDF tWEDF WEn tWDD tWDD tWDD D31 to D0 (Write) tBSD tBSD BS tRDYS tRDYH RDY tDACD tDACD DACKn (SA: IO ← memory) tDACD tDACDF tDACDF DACKn (SA: IO → memory) tDACD tDACD DACKn (DA) Legend: IO: DACK device SA: Single-address DMA transfer DA: Dual-address DMA transfer Note: DACK is configured as active-high. Figure 32.
PAGE 1607
32. Electrical Characteristics T1 Tw Twe T2 CLKOUT tAD tAD tCSD tCSD tRWD tRWD A25 to A0 CSn RD/WR tRSD tRSD tRSD RD tRDS D31 to D0 (Read) tRDH tWED1 tWEDF tWEDF WEn tWDD tWDD tWDD D31 to D0 (Write) tBSD tBSD BS tRDYS tRDYH RDY tDACD DACKn (SA: IO ← memory) tRDYS tRDYH tDACD tDACDF tDACD tDACDF DACKn (SA: IO → memory) tDACD tDACD DACKn (DA) Legend: IO: DACK device SA: Single-address DMA transfer DA: Dual-address DMA transfer Note: DACK is configured as active-high.
PAGE 1608
32. Electrical Characteristics TS1 T1 T2 TH1 CLKOUT tAD tAD tCSD tCSD tRWD tRWD A25 to A0 CSn RD/WR tRSD tRSD tRSD RD D31 to D0 (Read) tRDS tWED1 tWEDF WEn tWDD tRDH tWEDF tWDD tWDD D31 to D0 (Write) tBSD tBSD BS RDY tDACD tDACD tDACD DACKn (SA: IO ← memory) tDACDF DACKn (SA: IO → memory) DACKn (DA) tDACD tDACDF tDACD Legend: IO: DACK device SA: Single-address DMA transfer DA: Dual-address DMA transfer Note: DACK is configured as active-high. Figure 32.
PAGE 1609
32. Electrical Characteristics TB2 T1 TB1 TB2 TB1 TB2 TB1 T2 CLKOUT tAD tAD A25 to A5 tAD A4 to A0 tCSD tCSD tRWD tRWD CSn RD/WR tRSD tRSD tRSD RD tRDS D31 to D0 (Read) tBSD tRDH tRDS tRDH tBSD BS RDY tDACD DACKn (SA: IO ← memory) tDACD tDACD tDACD tDACD DACKn (DA) Legend: IO: DACK device SA: Single-address DMA transfer DA: Dual-address DMA transfer Note: DACK is configured as active-high. Figure 32.13 Burst ROM Bus Cycle (No Wait) Rev.1.00 Jan.
PAGE 1610
32. Electrical Characteristics T1 Tw Twe TB2 TB1 Twb TB2 TB1 Twb TB2 TB1 Twb T2 CLKOUT tAD tAD A25 to A5 tAD A4 to A0 tCSD tCSD CSn tRWD tRWD RD/WR tRSD tRSD RD tRDS D31 to D0 (Read) tRDH tRDS tRDH tBSD BS tRDYH tRDYS tRDYS tRDYH RDY DACKn (SA: IO ← memory) tDACD tRDYS tRDYH tDACD tDACD tDACD DACKn (DA) Legend: IO: DACK device SA: Single-address DMA transfer DA: Dual-address DMA transfer Note: DACK is configured as active-high. Figure 32.
PAGE 1611
32. Electrical Characteristics TS1 T1 TB2 TH1 TS1 TB1 TB2 TH1 TS1 TB1 TB2 TH1 TS1 TB1 T2 TH1 CLKOUT tAD tAD A25 to A5 tAD A4 to A0 tCSD tCSD tRWD tRWD CSn RD/WR tRSD tRSD RD D31 to D0 (Read) tRDS tBSD tRDH tRDS tRDH tBSD BS RDY DACKn (SA: IO ← memory) DACKn (DA) tDACD tDACD tDACD tDACD tDACD Legend: IO: DACK device SA: Single-address DMA transfer DA: Dual-address DMA transfer Note: DACK is configured as active-high. Figure 32.15 Burst ROM Bus Cycle (CSnWCR.
PAGE 1612
32.
PAGE 1613
32.
PAGE 1614
32.
PAGE 1615
32.
PAGE 1616
32.
PAGE 1617
32.
PAGE 1618
32.
PAGE 1619
32.
PAGE 1620
32.
PAGE 1621
32. Electrical Characteristics TS1 T1 T2 TH1 CLKOUT tAD tAD tCSD tCSD tRWD tRWD A25 to A0 CSn RD/WR tRSD tRSD tRSD RD D31 to D0 (Read) tRDS tRDH tWED1 tWED1 tWEDF WEn tBSD tBSD BS RDY tDACD tDACD DACKn (SA: IO ← memory) tDACD tDACD DACKn (DA) Legend: IO: DACK device SA: Single-address DMA transfer DA: Dual-address DMA transfer Note: DACK is configured as active-high. Figure 32.25 Memory Byte Control SRAM Bus Cycle: Basic Read Cycle (CSnWCR.IW = 0000, CSnWCR.RDS = 001, CSnWCR.
PAGE 1622
32. Electrical Characteristics 32.3.4 DBSC2 Signal Timing Table 32.9 DBSC2 Signal Timing Conditions: VDD-DDR= 1.7 to 1.9 V, Vref= 0.9 V, VDD= 1.1 V, Ta= −20 to +85/−40 to 85°C, CL= 30 pF, ODT=on), Drive Strength=Normal Item Symbol Min. Max. Unit MCK output cycle tCK 3.33 5.0 ns MCK output high-level pulse width tCH 0.45 0.55 tMCK MCK output low-level pulse width tCL 0.45 0.
PAGE 1623
32. Electrical Characteristics Item Symbol Min. Max. Write command to first MDQS delay time (Rising edge) tWDQSS WL −0.18 WL tMCK +0.18 MDQS falling edge setup time to MCK rising edge (Write) tWDSS 0.27 — tMCK MDQS falling edge hold tWDSH time to MCK rising edge (Write) 0.27 — tMCK MDQS high-level pulse width (Write) tWDQSH 0.35 0.9 tMCK MDQS low-level pulse width (Write) tWDQSL 0.35 0.9 tMCK MDQS preamble (Write) tWPRE 0.35 — tMCK MDQS postamble (write) tWPST 0.
PAGE 1624
32. Electrical Characteristics MCK0, MCK1 (solid line) MCK0, MCK1 (dotted line) t IS t IH MCKE, MCS, MRAS, MCAS, MWE, MBA[2:0], MA[14:0] t IPW Figure 32.27 Command Signal and MCK Output Clock MCK0, MCK1 (solid line) MCK0, MCK1 (dotted line) MCKE, MCS, MRAS, MCAS, MWE, MBA[2:0], MA[14:0] READ Command CL (Cas Latency) tRDQSCK (min) MDQS[3:0] (solid line) MDQS[3:0] (dotted line) tRDQSCK (Min.) tRDQSCK (min) tRDQSCK (max) MDQS[3:0] (solid line) MDQS[3:0] (dotted line) tRDQSCK (Max.
PAGE 1625
32. Electrical Characteristics tRDQSH MDQS[3:0] (solid line) MDQS[3:0] (dotted line) tRPST HiZ HiZ tRPRE tRDQSL Figure 32.29 Restriction of MDQS Input Waveform (Read) MCK0, MCK1 (solid line) MCK0, MCK1 (dotted line) MCKE, MCS, MRAS, MCAS, MWE, MBA[2:0], MA[14:0] WRITE Command WL = CL - 1 tWDQSS (min) MDQS[3:0] (solid line) MDQS[3:0] (dotted line) tWDQSS (Min.) HiZ HiZ tWDSH tWDSS tWDSH tWDSS tWDQSS (max) MDQS[3:0] (solid line) MDQS[3:0] (dotted line) tWDQSS (Max.
PAGE 1626
32. Electrical Characteristics MDQS[3:0] (solid line) MDQS[3:0] (dotted line) tWDS tWDS MDQ[31:0] MDM[3:0] tWDH tWDIPW tWDH tWDIPW Figure 32.32 MDQS and MDQ/MDM Output Waveform (Write) MDQS[3:0] (solid line) MDQS[3:0] (dotted line) HiZ HiZ tHZ MDQ[31:0] HiZ Figure 32.33 MDQ High-Impedance Time from MDQS (Write) Rev.1.00 Jan.
PAGE 1627
32. Electrical Characteristics 32.3.5 INTC Module Signal Timing Table 32.10 INTC Module Signal Timing Conditions: VDDQ= 3.0 to 3.6 V, VDD= 1.1 V, Ta= −40 to 85°C, CL= 30 pF, PLL2 on Item Symbol Min. Typ. Max. Unit Figure NMI setup time tNMIS 4 — — ns 32.34 NMI hold time tNMIH 1.5 — — ns 32.34 NMI pulse width (high level) tNMIIS 5 — — tcyc* 32.35 NMI pulse width (low level) tNMIIH 5 — — tcyc* 32.35 Edge-sense IRQ pulse width (high level) tIRQIH 5 — — tcyc* 32.
PAGE 1628
32. Electrical Characteristics tNMIIH tNMIIL tIRQIH tIRQIL NMI IRQ Figure 32.35 Interrupt Signal Input Timing (2) CLKOUT tIRQOD IRQOUT Figure 32.36 IRQOUT Timing Rev.1.00 Jan.
PAGE 1629
32. Electrical Characteristics 32.3.6 PCIC Module Signal Timing Table 32.11 PCIC Signal Timing (in PCIREQ/PCIGNT Non-Port Mode) (1) Conditions: VDDQ = 3.0 to 3.6 V, VDD = 1.1 V, Ta = –40 to 85°C, CL = 30 pF 33 MHz Pin Item PCICLK 66 MHz Symbol Min. Max. Min. Max. Unit Figure Clock period tPCICYC 30 — 15 30 ns 32.37 Clock pulse width (high) tPCIHIGH 11 — 6 — Clock pulse width (low) tPCIr 11 — 6 — Clock rise time tPCIf — 4 — 1.5 Clock fall time tNCDAD1 — 4 — 1.
PAGE 1630
32. Electrical Characteristics tPCICYC tPCIHIGH tPCILOW VH VH VH 0.5VDDQ 0.5VDDQ VL VL tPCIf tPCIr Figure 32.37 PCI Clock Input Timing 0.4VDDQ PCICLK tPCIVAL 0.4VDDQ Output delay Tri-state output tPCION Figure 32.38 PCI Output Signal Timing Rev.1.00 Jan.
PAGE 1631
32. Electrical Characteristics PCICLK 0.4VDDQ tPCISU tPCIH 0.4VDDQ Input Figure 32.39 PCI Input Signal Timing 32.3.7 DMAC Module Signal Timing Table 32.12 DMAC Module Signal Timing Conditions: VDDQ= 3.0 to 3.6 V, VDD= 1.5 V, Ta= −40 to 85°C, CL= 30 pF, PLL2 on Module Item Symbol Min. Max. Unit Figure DMAC DREQ setup time tDRQS 2.5 — ns 32.40 DREQ hold time tDRQH 1.5 — DRAK delay time tDRAKD 1.5 6 DACK delay time tDAKD 1.
PAGE 1632
32. Electrical Characteristics 32.3.8 TMU Module Signal Timing Table 32.13 TMU Module Signal Timing Conditions: VDDQ= 3.0 to 3.6 V, VDD= 1.1 V, Ta= −40 to 85°C, CL= 30 pF, PLL2 on Module Item Symbol Min. Max. Unit Figure TMU Timer clock pulse width (high) tTCLKWH 4 — tPcyc 32.41 Timer clock pulse width (low) tTCLKWL 4 — Timer clock rise time tTCLKr — 0.8 Timer clock fall time tTCLKf — 0.8 Note: tPcyc is the period of one peripheral clock (Pck) cycle.
PAGE 1633
32. Electrical Characteristics 32.3.9 SCIF Module Signal Timing Table 32.14 SCIF Module Signal Timing Conditions: VDDQ= 3.0 to 3.6 V, VDD= 1.1 V, Ta= −40 to 85°C, CL= 30 pF, PLL2 on Module Item Symbol Min. Max. Unit Figure SCIFn Input clock cycle (asynchronous) tScyc 4 — tPcyc 32.42 10 — tPcyc Input clock cycle (clock synchronous) Input clock pulse width tSCKW 0.4 0.6 tScyc Input clock rise time tSCKr — 0.8 tPcyc Input clock fall time tSCKf — 0.
PAGE 1634
32. Electrical Characteristics tScyc SCIFn_CLK tTXD tTXD SCIFn_TXD SCIFn_RXD tRXS tRXH Figure 32.43 Clock Timing in SCIF I/O Synchronous Mode Rev.1.00 Jan.
PAGE 1635
32. Electrical Characteristics 32.3.10 H-UDI Module Signal Timing Table 32.15 H-UDI Module Signal Timing Conditions: VDDQ= 3.0 to 3.6 V, VDD= 1.1 V, Ta= −40 to 85°C, CL= 30 pF, PLL2 on Item Symbol Min. Max. Unit Figure Remarks Input clock cycle tTCKcyc 50 — ns 32.44, 32.46 Input clock pulse width (high) tTCKH 15 — ns 32.
PAGE 1636
32. Electrical Characteristics RESET tASEBRKS tASEBRKH ASEBRK BRKACK Figure 32.45 RESET Hold Timing tTCKcyc TCK TDI TMS tTDIS tTDIH tTDO TDO Figure 32.46 H-UDI Data Transfer Timing tPINBRK ASEBRK Figure 32.47 Pin Break Timing Rev.1.00 Jan.
PAGE 1637
32. Electrical Characteristics 32.3.11 GPIO Signal Timing Table 32.16 GPIO Signal Timing Item Symbol Min. Max. Unit Figure GPIO output delay time tIOPD — 8 ns 32.48 GPIO input setup time tIOPS 3.5 — ns GPIO input hold time tIOPH 1.5 — ns CLKOUT tIOPD GPIO[n] (OUTPUT) tIOPS tIOPH GPIO[n] (INPUT) Figure 32.48 GPIO Signal Timing Rev.1.00 Jan.
PAGE 1638
32. Electrical Characteristics 32.3.12 HSPI Module Signal Timing Table 32.17 HSPI Module Signal Timing Item Symbol Min. Max. Unit Figure HSPI clock frequency (master) TSPICYC — Pck/8 MHz 32.
PAGE 1639
32. Electrical Characteristics 32.3.13 SIOF Module Signal Timing Table 32.18 SIOF Module Signal Timing Item Symbol Min. Max. Unit Figure SIOF_MCLK clock input cycle time tMCYC tpcyc — ns 32.50 SIOF_MCLK input high level width tMWH 0.4 × tMCYC — ns SIOF_MCLK input low level width tMWL 0.4 × tMCYC — ns SIOF_SCK clock cycle time tSICYC tpcyc — ns 32.51 to 32.55 SIOF_SCK output high level width tSWHO 0.4 × tSICYC — ns 32.51 to 32.54 SIOF_SCK output low level width tSWLO 0.
PAGE 1640
32. Electrical Characteristics tSICYC tSWHO tSWLO SIOF_SCK (Output) tFSD tFSD SIOF_SYNC (Output) tSTDD tSTDD SIOF_TXD tSRDS tSRDH SIOF_RXD Figure 32.51 SIOF Transmission/Reception Timing (Master Mode 1, Sampling on Falling Edges) tSICYC tSWLO SIOF_SCK (Output) tFSD tFSD SIOF_SYNC (Output) tSTDD tSTDD SIOF_TXD tSRDS tSRDH SIOF_RXD Figure 32.52 SIOF Transmission/Reception Timing (Master Mode 1, Sampling on Rising Edges) Rev.1.00 Jan.
PAGE 1641
32. Electrical Characteristics tSICYC tSWHO tSWLO SIOF_SCK (Output) tFSD tFSD SIOF_SYNC (Output) tSTDD tSTDD tSTDD tSTDD SIOF_TXD tSRDS tSRDH SIOF_RXD Figure 32.53 SIOF Transmission/Reception Timing (Master Mode 2, Sampling on Falling Edges) tSICYC tSWLO tSWHO SIOF_SCK (Output) tFSD tFSD SIOF_SYNC (Output) tSTDD tSTDD tSTDD tSTDD SIOF_TXD tSRDS tSRDH SIOF_RXD Figure 32.54 SIOF Transmission/Reception Timing (Master Mode 2, Sampling on Rising Edges) Rev.1.00 Jan.
PAGE 1642
32. Electrical Characteristics tSICYC tSWHI tSWLI SIOF_SCK (Output) tFSS tFSH SIOF_SYNC (Output) tSTDD tSTDD SIOF_TXD tSRDS tSRDH SIOF_RXD Figure 32.55 SIOF Transmission/Reception Timing (Slave Mode 1, Slave Mode 2) Rev.1.00 Jan.
PAGE 1643
32. Electrical Characteristics 32.3.14 MMCIF Module Signal Timing Table 32.19 MMCIF Module Signal Timing Item Symbol Min. Max. Unit Figure MMCCLK clock cycle time tMMcyc 50 — ns 32.56 MMCCLK clock high level width tMMWH 0.4 × tMmcyc — ns MMCCLK clock low level width tMMWL 0.4 × tMMcyc — ns MMCCMD output data delay time tMMTCD — 10 ns MMCCMD input data hold time tMMRCS 10 — ns MMCCMD input data setup time tMMRCH 10 — ns MMCD output data delay time tMMTDD — 10 ns 32.
PAGE 1644
32. Electrical Characteristics MMCCLK tMMRCS tMMRCH MMCCMD (Input) tMMRDS tMMRDH MMCDAT (Input) Figure 32.57 MMCIF Reception Timing (Sampling on Rising Edges) 32.3.15 HAC Interface Module Signal Timing Table 32.20 HAC Interface Module Signal Timing Item Symbol Min. Max. Unit Figure HAC_RES active low pulse width tRST_LOW 1000 — ns 32.58 HAC_SYNC active pulse width tSYN_HIGH 1000 — ns 32.59 HAC_SYNC delay time 1 tSYNCD1 — 15 ns 32.
PAGE 1645
32. Electrical Characteristics tSYN_HIGH HACn_SYNC HACn_BITCLK Figure 32.59 HAC Warm Reset Timing tICL_HIGH HACn_BITCLK tICL_LOW Figure 32.60 HAC Clock Input Timing tSDNSU HACn_BITCLK HACn_SDIN tSDNHD tSDCUTD HACn_SDOUT tSYNCD1 HACn_SYNC tSYNCD2 Figure 32.61 HAC Interface Module Signal Timing Rev.1.00 Jan.
PAGE 1646
32. Electrical Characteristics 32.3.16 SSI Interface Module Signal Timing Table 32.21 SSI Interface Module Signal Timing Item Symbol Min. Max. Unit Remarks Figure Output cycle time tOSCK 40 710 ns Output Input cycle time tISCK 80 3300 ns Input Input high level width/input low level width tIHC/tILC 30 ns Input Output high level width/output low level width TOHC/tOLC 13 ns Output SCK output rise time tRC — 60 ns Output SDATA output delay time tDTR — 50 ns Transmit 32.
PAGE 1647
32. Electrical Characteristics SSIn_SCK tDTR tHTR SSIn_WS SSIn_SDATA Figure 32.64 SSI Transmission Timing (2) SSIn_SCK tSR tHTR SSIn_WS SSIn_SDATA Figure 32.65 SSI Reception Timing (1) SSIn_SCK tSR tHTR SSIn_WS SSIn_SDATA Figure 32.66 SSI Reception Timing (2) Rev.1.00 Jan.
PAGE 1648
32. Electrical Characteristics 32.3.17 FLCTL Module Signal Timing Table 32.22 NAND-Type Flash Memory Interface Timing Item Symbol Min. Max. Unit Figure Command issue setup time tNCDS 2 × tfcyc −10 — ns 32.67, 32.71 Command issue hold time tNCDH 1.5 × tfcyc −10 — ns Data output setup time tNDOS 0.5 tfcyc −10 — ns Data output hold time tNDOH 0.5 tfcyc −10 — ns 32.67, 32.68, 32.70, 32.71 Command to address transition time 1 tNCDAD1 1.5 × tfcyc −10 — ns 32.67, 32.
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32. Electrical Characteristics FCE (Low) FCLE tNCDAD1 FALE tNCDS tNWP tNCDH FWE (High) FRE tNDOS FD7 to FD0 tNDOH Command (High) FR/B Figure 32.67 Command Issue Timing of NAND-Type Flash Memory FCE (Low) FCLE tNWC FALE tNCDAD2 tNWP tNWH tNWP tNWH tNWP tNCDAD1 FWE (High) FRE tNDOS tNDOH tNDOS tNDOH tNDOS tNDOH Address FD7 to FD0 (High) Address Address tNADRB FR/B Figure 32.68 Address Issue Timing of NAND-Type Flash Memory Rev.1.00 Jan.
PAGE 1650
32. Electrical Characteristics FCE FCLE (Low) (Low) FALE tNSCC (High) FWE tNSP tNRBDR2 tNSPH tNSP tNSP FRE tNRDS tNRDH tNRDS FD7 to FD0 tNRDS tNRDH Data tNADRB FR/B Data tNRBDR1 Figure 32.69 Data Read Timing of NAND-Type Flash Memory FCE FCLE (Low) (Low) tNWC FALE tNDWS tNWP tNWH tNWP tNWP FWE (High) FRE tNDOS tNDOH tNDOS FD7 to FD0 Data tNDOH tNDOS Data (High) FR/B Figure 32.70 Data Write Timing of NAND-Type Flash Memory Rev.1.00 Jan.
PAGE 1651
32. Electrical Characteristics FCE (Low) FCLE FALE (Low) tNCDS tNWP tNCDH tNSTS FWE tNCDSR tNSP FRE tNCDFSR tNDOS tNDOH tNRDS tNRDH FD7 to FD0 Command FR/B Status (High) Figure 32.71 Status Read Timing of NAND-Type Flash Memory Rev.1.00 Jan.
PAGE 1652
32. Electrical Characteristics 32.3.18 Display Unit Signal Timing Table 32.23 PCICLK/DCLKIN Signal Timing Conditions: VDDQ = 3.3 V ±0.3 V, Ta = -40°C to + 85°C, GND = VSSQ = 0 V Item Symbol Min. Typ. Max. Unit Figure PCICLK/DCLKIN cycle time tDICYC 20 — — ns 32.72 PCICLK/DCLKIN high level width tDCKIH 8 — — ns PCICLK/DCLKIN low level width tDCKIL 8 — — ns Table 32.24 Display Timing Conditions: VDDQ = 3.3 V ±0.3 V, Ta = –40°C to +85°C, GND = VSSQ = 0 V Item Symbol Min. Typ.
PAGE 1653
32. Electrical Characteristics Table 32.
PAGE 1654
32. Electrical Characteristics PCICLK/DCLKIN (Input) tDS tDH Display input control signal*1 (Input) Figure 32.73 Display Timing (with Respect to PCICLK/DCLKIN) tDCYC tDCKH DEVSEL/DCLKOUT (Output) tDD tDD Display output control signal*2 (Output) tDD Digital data for display*3 (Output) Figure 32.74 Display Timing (with Respect to DEVSEL/DCLKOUT) Rev.1.00 Jan.
PAGE 1655
32. Electrical Characteristics tEXHHW tEXHLW IRDY/HSYNC (Input) tEXVHW IRDY/HSYNC (Input) tOD1 tOD2 LOCK/ODDF (Input) Figure 32.75 Display Timing in TV Synchronous Mode 32.4 AC Characteristic Test Conditions The AC characteristic test conditions are as follows. DDR pin only • Input/output signal reference level MDQS: /MDQS cross point MCK: /MCK cross point Other than above: VDDQ-DDR/2 • Input pulse level: VSSQ to VDDQ-DDR • Input rise/fall time: 0.
PAGE 1656
32. Electrical Characteristics The following figure shows the output load circuit. IOL RT DUT output LSI output pin CL Reference level IOH Figure 32.76 Output Load Circuit Notes: 1. CL is the total value, including the capacitance of the test jig. The capacitance of each pin is set to 30 pF. 2. RT = 50Ω (DDR pin, AUD pin) 3. IOL = 24.5 mA (DDR pin, AUD pin) 4 mA (PC pin) 2 mA (other pins) IOH = –24.5 mA (DDR pin, AUD pin) –4 mA (PC pin) –2 mA (other pins) Rev.1.00 Jan.
PAGE 1657
Appendix Appendix A. Package Dimensions Figure A.1 Package Dimensions (436-Pin BGA) Note: The Tj (junction temperature) of this LSI becomes over 125°C. So a careful thermal design is necessary. Use a heat sink or forced air cooling to lower the Tj. Rev.1.00 Jan.
PAGE 1658
Appendix B. Mode Pin Settings The MODE14–MODE0 pin values are input in the event of a power-on reset via the PRESET pin. Note: The MODE6 pin is output state after power-on reset. Legend: H: High level input L: Low level input Table B.1 Clock Operating Modes with External Pin Combination Pin Value MODE [4:0] Pin Number Clock Operating Mode 4 3 2 1 0 OSC/ External input Frequency [MHz] Min 12 Frequency (vs.
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Appendix Table B.2 Area 0 Memory Type and Bus Width Pin Value MODE7 MODE6* MODE5 L L H H L H Note: * Table B.3 Memory Interface Bus Width L MPX interface 64 bits H Setting prohibited Setting prohibited L Setting prohibited Setting prohibited H MPX interface 32 bits L SRAM interface 64 bits H SRAM interface 8 bits L SRAM interface 16 bits H SRAM interface 32 bits The MODE6 pin is output state after power-on reset.
PAGE 1660
Appendix Table B.6 Bus Mode Pin Value MODE12 L H Table B.7 MODE11 Bus Mode L PCI host bus bridge H PCIC normal (non-host) L Local bus H Display unit Boot Address Mode Pin Value MODE13 Boot address Mode L 29-bit address mode H 32-bit address extended mode Table B.8 Mode Control Pin Value MODE14 Mode L Setting prohibited H Normal operation Table B.
PAGE 1661
Appendix C. Pin Functions C.1 Pin States Table C.
PAGE 1662
Appendix Reset Pin Name (LSI level) Pin Name (Module level) DACK0 DACK1 DACK2/ SCIF2_TXD/ MMCCMD/ SIOF_TXD DACK3/ SCIF2_SCK/ MMCDAT/ SIOF_SCK STATUS0/ DRAK0 STATUS1/ DRAK1 DRAK2/CE2A Related Module I/O Power Module Bus -on Manual Sleep Standby Release Port K1(default) GPIO I/O PI K K ⎯ K DACK0 O ⎯ O O K O Port K0 (default) GPIO I/O PI K K ⎯ K DACK1 O ⎯ O O K O DMAC DMAC Port K5 (default) GPIO I/O PI K K ⎯ K DACK2 DMAC O ⎯ O O O O SCIF2_TXD SCIF O ⎯
PAGE 1663
Appendix Reset Pin Name (LSI level) Pin Name (Module level) DREQ0 I/O Power Module Bus -on Manual Sleep Standby Release Port K3 (default) GPIO I/O PI K K ⎯ K DREQ0 I ⎯ PI/I PI/I PI/I PI/I Port K2 (default) GPIO I/O PI K K ⎯ K DREQ1 I ⎯ PI/I PI/I PI/I PI/I Port L7 (default) GPIO I/O PI K K ⎯ K DREQ2 DMAC I ⎯ PI/I PI/I PI/I PI/I INTB PCIC I ⎯ K K ⎯ K Port L6 (default) GPIO I/O PI K K ⎯ K DREQ3 DMAC I ⎯ PI/I PI/I PI/I PI/I INTC PCIC I ⎯
PAGE 1664
Appendix Reset Pin Name (LSI level) Pin Name Related (Module level) Module I/O Power Module Bus -on Manual Sleep Standby Release D[63:56]/ AD[31:24] *3 AD[31:24] PCIC I/O PZ K K ⎯ K D[63:56] LBSC I/O PZ K K ⎯ Z Port A[7:0] GPIO I/O PZ K K ⎯ K AD[23:18] PCIC I/O PZ K K ⎯ K D[55:50]/ AD[23:18] *3 D[49:48]/ AD[17:16]/ 3 DB[5:4] * D[47:44]/ AD[15:12]/ 3 DB[3:0] * D[43:40]/ AD[11:8]/ DG[5:2] *3 D[39:38]/ AD [7:6]/ 3 DG[1:0] * D[37:32]/ AD[5:0]/ DR[5:0] *3 WE[7:4]/ CBE
PAGE 1665
Appendix Reset Pin Name (LSI level) Pin Name Related (Module level) Module I/O Power Module Bus -on Manual Sleep Standby Release GNT3/ MMCCLK *3 GNT3 PCIC O PZ K K ⎯ K MMCCLK MMCIF O PZ K K K K Port E0 GPIO I/O PZ K K ⎯ K GNT[2:1] PCIC O PZ K K ⎯ K GNT[2:1] * 3 GPIO I/O PZ K K ⎯ K PCIC I/O PZ K K ⎯ K Port Q2 GPIO I/O PZ K K ⎯ K REQ3 PCIC I PZ K K ⎯ K Port E3 GPIO I/O PZ K K ⎯ K REQ[2:1] PCIC I PZ K K ⎯ K Port E1-E2 REQ0/RE
PAGE 1666
Appendix Reset Pin Name (LSI level) Pin Name (Module level) Related Module I/O Power Module Bus -on Manual Sleep Standby Release PCIRESET PCIRESET PCIC O L O K ⎯ O PERR* 3 PERR PCIC I/O PZ K K ⎯ K Port Q1 GPIO I/O PZ K K ⎯ K SERR* 3 SERR PCIC I/O PZ K K ⎯ K Port Q0 GPIO I/O PZ K K ⎯ K STOP PCIC I/O PZ K K ⎯ K CDE DU O PZ K K ⎯ K Port P4 GPIO I/O PZ K K ⎯ K TRDY PCIC I/O PZ K K ⎯ K DISP DU O PZ K K ⎯ K Port P2 GPIO I
PAGE 1667
Appendix Reset Pin Name (LSI level) Pin Name (Module level) MODE2/ IRQ/IRL6/ FD6 MODE3/ IRQ/IRL7/ FD7 MODE4/ SCIF3_TXD/ FCLE MODE5/ SIOF_MCLK MODE6/ SIOF_SYNC MODE7/ SCIF3_RXD/ FALE MODE8/ SCIF3_SCK/ FD0 Related Module I/O Power Module Bus -on Manual Sleep Standby Release MODE2 (power- CPG on reset) I I ⎯ ⎯ ⎯ ⎯ Port L2 (default) GPIO I/O ⎯ K K ⎯ K IRQ/IRL6 INTC I ⎯ I I ⎯ I FD6 FLCTL I/O ⎯ K K K K MODE3 (POWER-ON RESET) CPG I/O I ⎯ ⎯ ⎯ ⎯ Port L1 (default) GP
PAGE 1668
Appendix Reset Pin Name (LSI level) Pin Name (Module level) MDOE9/ SCIF4_TXD/ FD1 MODE10/ SCIF4_RXD/ FD2 MODE11/ SCIF4_SCK/ FD3 MODE12/ DRAK3/ CE2B Related Module I/O Power Module Bus -on Manual Sleep Standby Release MDOE9 (power- LBSC on reset) I I ⎯ ⎯ ⎯ ⎯ Port N2 (default) GPIO I/O ⎯ K K ⎯ K SCIF4_TXD SCIF O ⎯ Z O O O FD1 FLCTL I/O ⎯ K K K K MODE10 CPG (power-on reset) I I ⎯ ⎯ ⎯ ⎯ Port N1 (default) GPIO I/O ⎯ K K ⎯ K SCIF4_RXD SCIF I ⎯ I I I I
PAGE 1669
Appendix Reset Pin Name (LSI level) Pin Name (Module level) SCIF0_RTS/ HSPI_CS/ FSE SCIF0_RXD/ HSPI_RX/ FRB SCIF0_SCK/ HSPI_CLK/ FRE SCIF0_TXD/ HSPI_TX/ FWE SCIF1_RXD SCIF1_SCK SCIF1_TXD SCIF2_RXD/ SIOF_RXD SIOF_MCLK/ HAC_RES Related Module I/O Power Module Bus -on Manual Sleep Standby Release Port H3 (default) GPIO I/O PI K K ⎯ K SCIF0_RTS SCIF I/O ⎯ I K K K HSPI_CS HSPI I/O ⎯ Z K K K FSE FLCTL O ⎯ O K K k Port H1 (default) GPIO I/O PI K K ⎯ K SCIF0_RXD
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Appendix Reset Pin Name (LSI level) Pin Name (Module level) SIOF_RXD/ HAC0_SDIN/ SSI0_SCK SIOF_SCK/ HAC0_BITCLK/ SSI0_CLK SIOF_SYNC/ HAC0_SYNC/ SSI0_WS SIOF_TXD/ HAC0_SDOUT/ SSI0_SDATA HAC1_BITCLK/ SSI1_CLK SCIF5_TXD/ HAC1_SYNC/ SSI1_WS SCIF5_RXD/ HAC1_SDIN/ SSI1_SCK Related Module I/O Power Module Bus -on Manual Sleep Standby Release Port J5 (default) GPIO I/O PI K K ⎯ K SIOF_RXD SIOF I ⎯ I I I I HAC0_SDIN HAC I ⎯ I I I I SSI0_SCK SSI I/O ⎯ K K K K Port J2 (defau
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Appendix Reset Pin Name (LSI level) Pin Name (Module level) Related Module I/O Module Bus Power Manual Sleep Standby Release -on SCIF5_SCK/ HAC1_SDOUT/ SSI1_SDATA Port N6 (default) GPIO I/O PI K K ⎯ K SCIF5_SCK SCIF I/O ⎯ I K K K ASEBRK/ BRKACK TCK TRST TDI TMS TDO AUDCK AUDSYNC AUDATA[3:0] MPMD HAC1_SDOUT HAC O ⎯ O O O O SSI1_SDATA SSI I/O ⎯ I K K K ASEBRK/ BRKACK TCK TRST TDI TMS TDO AUDCK AUDSYNC AUDATA[3:0] MPMD H-UDI I/O PI PI/O PI/O ⎯ PI/O H-UDI H-UDI H-
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Appendix C.2 Handling of Unused Pins Table C.
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Appendix Pin Name (LSI level) DACK2/ SCIF2_TXD/ MMCCMD/ SIOF_TXD DACK3/ SCIF2_SCK/ MMCDAT/ SIOF_SCK STATUS0/ DRAK0 STATUS1/ DRAK1 DRAK2/CE2A DREQ0 DREQ1 DREQ2/INTB DREQ3/INTC Pin Name (Module level) Module I/O When Not in Use Port K5 (default) GPIO I/O Open DACK2 DMAC O SCIF2_TXD SCIF O MMCCMD MMCIF I/O SIOF_TXD SIOF O Port K4 (default) GPIO I/O DACK3 DMAC O SCIF2_SCK SCIF I/O MMCDAT MMCIF I/O SIOF_SCK SIOF I/O STATUS0 (default) RESET O DRAK0 DMAC O Port K7
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Appendix Pin Name (LSI level) Pin Name (Module level) Module I/O When Not in Use MCLK[1:0] MCLK[1:0] DBSC2 O Open MCLK[1:0] MCLK[1:0] DBSC2 O Open MDQS[3:0] MDQS[3:0] DBSC2 I/O Open MDQS[3:0] MDQS[3:0] DBSC2 I/O Open MDM[3:0] MDQ[3:0] DBSC2 O Open MDQ[31:0] MDQ[31:0] DBSC2 I/O Open MCKE MCKE DBSC2 O Open MCAS MCAS DBSC2 O Open MRAS MRAS DBSC2 O Open MCS MCS DBSC2 O Open MWE MWE DBSC2 O Open MODT MODT DBSC2 O Open MA[14:0] MA[14:0] DBSC2 O
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Appendix Pin Name (LSI level) D[43:40]/ AD[11:8]/ DG[5:2] D[39:38]/ AD [7:6]/ DG[1:0] D[37:32]/ AD[5:0]/ DR[5:0] WE[7:4]/ CBE [3:0] GNT0/GNTIN GNT3/MMCCLK GNT[2:1] REQ0/REQOUT REQ3 REQ[2:1] DEVSEL/ DCLKOUT Pin Name (Module level) Module I/O When Not in Use AD[11:8] PCIC I/O Open*2 D[43:40] LBSC I/O DG[5:2] DU O Port C[3:0] GPIO I/O AD[7:6] PCIC I/O D[39:38] LBSC I/O DG[1:0] DU O Port D[7:6] GPIO I/O AD[5:0] PCIC I/O D[37:32] LBSC I/O DR[5:0] DU O Port D[5:0] GPI
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Appendix Pin Name (Module level) Module I/O When Not in Use PCIFRAME PCIC I/O Open*2 VSYNC DU I/O Port P0 GPIO I/O IDSEL IDSEL PCIC I Pulled-down to VSS INTA INTA PCIC I/O Port Q4 GPIO I/O Open*2 or pulled-up to VDDQ when PCIC normal mode IRDY PCIC I/O Open*2 HSYNC DU I/O Port P1 GPIO I/O LOCK PCIC I/O ODDF DU I/O Port P3 GPIO I/O PAR PAR PCIC I/O Open*2 PCICLK/ DCLKIN PCICLK PCIC I DCLKIN DU I When the bus mode selected by MODE11 and MODE12 pins is
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Appendix Pin Name (LSI level) Pin Name (Module level) Module I/O When Not in Use TRDY/DISP TRDY PCIC I/O Open*2 DISP DU O Port P2 GPIO I/O CLKOUT CPG O CLKOUT Open CLKOUTENB CLKOUTENB CPG O Open PRESET PRESET RESET I Must be used NMI NMI INTC I Pulled-up to VDDQ MRESETOUT/ IRQOUT MRESETOUT RESET O Open IRQOUT INTC O IRQ/IRL[3:0] IRQ/IRL[3:0] INTC I Pulled-up to VDDQ MODE0/ IRQ/IRL4/ FD4 MODE0 (power-on reset) CPG I Must be used during power-on reset Por
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Appendix Pin Name (LSI level) MODE4/ SCIF3_TXD/ FCLE MODE5/ SIOF_MCLK MODE6/ SIOF_SYNC MODE7/ SCIF3_RXD/ FALE MODE8/ SCIF3_SCK/ FD0 MDOE9/ SCIF4_TXD/ FD1 MODE10/ SCIF4_RXD/ FD2 Pin Name (Module level) Module I/O When Not in Use MODE4 (power-on reset) CPG I Must be used during power-on reset Port N5 (default) GPIO I/O Open SCIF3_TXD SCIF O FCLE FLCTL O MODE5 (power-on reset) LBSC I Must be used during power-on reset SIOF_MCLK SIOF I Open MODE6 (power-on reset) LBSC I Must
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Appendix Pin Name (LSI level) MODE11/ SCIF4_SCK/ FD3 Pin Name (Module level) Module I/O When Not in Use MODE11 (power-on reset) LBSC I Must be used during power-on reset Port N0 (default) GPIO I/O Open SCIF4_SCK SCIF I/O FD3 FLCTL I/O MODE12 (power-on reset) LBSC I Must be used during power-on reset Port L0 (default) GPIO I/O Open DRAK3 DMAC O CE2B LBSC O MODE13 MMU I Must be used during power-on reset Port J0 (default) GPIO I/O Open TCLK TMU I IOIS16 LBSC I M
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Appendix Pin Name (LSI level) SCIF0_SCK/ HSPI_CLK/ FRE SCIF0_TXD/ HSPI_TX/ FWE SCIF1_RXD SCIF1_SCK SCIF1_TXD Pin Name (Module level) Module I/O When Not in Use Port H2 (default) GPIO I/O Open SCIF0_SCK SCIF I/O HSPI_CLK HSPI I/O FRE FLCTL O Port H0 (default) GPIO I/O SCIF0_TXD SCIF O HSPI_TX HSPI O FWE FLCTL O Port H6 (default) GPIO I/O SCIF1_RXD SCIF I Port H7 (default) GPIO I/O SCIF1_SCK SCIF I/O Port H5 (default) GPIO I/O SCIF1_TXD SCIF O SCIF2_RXD/ SI
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Appendix Pin Name (LSI level) SIOF_TXD/ HAC0_SDOUT/ SSI0_SDATA HAC1_BITCLK/ SSI1_CLK SCIF5_TXD/ HAC1_SYNC/ SSI1_WS SCIF5_RXD/ HAC1_SDIN/ SSI1_SCK Pin Name (Module level) Module I/O When Not in Use Port J6 (default) GPIO I/O Open SIOF_TXD SIOF O HAC0_SDOUT HAC O SSI0_SDATA SSI I/O Port J1 (default) GPIO I/O HAC1_BITCLK HAC I SSI1_CLK SSI I Port J7 (default) GPIO I/O SCIF5_TXD SCIF O HAC1_SYNC HAC O SSI1_WS SSI I/O Port N7 GPIO I/O Open Open Open SCIF5_RXD SCI
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Appendix Pin Name (LSI level) Pin Name (Module level) Module I/O When Not in Use AUDCK AUDCK H-UDI O Open AUDSYNC AUDSYNC H-UDI O Open AUDATA[3:0] AUDATA[3:0] H-UDI O Open MPMD MPMD H-UDI I Pulled-up to VDDQ Notes: Power must be supplied to each power supply pin, even when the function pin is not used. When a pin is not used, do not set the register for the pin. 1. This pin is pulled-up within this LSI after power-on reset.
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Appendix D. Turning On and Off Power Supply D.1 Turning On and Off Between Each Power Supply Series The order of the power supply between the 1.0V series power supply (VDD10: VDD and VDDPLL1 to 2 and VDDA-PLL1), the 1.8V series power supply (VDD18: VDD-DDR) and the 3.3V series power supply (VDD33: VDDQ and VDDQ-PLL1 to 2 and VDDQ-TD*) is as follows. Note: * If VDDQ-TD is connected to VDDQ.
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Appendix D.2 Power-On and Power-Off Sequences for Power Supplies with Different Potentials in DDR2-SDRAM Power Supply Backup Mode The power-on and power-off sequences for the 1.0 V power supply (VDD10 using pins VDD, VDD-PLL1, VDDA-PLL1, and VDD-PLL2), 1.8 V power supply (VDD18 using pin VDD-DDR), and 3.3 V power supply (VDD33 using pins VDDQ, VDDQ-PLL1, VDDQ-PLL2, and VDDQTD*) in DDR2-SDRAM power supply backup mode are as follows. Note: * If VDDQ-TD is connected to VDDQ.
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Appendix D.3 Turning On and Off Between the Same Power Supply Series The order of the power supply in the VDD10 series, the VDD18 series and the VDD33 series power supply is as follows. Figure D.3 is an explanation chart of VDD10. The regulation of the potential difference is the same VDD10 as the other (VDD10, VDD33).
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Appendix E. Version Registers (PVR, PRR) The SH7785 has the read-only registers which show the version of a processor core, and the version of a product. By using the value of these registers, it becomes possible to be able to distinguish the version and product of a processor from software, and to realize the scalability of the high system. Since the values of the version registers differ for every product, please refer to the hardware manual or contact Renesas Technology Corp.
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Appendix F. Product Lineup Table F.1 SH7785 Product Lineup Product Type Voltage Operating Frequency Part Number Operating Temperature SH7785 1.1 V 600 MHz R8A77850AADBG −40 to 85°C R8A77850AADBGV R8A77850ANBG R8A77850ANBGV Package 436-pin BGA 436-pin BGA (Lead Free) −20 to 85°C 436-pin BGA 436-pin BGA (Lead Free) Rev.1.00 Jan.
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Appendix Rev.1.00 Jan.
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Renesas 32-Bit RISC Microcomputer Hardware Manual SH7785 Publication Date: Rev.1.00, January 10, 2008 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp. © 2008. Renesas Technology Corp., All rights reserved. Printed in Japan.
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Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan RENESAS SALES OFFICES http://www.renesas.com Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.
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SH7785 Hardware Manual