Technical information

Section 3 Software Specifications when Using the SH72546RFCC, SH72544R, SH72543R, SH72531, and SH72531FCC
Rev. 2.00 Feb. 18, 2009 Page 35 of 94
REJ10J1938-0200
Table 3.3 Stopping Time by Memory Access (Reference)
Method Condition Stopping Time
H-UDI read/write Reading of one longword for the
internal RAM
Reading: Maximum three peripheral
clock cycles (Pφ)
Writing of one longword for the
internal RAM
Writing: Maximum two peripheral
clock cycles (Pφ)
Short break CPU clock: 160 MHz
JTAG clock: 20 MHz
Reading or writing of one byte, one
word, or one longword for the
external area
About 15 ms
7. Memory Access to the External Flash Memory Area
The emulator can download the load module to the external flash memory area (for details,
refer to section 6.21, Download Function to the Flash Memory Area, in the SH-2A, SH-2
E200F Emulator User’s Manual). Other memory write operations are enabled for the RAM
area. Therefore, an operation such as memory write or a BREAKPOINT should be set only for
the RAM area.
8. ROM Cache
For ROM cache in the MCU, the emulator operates as shown in table 3.4.